提交 0d0b8dcf 编写于 作者: J Jani Nikula

drm/i915/skl: drop workarounds for C0 revision

Pre-production hardware is not supported.
Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: NJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/ed7b784306b35fa5215b9c04de79a2bc48585503.1474034059.git.jani.nikula@intel.com
上级 a117f378
...@@ -382,8 +382,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv) ...@@ -382,8 +382,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
} }
/* WaC6DisallowByGfxPause*/ /* WaC6DisallowByGfxPause*/
if (IS_SKL_REVID(dev, 0, SKL_REVID_C0) || if (IS_BXT_REVID(dev, 0, BXT_REVID_B0))
IS_BXT_REVID(dev, 0, BXT_REVID_B0))
I915_WRITE(GEN6_GFXPAUSE, 0x30FFF); I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
if (IS_BROXTON(dev)) if (IS_BROXTON(dev))
......
...@@ -882,9 +882,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) ...@@ -882,9 +882,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_CCS_TLB_PREFETCH_ENABLE); GEN9_CCS_TLB_PREFETCH_ENABLE);
/* WaDisableMaskBasedCammingInRCC:skl,bxt */ /* WaDisableMaskBasedCammingInRCC:bxt */
if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) || if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
PIXEL_MASK_CAMMING_DISABLE); PIXEL_MASK_CAMMING_DISABLE);
......
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