提交 07e81d61 编写于 作者: T Tim Abbott 提交者: H. Peter Anvin

x86: Use section .data.page_aligned for the idt_table.

The .data.idt section is just squashed into the .data.page_aligned
output section by the linker script anyway, so it might as well be in
the .data.page_aligned section.

This eliminates all references to .data.idt on x86.
Signed-off-by: NTim Abbott <tabbott@ksplice.com>
Cc: Ingo Molnar <mingo@redhat.com>
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
上级 4ae59b91
...@@ -73,11 +73,9 @@ char ignore_fpu_irq; ...@@ -73,11 +73,9 @@ char ignore_fpu_irq;
/* /*
* The IDT has to be page-aligned to simplify the Pentium * The IDT has to be page-aligned to simplify the Pentium
* F0 0F bug workaround.. We have a special link segment * F0 0F bug workaround.
* for this.
*/ */
gate_desc idt_table[NR_VECTORS] gate_desc idt_table[NR_VECTORS] __page_aligned_data = { { { { 0, 0 } } }, };
__attribute__((__section__(".data.idt"))) = { { { { 0, 0 } } }, };
#endif #endif
DECLARE_BITMAP(used_vectors, NR_VECTORS); DECLARE_BITMAP(used_vectors, NR_VECTORS);
......
...@@ -112,7 +112,6 @@ SECTIONS ...@@ -112,7 +112,6 @@ SECTIONS
#endif #endif
PAGE_ALIGNED_DATA(PAGE_SIZE) PAGE_ALIGNED_DATA(PAGE_SIZE)
*(.data.idt)
CACHELINE_ALIGNED_DATA(CONFIG_X86_L1_CACHE_BYTES) CACHELINE_ALIGNED_DATA(CONFIG_X86_L1_CACHE_BYTES)
......
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