drm/nv41/pm: implement a second type of fanspeed pwm

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nouveau_pm.h

@@ -58,6 +58,8 @@ void *nv40_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
 void nv40_pm_clocks_set(struct drm_device *, void *);
 int nv40_pm_fanspeed_get(struct drm_device *);
 int nv40_pm_fanspeed_set(struct drm_device *, int percent);
+int nv41_pm_fanspeed_get(struct drm_device *);
+int nv41_pm_fanspeed_set(struct drm_device *, int percent);
 
 /* nv50_pm.c */
 int nv50_pm_clock_get(struct drm_device *, u32 id);

drivers/gpu/drm/nouveau/nouveau_state.c

@@ -298,6 +298,13 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
 			engine->pm.fanspeed_get	= nv40_pm_fanspeed_get;
 			engine->pm.fanspeed_set	= nv40_pm_fanspeed_set;
 			break;
+		case 0x42:
+		case 0x43:
+		case 0x47:
+		case 0x4b:
+			engine->pm.fanspeed_get	= nv41_pm_fanspeed_get;
+			engine->pm.fanspeed_set	= nv41_pm_fanspeed_set;
+			break;
 		default:
 			break;
 		}

drivers/gpu/drm/nouveau/nv40_pm.c

@@ -372,3 +372,30 @@ nv40_pm_fanspeed_set(struct drm_device *dev, int percent)
 	nv_wr32(dev, 0x0010f0, 0x80000000 | (duty << 16) | divs);
 	return 0;
 }
+
+int
+nv41_pm_fanspeed_get(struct drm_device *dev)
+{
+	u32 reg = nv_rd32(dev, 0x0015f4);
+	if (reg & 0x80000000) {
+		u32 divs = nv_rd32(dev, 0x0015f8);
+		u32 duty = (reg & 0x7fffffff);
+		if (divs && divs >= duty)
+			return ((divs - duty) * 100) / divs;
+	}
+
+	return 100;
+}
+
+int
+nv41_pm_fanspeed_set(struct drm_device *dev, int percent)
+{
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
+	struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
+	u32 divs = pm->pwm_divisor;
+	u32 duty = ((100 - percent) * divs) / 100;
+
+	nv_wr32(dev, 0x0015f8, divs);
+	nv_wr32(dev, 0x0015f4, duty | 0x80000000);
+	return 0;
+}