1.)  The DMA programs (struct pcl) are PCI-endian = little endian data
(except for the 3rd quadlet in a PCL which the controller does not
touch).  Annotate them as such.

Fix all accesses of the PCL to work with big endian CPUs also.  Not
actually tested, I only have a little endian PC to test with.  This
includes replacement of a bitfield struct pcl_status by open-coded
shift and mask operations.

2.)  The two __attribute__ ((packed)) at struct pcl are not really
required since it consists of u32/__le32 only, i.e. there will be no
padding with or without the attribute.

3.)  The received IEEE 1394 data are byteswapped by the controller from
IEEE 1394 endian = big endian to PCI endian = little endian because the
PCL_BIGENDIAN control bit is set.  Therefore annotate the DMA buffer as
a __le32 array.

Fix the one access of the DMA buffer (the check of the transaction code
of link packets) to work with big endian CPUs.  Also fix the two
accesses of the client bounce buffer (the reading of packet length).

4.)  Add a comment to the userspace ABI header that all of the data gets
out as little endian data, except for the timestamp which is CPU endian.
(We could make it little endian too, but why?  Vice versa, an ioctl
could be added to dump packet data in big endian byte order...)
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>