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    perf/x86/intel: Add mem-loads/stores support for Haswell · f9134f36
    Andi Kleen 提交于
    mem-loads is basically the same as Sandy Bridge,
    but we use a separate string for changes later.
    
    Haswell doesn't support the full precise store mode,
    so we emulate it using the "DataLA" facility.
    This allows to do everything, but for data sources we
    can only detect L1 hit or not.
    
    There is no explicit enable bit anymore, so we have
    to tie it to a perf internal only flag.
    
    The address is supported for all memory related PEBS
    events with DataLA. Instead of only logging for the
    load and store events we allow logging it for all
    (it will be simply 0 if the current event does not
    support it)
    Signed-off-by: NAndi Kleen <ak@linux.intel.com>
    Cc: Andi Kleen <ak@linux.jf.intel.com>
    Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
    Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
    Link: http://lkml.kernel.org/r/1371515812-9646-7-git-send-email-andi@firstfloor.orgSigned-off-by: NIngo Molnar <mingo@kernel.org>
    f9134f36
perf_event.h 17.7 KB