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    x86: Add a synthetic TSC_RELIABLE feature bit. · eca0cd02
    Alok Kataria 提交于
    Impact: Changes timebase calibration on Vmware.
    
    Use the synthetic TSC_RELIABLE bit to workaround virtualization anomalies.
    
    Virtual TSCs can be kept nearly in sync, but because the virtual TSC
    offset is set by software, it's not perfect.  So, the TSC
    synchronization test can fail. Even then the TSC can be used as a
    clocksource since the VMware platform exports a reliable TSC to the
    guest for timekeeping purposes. Use this bit to check if we need to
    skip the TSC sync checks.
    
    Along with this also set the CONSTANT_TSC bit when on VMware, since we
    still want to use TSC as clocksource on VM running over hardware which
    has unsynchronized TSC's (opteron's), since the hypervisor will take
    care of providing consistent TSC to the guest.
    Signed-off-by: NAlok N Kataria <akataria@vmware.com>
    Signed-off-by: NDan Hecht <dhecht@vmware.com>
    Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
    eca0cd02
tsc_sync.c 4.4 KB