The CS4271 requires its LRCLK and MCLK to be stable before its RESET
line is de-asserted. That also means that clocks cannot be changed
without putting the chip back into hardware reset, which also requires
a complete re-initialization of all registers.

One (undocumented) workaround is to assert and de-assert the PDN bit
in the MODE2 register.

This patch adds a new flag to both the DT bindings as well as to the
platform data to enable that workaround.
Signed-off-by: NDaniel Mack <zonque@gmail.com>
Acked-by: NAlexander Sverdlin <subaparts@yandex.ru>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>