The port header register set is always present for port, it is mainly
for capability, control and status of the ports that AFU connected to.

This patch implements header sub feature support. Below user interfaces
are created by this patch.

Sysfs interface:
* /sys/class/fpga_region/<regionX>/<dfl-port.x>/id
  Read-only. Port ID.

Ioctl interface:
* DFL_FPGA_PORT_RESET
  Reset the FPGA Port and its AFU.
Signed-off-by: NTim Whisonant <tim.whisonant@intel.com>
Signed-off-by: NEnno Luebbers <enno.luebbers@intel.com>
Signed-off-by: NShiva Rao <shiva.rao@intel.com>
Signed-off-by: NChristopher Rauer <christopher.rauer@intel.com>
Signed-off-by: NXiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: NWu Hao <hao.wu@intel.com>
Acked-by: NAlan Tull <atull@kernel.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>