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    powerpc/fsl_pci: Fix P2P bridge handling for MPC83xx PCIe controllers · f93611fa
    Anton Vorontsov 提交于
    It appears that we wrongly calculate dev_base for type1 config cycles.
    The thing is: we shouldn't subtract hose->first_busno because PCI core
    sets PCI primary, secondary and subordinate bus numbers, and PCIe
    controller actually takes the registers into account. So we should use
    just bus->number.
    
    Also, according to MPC8315 reference manual, primary bus number should
    always remain 0. We have PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS quirk
    in indirect_pci.c, but since 83xx is somewhat special, it doesn't use
    indirect_pci.c routines, so we have to implement the quirk specifically
    for 83xx PCIe controllers.
    Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
    Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
    f93611fa
fsl_pci.c 20.4 KB