Xilinx MDM (Microblaze Debug Module) also contains
uart interface via JTAG which is compatible with
uartlite driver. This interface is really slow
that's why timeout is setup to 1s.

Make this time delay not to be cpu speed dependent.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NPeter Korsgaard <peter@korsgaard.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>