SDHC Spec 3.0: Capabilities Register bits[15-08] are Base Clock Frequency
      1.0/2.0: Capabilities Register bits[13-08] are Base Clock Frequency
Signed-off-by: NZhangfei Gao <zgao6@marvell.com>
Cc: David Vrabel <david.vrabel@csr.com>
Cc: Matt Fleming <matt@console-pimps.org>
Cc: Michal Miroslaw <mirqus@gmail.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NChris Ball <cjb@laptop.org>