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    MIPS: Rearrange PTE bits into fixed positions. · be0c37c9
    Steven J. Hill 提交于
    This patch rearranges the PTE bits into fixed positions for R2
    and later cores. In the past, the TLB handling code did runtime
    checking of RI/XI and adjusted the shifts and rotates in order
    to fit the largest PFN value into the PTE. The checking now
    occurs when building the TLB handler, thus eliminating those
    checks. These new arrangements also define the largest possible
    PFN value that can fit in the PTE. HUGE page support is only
    available for 64-bit cores. Layouts of the PTE bits are now:
    
       64-bit, R1 or earlier:     CCC D V G [S H] M A W R P
       32-bit, R1 or earler:      CCC D V G M A W R P
       64-bit, R2 or later:       CCC D V G RI/R XI [S H] M A W P
       32-bit, R2 or later:       CCC D V G RI/R XI M A W P
    
    [ralf@linux-mips.org: Fix another build error *rant* *rant*]
    Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/9353/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
    be0c37c9
tlbex.c 63.4 KB