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    x86: optimize lock prefix switching to run less frequently · ca74a6f8
    Andi Kleen 提交于
    On VMs implemented using JITs that cache translated code changing the lock
    prefixes is a quite costly operation that forces the JIT to throw away and
    retranslate a lot of code.
    
    Previously a SMP kernel would rewrite the locks once for each CPU which
    is quite unnecessary. This patch changes the code to never switch at boot in
     the normal case (SMP kernel booting with >1 CPU) or only once for SMP kernel
    on UP.
    
    This makes a significant difference in boot up performance on AMD SimNow!
    Also I expect it to be a little faster on native systems too because a smp
    switch does a lot of text_poke()s which each synchronize the pipeline.
    
    v1->v2: Rename max_cpus
    v1->v2: Fix off by one in UP check (Thomas Gleixner)
    Signed-off-by: NAndi Kleen <ak@suse.de>
    Signed-off-by: NIngo Molnar <mingo@elte.hu>
    Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
    ca74a6f8
alternative.c 12.0 KB