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    perf: Add support for supplementary event registers · a7e3ed1e
    Andi Kleen 提交于
    Change logs against Andi's original version:
    
    - Extends perf_event_attr:config to config{,1,2} (Peter Zijlstra)
    - Fixed a major event scheduling issue. There cannot be a ref++ on an
      event that has already done ref++ once and without calling
      put_constraint() in between. (Stephane Eranian)
    - Use thread_cpumask for percore allocation. (Lin Ming)
    - Use MSR names in the extra reg lists. (Lin Ming)
    - Remove redundant "c = NULL" in intel_percore_constraints
    - Fix comment of perf_event_attr::config1
    
    Intel Nehalem/Westmere have a special OFFCORE_RESPONSE event
    that can be used to monitor any offcore accesses from a core.
    This is a very useful event for various tunings, and it's
    also needed to implement the generic LLC-* events correctly.
    
    Unfortunately this event requires programming a mask in a separate
    register. And worse this separate register is per core, not per
    CPU thread.
    
    This patch:
    
    - Teaches perf_events that OFFCORE_RESPONSE needs extra parameters.
      The extra parameters are passed by user space in the
      perf_event_attr::config1 field.
    
    - Adds support to the Intel perf_event core to schedule per
      core resources. This adds fairly generic infrastructure that
      can be also used for other per core resources.
      The basic code has is patterned after the similar AMD northbridge
      constraints code.
    
    Thanks to Stephane Eranian who pointed out some problems
    in the original version and suggested improvements.
    Signed-off-by: NAndi Kleen <ak@linux.intel.com>
    Signed-off-by: NLin Ming <ming.m.lin@intel.com>
    Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
    LKML-Reference: <1299119690-13991-2-git-send-email-ming.m.lin@intel.com>
    Signed-off-by: NIngo Molnar <mingo@elte.hu>
    a7e3ed1e
perf_event.h 31.5 KB