-
由 Gregory Herrero 提交于
Use Streaming DMA mappings to handle cache coherency of frame list and descriptor list. Cache are always flushed before controller access it or before cpu access it. Acked-by: NJohn Youn <johnyoun@synopsys.com> Signed-off-by: NGregory Herrero <gregory.herrero@intel.com> Signed-off-by: NFelipe Balbi <balbi@ti.com>
95105a99