• M
    clk: vc5: Abort clock configuration without upstream clock · 8d0ccf43
    Marek Vasut 提交于
    [ Upstream commit 2137a109a5e39c2bdccfffe65230ed3fadbaac0e ]
    
    In case the upstream clock are not set, which can happen in case the
    VC5 has no valid upstream clock, the $src variable is used uninited
    by regmap_update_bits(). Check for this condition and return -EINVAL
    in such case.
    
    Note that in case the VC5 has no valid upstream clock, the VC5 can
    not operate correctly. That is a hardware property of the VC5. The
    internal oscilator present in some VC5 models is also considered
    upstream clock.
    Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
    Cc: Alexey Firago <alexey_firago@mentor.com>
    Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
    Cc: Stephen Boyd <sboyd@kernel.org>
    Cc: linux-renesas-soc@vger.kernel.org
    [sboyd@kernel.org: Added comment about probe preventing this from
    happening in the first place]
    Signed-off-by: NStephen Boyd <sboyd@kernel.org>
    Signed-off-by: NSasha Levin <sashal@kernel.org>
    Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
    8d0ccf43
clk-versaclock5.c 26.3 KB