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    drm/exynos: added hdmi display support · d8408326
    Seung-Woo Kim 提交于
    This patch is hdmi display support for exynos drm driver.
    
    There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv
    and some low level code is already in s5p-tv and even headers for register
    define are almost same. but in this patch, we decide not to consider separated
    common code with s5p-tv.
    
    Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc.
    
    1. mixer. The piece of hardware responsible for mixing and blending multiple
    data inputs before passing it to an output device.  The mixer is capable of
    handling up to three image layers. One is the output of VP.  Other two are
    images in RGB format.  The blending factor, and layers' priority are controlled
    by mixer's registers. The output is passed to HDMI.
    
    2. vp (video processor). It is used for processing of NV12/NV21 data.  An image
    stored in RAM is accessed by DMA. The output in YCbCr444 format is send to
    mixer.
    
    3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes
    pixel data from mixer and transforms it into data frames. The output is send
    to HDMIPHY interface.
    
    4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to
    HDMI connector. Basically, it contains a PLL that produces source clock for
    mixer, vp and hdmi.
    
    5. ddc (display data channel). It is dedicated i2c channel to exchange display
    information as edid with display monitor.
    
    With plane support, exynos hdmi driver fully supports two mixer layes and vp
    layer. Also vp layer supports multi buffer plane pixel formats having non
    contigus memory spaces.
    
    In exynos drm driver, common drm_hdmi driver to interface with drm framework
    has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as
    sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls
    them. mixer controls all overlay layers in both mixer and vp.
    
    Vblank interrupts for hdmi are handled by mixer internally because drm
    framework cannot support multiple irq id. And pipe number is used to check
    which display device irq happens.
    
    History
    v2: this version
     - drm plane feature support to handle overlay layers.
     - multi buffer plane pixel format support for vp layer.
     - vp layer support
    
    RFCv1: original
     - at https://lkml.org/lkml/2011/11/4/164Signed-off-by: NSeung-Woo Kim <sw0312.kim@samsung.com>
    Signed-off-by: NInki Dae <inki.dae@samsung.com>
    Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com>
    Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
    d8408326
exynos_hdmiphy.c 1.3 KB