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    drm/nvc0/ltcg: mask off intr 0x10 · 79eee7aa
    Ben Skeggs 提交于
    NVIDIA do that at startup too on Fermi, so perhaps the heap of 0x10
    intrs we receive are normal and we can ignore them.
    
    On Kepler NVIDIA *don't* do this, but the hardware appears to come up
    with the bit masked off by default - so that's probably why :)
    
    This should silence some interrupt spam seen on Fermi+ boards.
    
    Backported patch from reworked nouveau kernel tree.
    Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
    79eee7aa
nvc0_fb.c 3.6 KB