• C
    drm/i915: HSW always use GGTT selector for secure batches · 77072258
    Chris Wilson 提交于
    gen6 and earlier conflate address space selection (ppgtt vs ggtt) with
    the security bit (i.e. only privileged batches were allowed to run from
    ggtt). From Haswell only, you are able to select the security bit
    separate from the address space - and we always requested to use ppgtt.
    This breaks the golden render state batch execution with full-ppgtt as
    that is only present in the global GTT and more generally any secure
    batch that is not colocated in the ppgtt and ggtt. So we need to
    disable the use of the ppgtt selector bit for secure batches, or else we
    hang immediately upon boot and thence after every GPU reset...
    
    v2: Only HSW differentiates between secure dispatch and ggtt, so simply
    ignore the differentiation and always use secure==ggtt.
    Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
    Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
    [danvet: Rectify commit message as noted by Chris.]
    Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    77072258
intel_ringbuffer.c 74.6 KB