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由 Nishanth Menon 提交于
SmartReflex AVS Errorgen module supplies signals to Voltage Processor. It is suggested that by disabling Errorgen module before we disable VP, we might be able to ensure lesser chances of race condition to occur in the system. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NJean Pihet <j-pihet@ti.com> Reviewed-by: NKevin Hilman <khilman@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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