The lower 7 bits of PCIEPARL are reserved.  When we write to this register,
these bits must be 0.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>