The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250.
The clock options are a fixed divided by 2 clock and the output of the
PLL itself. Add support for these new clock instances.
Signed-off-by: NKisoo Yu <ksoo.yu@samsung.com>
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
[kgene.kim@samsung.com: moved common pll stuff into s5p-clock.c]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>