• D
    drm/i915: CPT+ pch transcoder workaround · 23670b32
    Daniel Vetter 提交于
    We need to set the timing override chicken bit after fdi link training
    has completed and before we enable the transcoder. We also have to
    clear that bit again after disabling the pch transcoder.
    
    See "Graphics BSpec: vol4g North Display Engine Registers [IVB],
    Display Mode Set Sequence" and "Graphics BSpec: vol4h South Display
    Engine Registers [CPT, PPT], South Display Engine Transcoder and FDI
    Control, Transcoder Debug and DFT, TRANS_CHICKEN_2" bit 31:
    
    "Workaround : Enable the override prior to enabling the transcoder.
    Disable the override after disabling the transcoder."
    
    While at it, use the _PIPE macro for the other TRANS_DP register.
    
    v2: Keep the w/a as-is, but kill the original (but wrongly placed)
    workaround introduced in
    
    commit 3bcf603f
    Author: Jesse Barnes <jbarnes@virtuousgeek.org>
    Date:   Wed Jul 27 11:51:40 2011 -0700
    
        drm/i915: apply timing generator bug workaround on CPT and PPT
    
    and
    
    commit d4270e57
    Author: Jesse Barnes <jbarnes@virtuousgeek.org>
    Date:   Tue Oct 11 10:43:02 2011 -0700
    
        drm/i915: export a CPT mode set verification function
    
    Note that this old code has unconditionally set the w/a, which might
    explain why fdi link training sometimes silently fails, and especially
    why the auto-train did not seem to work properly.
    
    v3: Paulo Zanoni pointed out that this workaround is also required on
    the LPT PCH. And Arthur Ranyan confirmed that this workaround is
    requierd for all ports on the pch, not just DP: The important part
    is that the bit is set whenever the pch transcoder is enabled, and
    that it is _not_ set while the fdi link is trained. It is also
    important that the pch transcoder is fully disabled, i.e. we have to
    wait for bit 30 to clear before clearing the w/a bit.
    
    Hence move to workaround into enable/disable_transcoder, where the pch
    transcoder gets enabled/disabled.
    
    v4: Whitespace changes dropped.
    
    v5: Don't run the w/a on IBX, we only need it on CPT/PPT and LPT.
    
    v6:
    - resolve conflicts with Paulo's big hsw vga rework
    - s/!IBX/CPT since hsw paths are now all separate, and Paulo's patch
      to implement the equivalent w/a for LPT is already merged.
    
    Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
    Cc: Paulo Zanoni <przanoni@gmail.com>
    Cc: Arthur Ranyan <arthur.j.runyan@intel.com>
    Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v5)
    Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v5)
    Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    23670b32
intel_display.c 248.1 KB