The chip documentation on the expected TID vs eager TID parity error
bits was reversed from what was implemented in the RTL, for both
chips.  This corrects the definitions.
Signed-off-by: NDave Olson <dave.olson@qlogic.com>
Signed-off-by: NBryan O'Sullivan <bryan.osullivan@qlogic.com>
Signed-off-by: NRoland Dreier <rolandd@cisco.com>