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    MIPS: add support for hardware performance events (skeleton) · 14f70012
    Deng-Cheng Zhu 提交于
    This patch provides the skeleton of the HW perf event support. To enable
    this feature, we can not choose the SMTC kernel; Oprofile should be
    disabled; kernel performance events be selected. Then we can enable it in
    Kernel type menu.
    
    Oprofile for MIPS platforms initializes irq at arch init time. Currently
    we do not change this logic to allow PMU reservation.
    
    If a platform has EIC, we can use the irq base and perf counter irq offset
    defines for the interrupt controller in specific init_hw_perf_events().
    
    Based on this skeleton patch, the 3 different kinds of MIPS PMU, namely,
    mipsxx/loongson2/rm9000, can be supported by adding corresponding lower
    level C files at the bottom. The suggested names of these files are
    perf_event_mipsxx.c/perf_event_loongson2.c/perf_event_rm9000.c. So, for
    example, we can do this by adding "#include perf_event_mipsxx.c" at the
    bottom of perf_event.c.
    
    In addition, PMUs with 64bit counters are also considered in this patch.
    Signed-off-by: NDeng-Cheng Zhu <dengcheng.zhu@gmail.com>
    To: linux-mips@linux-mips.org
    Cc: a.p.zijlstra@chello.nl
    Cc: paulus@samba.org
    Cc: mingo@elte.hu
    Cc: acme@redhat.com
    Cc: jamie.iles@picochip.com
    Cc: ddaney@caviumnetworks.com
    Cc: matt@console-pimps.org
    Patchwork: https://patchwork.linux-mips.org/patch/1688/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
    14f70012
perf_event.h 654 字节