When doing register reads, it is possible for there to be a stale
data ready bit set which will cause subsequent reads to return
prematurely with incorrect data.  This patch fixes the issues by
ensuring stale data is cleared before starting another transaction.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NJon Smirl <jonsmirl@gmail.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>