init_64.c 65.6 KB
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/*
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 *  arch/sparc64/mm/init.c
 *
 *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */
 
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#include <linux/module.h>
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#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/initrd.h>
#include <linux/swap.h>
#include <linux/pagemap.h>
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#include <linux/poison.h>
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#include <linux/fs.h>
#include <linux/seq_file.h>
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#include <linux/kprobes.h>
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#include <linux/cache.h>
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#include <linux/sort.h>
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#include <linux/percpu.h>
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#include <linux/memblock.h>
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#include <linux/mmzone.h>
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#include <linux/gfp.h>
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#include <asm/head.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/oplib.h>
#include <asm/iommu.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>
#include <asm/dma.h>
#include <asm/starfire.h>
#include <asm/tlb.h>
#include <asm/spitfire.h>
#include <asm/sections.h>
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#include <asm/tsb.h>
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#include <asm/hypervisor.h>
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#include <asm/prom.h>
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#include <asm/mdesc.h>
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#include <asm/cpudata.h>
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#include <asm/setup.h>
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#include <asm/irq.h>
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#include "init_64.h"
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unsigned long kern_linear_pte_xor[4] __read_mostly;
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/* A bitmap, two bits for every 256MB of physical memory.  These two
 * bits determine what page size we use for kernel linear
 * translations.  They form an index into kern_linear_pte_xor[].  The
 * value in the indexed slot is XOR'd with the TLB miss virtual
 * address to form the resulting TTE.  The mapping is:
 *
 *	0	==>	4MB
 *	1	==>	256MB
 *	2	==>	2GB
 *	3	==>	16GB
 *
 * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
 * support 2GB pages, and hopefully future cpus will support the 16GB
 * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
 * if these larger page sizes are not supported by the cpu.
 *
 * It would be nice to determine this from the machine description
 * 'cpu' properties, but we need to have this table setup before the
 * MDESC is initialized.
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 */
unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];

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#ifndef CONFIG_DEBUG_PAGEALLOC
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/* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
 * Space is allocated for this right after the trap table in
 * arch/sparc64/kernel/head.S
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 */
extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
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#endif
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static unsigned long cpu_pgsz_mask;

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#define MAX_BANKS	32

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static struct linux_prom64_registers pavail[MAX_BANKS];
static int pavail_ents;
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static int cmp_p64(const void *a, const void *b)
{
	const struct linux_prom64_registers *x = a, *y = b;

	if (x->phys_addr > y->phys_addr)
		return 1;
	if (x->phys_addr < y->phys_addr)
		return -1;
	return 0;
}

static void __init read_obp_memory(const char *property,
				   struct linux_prom64_registers *regs,
				   int *num_ents)
{
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	phandle node = prom_finddevice("/memory");
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	int prop_size = prom_getproplen(node, property);
	int ents, ret, i;

	ents = prop_size / sizeof(struct linux_prom64_registers);
	if (ents > MAX_BANKS) {
		prom_printf("The machine has more %s property entries than "
			    "this kernel can support (%d).\n",
			    property, MAX_BANKS);
		prom_halt();
	}

	ret = prom_getproperty(node, property, (char *) regs, prop_size);
	if (ret == -1) {
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		prom_printf("Couldn't get %s property from /memory.\n",
				property);
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		prom_halt();
	}

	/* Sanitize what we got from the firmware, by page aligning
	 * everything.
	 */
	for (i = 0; i < ents; i++) {
		unsigned long base, size;

		base = regs[i].phys_addr;
		size = regs[i].reg_size;
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		size &= PAGE_MASK;
		if (base & ~PAGE_MASK) {
			unsigned long new_base = PAGE_ALIGN(base);

			size -= new_base - base;
			if ((long) size < 0L)
				size = 0UL;
			base = new_base;
		}
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		if (size == 0UL) {
			/* If it is empty, simply get rid of it.
			 * This simplifies the logic of the other
			 * functions that process these arrays.
			 */
			memmove(&regs[i], &regs[i + 1],
				(ents - i - 1) * sizeof(regs[0]));
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			i--;
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			ents--;
			continue;
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		}
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		regs[i].phys_addr = base;
		regs[i].reg_size = size;
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	}

	*num_ents = ents;

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	sort(regs, ents, sizeof(struct linux_prom64_registers),
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	     cmp_p64, NULL);
}
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unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
					sizeof(unsigned long)];
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EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
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/* Kernel physical address base and size in bytes.  */
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unsigned long kern_base __read_mostly;
unsigned long kern_size __read_mostly;
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/* Initial ramdisk setup */
extern unsigned long sparc_ramdisk_image64;
extern unsigned int sparc_ramdisk_image;
extern unsigned int sparc_ramdisk_size;

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struct page *mem_map_zero __read_mostly;
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EXPORT_SYMBOL(mem_map_zero);
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unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;

unsigned long sparc64_kern_pri_context __read_mostly;
unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
unsigned long sparc64_kern_sec_context __read_mostly;

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int num_kernel_image_mappings;
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#ifdef CONFIG_DEBUG_DCFLUSH
atomic_t dcpage_flushes = ATOMIC_INIT(0);
#ifdef CONFIG_SMP
atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
#endif
#endif

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inline void flush_dcache_page_impl(struct page *page)
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{
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	BUG_ON(tlb_type == hypervisor);
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#ifdef CONFIG_DEBUG_DCFLUSH
	atomic_inc(&dcpage_flushes);
#endif

#ifdef DCACHE_ALIASING_POSSIBLE
	__flush_dcache_page(page_address(page),
			    ((tlb_type == spitfire) &&
			     page_mapping(page) != NULL));
#else
	if (page_mapping(page) != NULL &&
	    tlb_type == spitfire)
		__flush_icache_page(__pa(page_address(page)));
#endif
}

#define PG_dcache_dirty		PG_arch_1
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#define PG_dcache_cpu_shift	32UL
#define PG_dcache_cpu_mask	\
	((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
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#define dcache_dirty_cpu(page) \
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	(((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
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static inline void set_dcache_dirty(struct page *page, int this_cpu)
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{
	unsigned long mask = this_cpu;
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	unsigned long non_cpu_bits;

	non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
	mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);

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	__asm__ __volatile__("1:\n\t"
			     "ldx	[%2], %%g7\n\t"
			     "and	%%g7, %1, %%g1\n\t"
			     "or	%%g1, %0, %%g1\n\t"
			     "casx	[%2], %%g7, %%g1\n\t"
			     "cmp	%%g7, %%g1\n\t"
			     "bne,pn	%%xcc, 1b\n\t"
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			     " nop"
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			     : /* no outputs */
			     : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
			     : "g1", "g7");
}

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static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
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{
	unsigned long mask = (1UL << PG_dcache_dirty);

	__asm__ __volatile__("! test_and_clear_dcache_dirty\n"
			     "1:\n\t"
			     "ldx	[%2], %%g7\n\t"
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			     "srlx	%%g7, %4, %%g1\n\t"
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			     "and	%%g1, %3, %%g1\n\t"
			     "cmp	%%g1, %0\n\t"
			     "bne,pn	%%icc, 2f\n\t"
			     " andn	%%g7, %1, %%g1\n\t"
			     "casx	[%2], %%g7, %%g1\n\t"
			     "cmp	%%g7, %%g1\n\t"
			     "bne,pn	%%xcc, 1b\n\t"
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			     " nop\n"
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			     "2:"
			     : /* no outputs */
			     : "r" (cpu), "r" (mask), "r" (&page->flags),
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			       "i" (PG_dcache_cpu_mask),
			       "i" (PG_dcache_cpu_shift)
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			     : "g1", "g7");
}

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static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
{
	unsigned long tsb_addr = (unsigned long) ent;

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	if (tlb_type == cheetah_plus || tlb_type == hypervisor)
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		tsb_addr = __pa(tsb_addr);

	__tsb_insert(tsb_addr, tag, pte);
}

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unsigned long _PAGE_ALL_SZ_BITS __read_mostly;

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static void flush_dcache(unsigned long pfn)
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{
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	struct page *page;
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	page = pfn_to_page(pfn);
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	if (page) {
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		unsigned long pg_flags;

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		pg_flags = page->flags;
		if (pg_flags & (1UL << PG_dcache_dirty)) {
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			int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
				   PG_dcache_cpu_mask);
			int this_cpu = get_cpu();

			/* This is just to optimize away some function calls
			 * in the SMP case.
			 */
			if (cpu == this_cpu)
				flush_dcache_page_impl(page);
			else
				smp_flush_dcache_page_impl(page, cpu);

			clear_dcache_dirty_cpu(page, cpu);

			put_cpu();
		}
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	}
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}

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/* mm->context.lock must be held */
static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
				    unsigned long tsb_hash_shift, unsigned long address,
				    unsigned long tte)
{
	struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
	unsigned long tag;

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	if (unlikely(!tsb))
		return;

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	tsb += ((address >> tsb_hash_shift) &
		(mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
	tag = (address >> 22UL);
	tsb_insert(tsb, tag, tte);
}

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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
static inline bool is_hugetlb_pte(pte_t pte)
{
	if ((tlb_type == hypervisor &&
	     (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
	    (tlb_type != hypervisor &&
	     (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
		return true;
	return false;
}
#endif

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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
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{
	struct mm_struct *mm;
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	unsigned long flags;
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	pte_t pte = *ptep;
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	if (tlb_type != hypervisor) {
		unsigned long pfn = pte_pfn(pte);

		if (pfn_valid(pfn))
			flush_dcache(pfn);
	}
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	mm = vma->vm_mm;
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	/* Don't insert a non-valid PTE into the TSB, we'll deadlock.  */
	if (!pte_accessible(mm, pte))
		return;

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	spin_lock_irqsave(&mm->context.lock, flags);

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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
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	if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
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		__update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
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					address, pte_val(pte));
	else
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#endif
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		__update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
					address, pte_val(pte));
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	spin_unlock_irqrestore(&mm->context.lock, flags);
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}

void flush_dcache_page(struct page *page)
{
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	struct address_space *mapping;
	int this_cpu;
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	if (tlb_type == hypervisor)
		return;

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	/* Do not bother with the expensive D-cache flush if it
	 * is merely the zero page.  The 'bigcore' testcase in GDB
	 * causes this case to run millions of times.
	 */
	if (page == ZERO_PAGE(0))
		return;

	this_cpu = get_cpu();

	mapping = page_mapping(page);
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	if (mapping && !mapping_mapped(mapping)) {
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		int dirty = test_bit(PG_dcache_dirty, &page->flags);
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		if (dirty) {
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			int dirty_cpu = dcache_dirty_cpu(page);

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			if (dirty_cpu == this_cpu)
				goto out;
			smp_flush_dcache_page_impl(page, dirty_cpu);
		}
		set_dcache_dirty(page, this_cpu);
	} else {
		/* We could delay the flush for the !page_mapping
		 * case too.  But that case is for exec env/arg
		 * pages and those are %99 certainly going to get
		 * faulted into the tlb (and thus flushed) anyways.
		 */
		flush_dcache_page_impl(page);
	}

out:
	put_cpu();
}
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EXPORT_SYMBOL(flush_dcache_page);
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void __kprobes flush_icache_range(unsigned long start, unsigned long end)
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{
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	/* Cheetah and Hypervisor platform cpus have coherent I-cache. */
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	if (tlb_type == spitfire) {
		unsigned long kaddr;

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		/* This code only runs on Spitfire cpus so this is
		 * why we can assume _PAGE_PADDR_4U.
		 */
		for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
			unsigned long paddr, mask = _PAGE_PADDR_4U;

			if (kaddr >= PAGE_OFFSET)
				paddr = kaddr & mask;
			else {
				pgd_t *pgdp = pgd_offset_k(kaddr);
				pud_t *pudp = pud_offset(pgdp, kaddr);
				pmd_t *pmdp = pmd_offset(pudp, kaddr);
				pte_t *ptep = pte_offset_kernel(pmdp, kaddr);

				paddr = pte_val(*ptep) & mask;
			}
			__flush_icache_page(paddr);
		}
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	}
}
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EXPORT_SYMBOL(flush_icache_range);
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void mmu_info(struct seq_file *m)
{
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	static const char *pgsz_strings[] = {
		"8K", "64K", "512K", "4MB", "32MB",
		"256MB", "2GB", "16GB",
	};
	int i, printed;

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	if (tlb_type == cheetah)
		seq_printf(m, "MMU Type\t: Cheetah\n");
	else if (tlb_type == cheetah_plus)
		seq_printf(m, "MMU Type\t: Cheetah+\n");
	else if (tlb_type == spitfire)
		seq_printf(m, "MMU Type\t: Spitfire\n");
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	else if (tlb_type == hypervisor)
		seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
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	else
		seq_printf(m, "MMU Type\t: ???\n");

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	seq_printf(m, "MMU PGSZs\t: ");
	printed = 0;
	for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
		if (cpu_pgsz_mask & (1UL << i)) {
			seq_printf(m, "%s%s",
				   printed ? "," : "", pgsz_strings[i]);
			printed++;
		}
	}
	seq_putc(m, '\n');

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#ifdef CONFIG_DEBUG_DCFLUSH
	seq_printf(m, "DCPageFlushes\t: %d\n",
		   atomic_read(&dcpage_flushes));
#ifdef CONFIG_SMP
	seq_printf(m, "DCPageFlushesXC\t: %d\n",
		   atomic_read(&dcpage_flushes_xcall));
#endif /* CONFIG_SMP */
#endif /* CONFIG_DEBUG_DCFLUSH */
}

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struct linux_prom_translation prom_trans[512] __read_mostly;
unsigned int prom_trans_ents __read_mostly;

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unsigned long kern_locked_tte_data;

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/* The obp translations are saved based on 8k pagesize, since obp can
 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
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 * HI_OBP_ADDRESS range are handled in ktlb.S.
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 */
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static inline int in_obp_range(unsigned long vaddr)
{
	return (vaddr >= LOW_OBP_ADDRESS &&
		vaddr < HI_OBP_ADDRESS);
}

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static int cmp_ptrans(const void *a, const void *b)
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{
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	const struct linux_prom_translation *x = a, *y = b;
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	if (x->virt > y->virt)
		return 1;
	if (x->virt < y->virt)
		return -1;
	return 0;
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}

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/* Read OBP translations property into 'prom_trans[]'.  */
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static void __init read_obp_translations(void)
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{
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	int n, node, ents, first, last, i;
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	node = prom_finddevice("/virtual-memory");
	n = prom_getproplen(node, "translations");
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	if (unlikely(n == 0 || n == -1)) {
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		prom_printf("prom_mappings: Couldn't get size.\n");
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		prom_halt();
	}
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	if (unlikely(n > sizeof(prom_trans))) {
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		prom_printf("prom_mappings: Size %d is too big.\n", n);
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		prom_halt();
	}
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	if ((n = prom_getproperty(node, "translations",
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				  (char *)&prom_trans[0],
				  sizeof(prom_trans))) == -1) {
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		prom_printf("prom_mappings: Couldn't get property.\n");
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		prom_halt();
	}
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	n = n / sizeof(struct linux_prom_translation);
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	ents = n;

	sort(prom_trans, ents, sizeof(struct linux_prom_translation),
	     cmp_ptrans, NULL);

	/* Now kick out all the non-OBP entries.  */
	for (i = 0; i < ents; i++) {
		if (in_obp_range(prom_trans[i].virt))
			break;
	}
	first = i;
	for (; i < ents; i++) {
		if (!in_obp_range(prom_trans[i].virt))
			break;
	}
	last = i;

	for (i = 0; i < (last - first); i++) {
		struct linux_prom_translation *src = &prom_trans[i + first];
		struct linux_prom_translation *dest = &prom_trans[i];

		*dest = *src;
	}
	for (; i < ents; i++) {
		struct linux_prom_translation *dest = &prom_trans[i];
		dest->virt = dest->size = dest->data = 0x0UL;
	}

	prom_trans_ents = last - first;

	if (tlb_type == spitfire) {
		/* Clear diag TTE bits. */
		for (i = 0; i < prom_trans_ents; i++)
			prom_trans[i].data &= ~0x0003fe0000000000UL;
	}
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	/* Force execute bit on.  */
	for (i = 0; i < prom_trans_ents; i++)
		prom_trans[i].data |= (tlb_type == hypervisor ?
				       _PAGE_EXEC_4V : _PAGE_EXEC_4U);
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}
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static void __init hypervisor_tlb_lock(unsigned long vaddr,
				       unsigned long pte,
				       unsigned long mmu)
{
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	unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);

	if (ret != 0) {
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		prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
583
			    "errors with %lx\n", vaddr, 0, pte, mmu, ret);
584 585
		prom_halt();
	}
586 587
}

588 589
static unsigned long kern_large_tte(unsigned long paddr);

590
static void __init remap_kernel(void)
591 592
{
	unsigned long phys_page, tte_vaddr, tte_data;
593
	int i, tlb_ent = sparc64_highest_locked_tlbent();
594

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	tte_vaddr = (unsigned long) KERNBASE;
596
	phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
597
	tte_data = kern_large_tte(phys_page);
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	kern_locked_tte_data = tte_data;

601 602
	/* Now lock us into the TLBs via Hypervisor or OBP. */
	if (tlb_type == hypervisor) {
603
		for (i = 0; i < num_kernel_image_mappings; i++) {
604 605
			hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
			hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
606 607
			tte_vaddr += 0x400000;
			tte_data += 0x400000;
608 609
		}
	} else {
610 611 612 613 614
		for (i = 0; i < num_kernel_image_mappings; i++) {
			prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
			prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
			tte_vaddr += 0x400000;
			tte_data += 0x400000;
615
		}
616
		sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
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	}
618 619 620 621 622 623
	if (tlb_type == cheetah_plus) {
		sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
					    CTX_CHEETAH_PLUS_NUC);
		sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
		sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
	}
624
}
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626

627
static void __init inherit_prom_mappings(void)
628
{
629
	/* Now fixup OBP's idea about where we really are mapped. */
630
	printk("Remapping the kernel... ");
631
	remap_kernel();
632
	printk("done.\n");
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}

void prom_world(int enter)
{
	if (!enter)
638
		set_fs(get_fs());
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639

640
	__asm__ __volatile__("flushw");
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}

void __flush_dcache_range(unsigned long start, unsigned long end)
{
	unsigned long va;

	if (tlb_type == spitfire) {
		int n = 0;

		for (va = start; va < end; va += 32) {
			spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
			if (++n >= 512)
				break;
		}
655
	} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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		start = __pa(start);
		end = __pa(end);
		for (va = start; va < end; va += 32)
			__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
					     "membar #Sync"
					     : /* no outputs */
					     : "r" (va),
					       "i" (ASI_DCACHE_INVALIDATE));
	}
}
666
EXPORT_SYMBOL(__flush_dcache_range);
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668 669 670 671 672 673 674
/* get_new_mmu_context() uses "cache + 1".  */
DEFINE_SPINLOCK(ctx_alloc_lock);
unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
#define MAX_CTX_NR	(1UL << CTX_NR_BITS)
#define CTX_BMAP_SLOTS	BITS_TO_LONGS(MAX_CTX_NR)
DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);

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/* Caller does TLB context flushing on local CPU if necessary.
 * The caller also ensures that CTX_VALID(mm->context) is false.
 *
 * We must be careful about boundary cases so that we never
 * let the user have CTX 0 (nucleus) or we ever use a CTX
 * version of zero (and thus NO_CONTEXT would not be caught
 * by version mis-match tests in mmu_context.h).
682 683
 *
 * Always invoked with interrupts disabled.
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 */
void get_new_mmu_context(struct mm_struct *mm)
{
	unsigned long ctx, new_ctx;
	unsigned long orig_pgsz_bits;
689
	int new_version;
L
Linus Torvalds 已提交
690

691
	spin_lock(&ctx_alloc_lock);
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	orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
	ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
	new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
695
	new_version = 0;
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	if (new_ctx >= (1 << CTX_NR_BITS)) {
		new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
		if (new_ctx >= ctx) {
			int i;
			new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
				CTX_FIRST_VERSION;
			if (new_ctx == 1)
				new_ctx = CTX_FIRST_VERSION;

			/* Don't call memset, for 16 entries that's just
			 * plain silly...
			 */
			mmu_context_bmap[0] = 3;
			mmu_context_bmap[1] = 0;
			mmu_context_bmap[2] = 0;
			mmu_context_bmap[3] = 0;
			for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
				mmu_context_bmap[i + 0] = 0;
				mmu_context_bmap[i + 1] = 0;
				mmu_context_bmap[i + 2] = 0;
				mmu_context_bmap[i + 3] = 0;
			}
718
			new_version = 1;
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			goto out;
		}
	}
	mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
	new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
out:
	tlb_context_cache = new_ctx;
	mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
727
	spin_unlock(&ctx_alloc_lock);
728 729 730

	if (unlikely(new_version))
		smp_new_mmu_context_version();
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}

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static int numa_enabled = 1;
static int numa_debug;

static int __init early_numa(char *p)
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737
{
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	if (!p)
		return 0;

	if (strstr(p, "off"))
		numa_enabled = 0;
743

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	if (strstr(p, "debug"))
		numa_debug = 1;
746

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747
	return 0;
748
}
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early_param("numa", early_numa);

#define numadbg(f, a...) \
do {	if (numa_debug) \
		printk(KERN_INFO f, ## a); \
} while (0)
755

756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780
static void __init find_ramdisk(unsigned long phys_base)
{
#ifdef CONFIG_BLK_DEV_INITRD
	if (sparc_ramdisk_image || sparc_ramdisk_image64) {
		unsigned long ramdisk_image;

		/* Older versions of the bootloader only supported a
		 * 32-bit physical address for the ramdisk image
		 * location, stored at sparc_ramdisk_image.  Newer
		 * SILO versions set sparc_ramdisk_image to zero and
		 * provide a full 64-bit physical address at
		 * sparc_ramdisk_image64.
		 */
		ramdisk_image = sparc_ramdisk_image;
		if (!ramdisk_image)
			ramdisk_image = sparc_ramdisk_image64;

		/* Another bootloader quirk.  The bootloader normalizes
		 * the physical address to KERNBASE, so we have to
		 * factor that back out and add in the lowest valid
		 * physical page address to get the true physical address.
		 */
		ramdisk_image -= KERNBASE;
		ramdisk_image += phys_base;

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		numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
			ramdisk_image, sparc_ramdisk_size);

784 785
		initrd_start = ramdisk_image;
		initrd_end = ramdisk_image + sparc_ramdisk_size;
786

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Yinghai Lu 已提交
787
		memblock_reserve(initrd_start, sparc_ramdisk_size);
788 789 790

		initrd_start += PAGE_OFFSET;
		initrd_end += PAGE_OFFSET;
791 792 793 794
	}
#endif
}

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struct node_mem_mask {
	unsigned long mask;
	unsigned long val;
};
static struct node_mem_mask node_masks[MAX_NUMNODES];
static int num_node_masks;

802 803
#ifdef CONFIG_NEED_MULTIPLE_NODES

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int numa_cpu_lookup_table[NR_CPUS];
cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];

struct mdesc_mblock {
	u64	base;
	u64	size;
	u64	offset; /* RA-to-PA */
};
static struct mdesc_mblock *mblocks;
static int num_mblocks;

static unsigned long ra_to_pa(unsigned long addr)
{
	int i;

	for (i = 0; i < num_mblocks; i++) {
		struct mdesc_mblock *m = &mblocks[i];

		if (addr >= m->base &&
		    addr < (m->base + m->size)) {
			addr += m->offset;
			break;
		}
	}
	return addr;
}

static int find_node(unsigned long addr)
{
	int i;

	addr = ra_to_pa(addr);
	for (i = 0; i < num_node_masks; i++) {
		struct node_mem_mask *p = &node_masks[i];

		if ((addr & p->mask) == p->val)
			return i;
	}
	return -1;
}

845
static u64 memblock_nid_range(u64 start, u64 end, int *nid)
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{
	*nid = find_node(start);
	start += PAGE_SIZE;
	while (start < end) {
		int n = find_node(start);

		if (n != *nid)
			break;
		start += PAGE_SIZE;
	}

857 858 859
	if (start > end)
		start = end;

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860 861 862 863 864
	return start;
}
#endif

/* This must be invoked after performing all of the necessary
T
Tejun Heo 已提交
865
 * memblock_set_node() calls for 'nid'.  We need to be able to get
D
David S. Miller 已提交
866
 * correct data from get_pfn_range_for_nid().
867
 */
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static void __init allocate_node_data(int nid)
{
	struct pglist_data *p;
871
	unsigned long start_pfn, end_pfn;
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David S. Miller 已提交
872
#ifdef CONFIG_NEED_MULTIPLE_NODES
873 874
	unsigned long paddr;

875
	paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
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876 877 878 879 880 881 882
	if (!paddr) {
		prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
		prom_halt();
	}
	NODE_DATA(nid) = __va(paddr);
	memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));

883
	NODE_DATA(nid)->node_id = nid;
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#endif

	p = NODE_DATA(nid);

	get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
	p->node_start_pfn = start_pfn;
	p->node_spanned_pages = end_pfn - start_pfn;
}

static void init_node_masks_nonnuma(void)
894
{
895
#ifdef CONFIG_NEED_MULTIPLE_NODES
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	int i;
897
#endif
L
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898

D
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899
	numadbg("Initializing tables for non-numa.\n");
900

D
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901 902
	node_masks[0].mask = node_masks[0].val = 0;
	num_node_masks = 1;
903

904
#ifdef CONFIG_NEED_MULTIPLE_NODES
D
David S. Miller 已提交
905 906
	for (i = 0; i < NR_CPUS; i++)
		numa_cpu_lookup_table[i] = 0;
L
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907

908
	cpumask_setall(&numa_cpumask_lookup_table[0]);
909
#endif
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}

#ifdef CONFIG_NEED_MULTIPLE_NODES
struct pglist_data *node_data[MAX_NUMNODES];

EXPORT_SYMBOL(numa_cpu_lookup_table);
EXPORT_SYMBOL(numa_cpumask_lookup_table);
EXPORT_SYMBOL(node_data);

struct mdesc_mlgroup {
	u64	node;
	u64	latency;
	u64	match;
	u64	mask;
};
static struct mdesc_mlgroup *mlgroups;
static int num_mlgroups;

static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
				   u32 cfg_handle)
{
	u64 arc;

	mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
		u64 target = mdesc_arc_target(md, arc);
		const u64 *val;

		val = mdesc_get_property(md, target,
					 "cfg-handle", NULL);
		if (val && *val == cfg_handle)
			return 0;
	}
	return -ENODEV;
}

static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
				    u32 cfg_handle)
{
	u64 arc, candidate, best_latency = ~(u64)0;

	candidate = MDESC_NODE_NULL;
	mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
		u64 target = mdesc_arc_target(md, arc);
		const char *name = mdesc_node_name(md, target);
		const u64 *val;

		if (strcmp(name, "pio-latency-group"))
			continue;

		val = mdesc_get_property(md, target, "latency", NULL);
		if (!val)
			continue;

		if (*val < best_latency) {
			candidate = target;
			best_latency = *val;
		}
	}

	if (candidate == MDESC_NODE_NULL)
		return -ENODEV;

	return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
}

int of_node_to_nid(struct device_node *dp)
{
	const struct linux_prom64_registers *regs;
	struct mdesc_handle *md;
	u32 cfg_handle;
	int count, nid;
	u64 grp;

983 984 985 986
	/* This is the right thing to do on currently supported
	 * SUN4U NUMA platforms as well, as the PCI controller does
	 * not sit behind any particular memory controller.
	 */
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David S. Miller 已提交
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	if (!mlgroups)
		return -1;

	regs = of_get_property(dp, "reg", NULL);
	if (!regs)
		return -1;

	cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;

	md = mdesc_grab();

	count = 0;
	nid = -1;
	mdesc_for_each_node_by_name(md, grp, "group") {
		if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
			nid = count;
			break;
		}
		count++;
	}

	mdesc_release(md);

	return nid;
}

1013
static void __init add_node_ranges(void)
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David S. Miller 已提交
1014
{
1015
	struct memblock_region *reg;
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1016

1017 1018
	for_each_memblock(memory, reg) {
		unsigned long size = reg->size;
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1019 1020
		unsigned long start, end;

1021
		start = reg->base;
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1022 1023 1024 1025 1026
		end = start + size;
		while (start < end) {
			unsigned long this_end;
			int nid;

1027
			this_end = memblock_nid_range(start, end, &nid);
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David S. Miller 已提交
1028

T
Tejun Heo 已提交
1029
			numadbg("Setting memblock NUMA node nid[%d] "
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1030 1031 1032
				"start[%lx] end[%lx]\n",
				nid, start, this_end);

1033 1034
			memblock_set_node(start, this_end - start,
					  &memblock.memory, nid);
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			start = this_end;
		}
	}
}

static int __init grab_mlgroups(struct mdesc_handle *md)
{
	unsigned long paddr;
	int count = 0;
	u64 node;

	mdesc_for_each_node_by_name(md, node, "memory-latency-group")
		count++;
	if (!count)
		return -ENOENT;

Y
Yinghai Lu 已提交
1051
	paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
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David S. Miller 已提交
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			  SMP_CACHE_BYTES);
	if (!paddr)
		return -ENOMEM;

	mlgroups = __va(paddr);
	num_mlgroups = count;

	count = 0;
	mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
		struct mdesc_mlgroup *m = &mlgroups[count++];
		const u64 *val;

		m->node = node;

		val = mdesc_get_property(md, node, "latency", NULL);
		m->latency = *val;
		val = mdesc_get_property(md, node, "address-match", NULL);
		m->match = *val;
		val = mdesc_get_property(md, node, "address-mask", NULL);
		m->mask = *val;

1073 1074
		numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
			"match[%llx] mask[%llx]\n",
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			count - 1, m->node, m->latency, m->match, m->mask);
	}

	return 0;
}

static int __init grab_mblocks(struct mdesc_handle *md)
{
	unsigned long paddr;
	int count = 0;
	u64 node;

	mdesc_for_each_node_by_name(md, node, "mblock")
		count++;
	if (!count)
		return -ENOENT;

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Yinghai Lu 已提交
1092
	paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
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			  SMP_CACHE_BYTES);
	if (!paddr)
		return -ENOMEM;

	mblocks = __va(paddr);
	num_mblocks = count;

	count = 0;
	mdesc_for_each_node_by_name(md, node, "mblock") {
		struct mdesc_mblock *m = &mblocks[count++];
		const u64 *val;

		val = mdesc_get_property(md, node, "base", NULL);
		m->base = *val;
		val = mdesc_get_property(md, node, "size", NULL);
		m->size = *val;
		val = mdesc_get_property(md, node,
					 "address-congruence-offset", NULL);
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		/* The address-congruence-offset property is optional.
		 * Explicity zero it be identifty this.
		 */
		if (val)
			m->offset = *val;
		else
			m->offset = 0UL;
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1120
		numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
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			count - 1, m->base, m->size, m->offset);
	}

	return 0;
}

static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
					       u64 grp, cpumask_t *mask)
{
	u64 arc;

1132
	cpumask_clear(mask);
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	mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
		u64 target = mdesc_arc_target(md, arc);
		const char *name = mdesc_node_name(md, target);
		const u64 *id;

		if (strcmp(name, "cpu"))
			continue;
		id = mdesc_get_property(md, target, "id", NULL);
1142
		if (*id < nr_cpu_ids)
1143
			cpumask_set_cpu(*id, mask);
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	}
}

static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
{
	int i;

	for (i = 0; i < num_mlgroups; i++) {
		struct mdesc_mlgroup *m = &mlgroups[i];
		if (m->node == node)
			return m;
	}
	return NULL;
}

static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
				      int index)
{
	struct mdesc_mlgroup *candidate = NULL;
	u64 arc, best_latency = ~(u64)0;
	struct node_mem_mask *n;

	mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
		u64 target = mdesc_arc_target(md, arc);
		struct mdesc_mlgroup *m = find_mlgroup(target);
		if (!m)
			continue;
		if (m->latency < best_latency) {
			candidate = m;
			best_latency = m->latency;
		}
	}
	if (!candidate)
		return -ENOENT;

	if (num_node_masks != index) {
		printk(KERN_ERR "Inconsistent NUMA state, "
		       "index[%d] != num_node_masks[%d]\n",
		       index, num_node_masks);
		return -EINVAL;
	}

	n = &node_masks[num_node_masks++];

	n->mask = candidate->mask;
	n->val = candidate->match;
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1191
	numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
D
David S. Miller 已提交
1192
		index, n->mask, n->val, candidate->latency);
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1193

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1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204
	return 0;
}

static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
					 int index)
{
	cpumask_t mask;
	int cpu;

	numa_parse_mdesc_group_cpus(md, grp, &mask);

1205
	for_each_cpu(cpu, &mask)
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David S. Miller 已提交
1206
		numa_cpu_lookup_table[cpu] = index;
1207
	cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
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	if (numa_debug) {
		printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1211
		for_each_cpu(cpu, &mask)
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1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259
			printk("%d ", cpu);
		printk("]\n");
	}

	return numa_attach_mlgroup(md, grp, index);
}

static int __init numa_parse_mdesc(void)
{
	struct mdesc_handle *md = mdesc_grab();
	int i, err, count;
	u64 node;

	node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
	if (node == MDESC_NODE_NULL) {
		mdesc_release(md);
		return -ENOENT;
	}

	err = grab_mblocks(md);
	if (err < 0)
		goto out;

	err = grab_mlgroups(md);
	if (err < 0)
		goto out;

	count = 0;
	mdesc_for_each_node_by_name(md, node, "group") {
		err = numa_parse_mdesc_group(md, node, count);
		if (err < 0)
			break;
		count++;
	}

	add_node_ranges();

	for (i = 0; i < num_node_masks; i++) {
		allocate_node_data(i);
		node_set_online(i);
	}

	err = 0;
out:
	mdesc_release(md);
	return err;
}

1260 1261 1262 1263 1264 1265 1266 1267 1268 1269
static int __init numa_parse_jbus(void)
{
	unsigned long cpu, index;

	/* NUMA node id is encoded in bits 36 and higher, and there is
	 * a 1-to-1 mapping from CPU ID to NUMA node ID.
	 */
	index = 0;
	for_each_present_cpu(cpu) {
		numa_cpu_lookup_table[cpu] = index;
1270
		cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287
		node_masks[index].mask = ~((1UL << 36UL) - 1UL);
		node_masks[index].val = cpu << 36UL;

		index++;
	}
	num_node_masks = index;

	add_node_ranges();

	for (index = 0; index < num_node_masks; index++) {
		allocate_node_data(index);
		node_set_online(index);
	}

	return 0;
}

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1288 1289
static int __init numa_parse_sun4u(void)
{
1290 1291 1292 1293 1294 1295 1296 1297
	if (tlb_type == cheetah || tlb_type == cheetah_plus) {
		unsigned long ver;

		__asm__ ("rdpr %%ver, %0" : "=r" (ver));
		if ((ver >> 32UL) == __JALAPENO_ID ||
		    (ver >> 32UL) == __SERRANO_ID)
			return numa_parse_jbus();
	}
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1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316
	return -1;
}

static int __init bootmem_init_numa(void)
{
	int err = -1;

	numadbg("bootmem_init_numa()\n");

	if (numa_enabled) {
		if (tlb_type == hypervisor)
			err = numa_parse_mdesc();
		else
			err = numa_parse_sun4u();
	}
	return err;
}

#else
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1318 1319 1320 1321 1322 1323 1324 1325 1326
static int bootmem_init_numa(void)
{
	return -1;
}

#endif

static void __init bootmem_init_nonnuma(void)
{
Y
Yinghai Lu 已提交
1327 1328
	unsigned long top_of_ram = memblock_end_of_DRAM();
	unsigned long total_ram = memblock_phys_mem_size();
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	numadbg("bootmem_init_nonnuma()\n");

	printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
	       top_of_ram, total_ram);
	printk(KERN_INFO "Memory hole size: %ldMB\n",
	       (top_of_ram - total_ram) >> 20);

	init_node_masks_nonnuma();
1338
	memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
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1339 1340 1341 1342 1343 1344 1345 1346
	allocate_node_data(0);
	node_set_online(0);
}

static unsigned long __init bootmem_init(unsigned long phys_base)
{
	unsigned long end_pfn;

Y
Yinghai Lu 已提交
1347
	end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
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1348 1349 1350 1351 1352 1353
	max_pfn = max_low_pfn = end_pfn;
	min_low_pfn = (phys_base >> PAGE_SHIFT);

	if (bootmem_init_numa() < 0)
		bootmem_init_nonnuma();

1354 1355
	/* Dump memblock with node info. */
	memblock_dump_all();
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David S. Miller 已提交
1356

1357
	/* XXX cpu notifier XXX */
1358

1359
	sparse_memory_present_with_active_regions(MAX_NUMNODES);
1360 1361
	sparse_init();

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Linus Torvalds 已提交
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	return end_pfn;
}

1365 1366 1367
static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
static int pall_ents __initdata;

1368
#ifdef CONFIG_DEBUG_PAGEALLOC
1369 1370
static unsigned long __ref kernel_map_range(unsigned long pstart,
					    unsigned long pend, pgprot_t prot)
1371 1372 1373 1374 1375 1376
{
	unsigned long vstart = PAGE_OFFSET + pstart;
	unsigned long vend = PAGE_OFFSET + pend;
	unsigned long alloc_bytes = 0UL;

	if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1377
		prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424
			    vstart, vend);
		prom_halt();
	}

	while (vstart < vend) {
		unsigned long this_end, paddr = __pa(vstart);
		pgd_t *pgd = pgd_offset_k(vstart);
		pud_t *pud;
		pmd_t *pmd;
		pte_t *pte;

		pud = pud_offset(pgd, vstart);
		if (pud_none(*pud)) {
			pmd_t *new;

			new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
			alloc_bytes += PAGE_SIZE;
			pud_populate(&init_mm, pud, new);
		}

		pmd = pmd_offset(pud, vstart);
		if (!pmd_present(*pmd)) {
			pte_t *new;

			new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
			alloc_bytes += PAGE_SIZE;
			pmd_populate_kernel(&init_mm, pmd, new);
		}

		pte = pte_offset_kernel(pmd, vstart);
		this_end = (vstart + PMD_SIZE) & PMD_MASK;
		if (this_end > vend)
			this_end = vend;

		while (vstart < this_end) {
			pte_val(*pte) = (paddr | pgprot_val(prot));

			vstart += PAGE_SIZE;
			paddr += PAGE_SIZE;
			pte++;
		}
	}

	return alloc_bytes;
}

extern unsigned int kvmap_linear_patch[1];
1425 1426
#endif /* CONFIG_DEBUG_PAGEALLOC */

1427
static void __init kpte_set_val(unsigned long index, unsigned long val)
1428
{
1429
	unsigned long *ptr = kpte_linear_bitmap;
1430

1431 1432
	val <<= ((index % (BITS_PER_LONG / 2)) * 2);
	ptr += (index / (BITS_PER_LONG / 2));
1433

1434 1435
	*ptr |= val;
}
1436

1437 1438 1439
static const unsigned long kpte_shift_min = 28; /* 256MB */
static const unsigned long kpte_shift_max = 34; /* 16GB */
static const unsigned long kpte_shift_incr = 3;
1440

1441 1442 1443 1444 1445 1446 1447
static unsigned long kpte_mark_using_shift(unsigned long start, unsigned long end,
					   unsigned long shift)
{
	unsigned long size = (1UL << shift);
	unsigned long mask = (size - 1UL);
	unsigned long remains = end - start;
	unsigned long val;
1448

1449 1450
	if (remains < size || (start & mask))
		return start;
1451

1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491
	/* VAL maps:
	 *
	 *	shift 28 --> kern_linear_pte_xor index 1
	 *	shift 31 --> kern_linear_pte_xor index 2
	 *	shift 34 --> kern_linear_pte_xor index 3
	 */
	val = ((shift - kpte_shift_min) / kpte_shift_incr) + 1;

	remains &= ~mask;
	if (shift != kpte_shift_max)
		remains = size;

	while (remains) {
		unsigned long index = start >> kpte_shift_min;

		kpte_set_val(index, val);

		start += 1UL << kpte_shift_min;
		remains -= 1UL << kpte_shift_min;
	}

	return start;
}

static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
{
	unsigned long smallest_size, smallest_mask;
	unsigned long s;

	smallest_size = (1UL << kpte_shift_min);
	smallest_mask = (smallest_size - 1UL);

	while (start < end) {
		unsigned long orig_start = start;

		for (s = kpte_shift_max; s >= kpte_shift_min; s -= kpte_shift_incr) {
			start = kpte_mark_using_shift(start, end, s);

			if (start != orig_start)
				break;
1492
		}
1493 1494 1495

		if (start == orig_start)
			start = (start + smallest_size) & ~smallest_mask;
1496 1497
	}
}
1498

1499
static void __init init_kpte_bitmap(void)
1500
{
1501
	unsigned long i;
1502 1503

	for (i = 0; i < pall_ents; i++) {
1504 1505
		unsigned long phys_start, phys_end;

1506 1507
		phys_start = pall[i].phys_addr;
		phys_end = phys_start + pall[i].reg_size;
1508 1509

		mark_kpte_bitmap(phys_start, phys_end);
1510 1511
	}
}
1512

1513 1514
static void __init kernel_physical_mapping_init(void)
{
1515
#ifdef CONFIG_DEBUG_PAGEALLOC
1516 1517 1518 1519 1520 1521 1522 1523
	unsigned long i, mem_alloced = 0UL;

	for (i = 0; i < pall_ents; i++) {
		unsigned long phys_start, phys_end;

		phys_start = pall[i].phys_addr;
		phys_end = phys_start + pall[i].reg_size;

1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534
		mem_alloced += kernel_map_range(phys_start, phys_end,
						PAGE_KERNEL);
	}

	printk("Allocated %ld bytes for kernel page tables.\n",
	       mem_alloced);

	kvmap_linear_patch[0] = 0x01000000; /* nop */
	flushi(&kvmap_linear_patch[0]);

	__flush_tlb_all();
1535
#endif
1536 1537
}

1538
#ifdef CONFIG_DEBUG_PAGEALLOC
1539 1540 1541 1542 1543 1544 1545 1546
void kernel_map_pages(struct page *page, int numpages, int enable)
{
	unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
	unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);

	kernel_map_range(phys_start, phys_end,
			 (enable ? PAGE_KERNEL : __pgprot(0)));

1547 1548 1549
	flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
			       PAGE_OFFSET + phys_end);

1550 1551 1552 1553 1554 1555 1556 1557
	/* we should perform an IPI and flush all tlbs,
	 * but that can deadlock->flush only current cpu.
	 */
	__flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
				 PAGE_OFFSET + phys_end);
}
#endif

1558 1559
unsigned long __init find_ecache_flush_span(unsigned long size)
{
1560 1561
	int i;

1562 1563 1564
	for (i = 0; i < pavail_ents; i++) {
		if (pavail[i].reg_size >= size)
			return pavail[i].phys_addr;
1565 1566
	}

1567
	return ~0UL;
1568 1569
}

1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659
unsigned long PAGE_OFFSET;
EXPORT_SYMBOL(PAGE_OFFSET);

static void __init page_offset_shift_patch_one(unsigned int *insn, unsigned long phys_bits)
{
	unsigned long final_shift;
	unsigned int val = *insn;
	unsigned int cnt;

	/* We are patching in ilog2(max_supported_phys_address), and
	 * we are doing so in a manner similar to a relocation addend.
	 * That is, we are adding the shift value to whatever value
	 * is in the shift instruction count field already.
	 */
	cnt = (val & 0x3f);
	val &= ~0x3f;

	/* If we are trying to shift >= 64 bits, clear the destination
	 * register.  This can happen when phys_bits ends up being equal
	 * to MAX_PHYS_ADDRESS_BITS.
	 */
	final_shift = (cnt + (64 - phys_bits));
	if (final_shift >= 64) {
		unsigned int rd = (val >> 25) & 0x1f;

		val = 0x80100000 | (rd << 25);
	} else {
		val |= final_shift;
	}
	*insn = val;

	__asm__ __volatile__("flush	%0"
			     : /* no outputs */
			     : "r" (insn));
}

static void __init page_offset_shift_patch(unsigned long phys_bits)
{
	extern unsigned int __page_offset_shift_patch;
	extern unsigned int __page_offset_shift_patch_end;
	unsigned int *p;

	p = &__page_offset_shift_patch;
	while (p < &__page_offset_shift_patch_end) {
		unsigned int *insn = (unsigned int *)(unsigned long)*p;

		page_offset_shift_patch_one(insn, phys_bits);

		p++;
	}
}

static void __init setup_page_offset(void)
{
	unsigned long max_phys_bits = 40;

	if (tlb_type == cheetah || tlb_type == cheetah_plus) {
		max_phys_bits = 42;
	} else if (tlb_type == hypervisor) {
		switch (sun4v_chip_type) {
		case SUN4V_CHIP_NIAGARA1:
		case SUN4V_CHIP_NIAGARA2:
			max_phys_bits = 39;
			break;
		case SUN4V_CHIP_NIAGARA3:
			max_phys_bits = 43;
			break;
		case SUN4V_CHIP_NIAGARA4:
		case SUN4V_CHIP_NIAGARA5:
		case SUN4V_CHIP_SPARC64X:
		default:
			max_phys_bits = 47;
			break;
		}
	}

	if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
		prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
			    max_phys_bits);
		prom_halt();
	}

	PAGE_OFFSET = PAGE_OFFSET_BY_BITS(max_phys_bits);

	pr_info("PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
		PAGE_OFFSET, max_phys_bits);

	page_offset_shift_patch(max_phys_bits);
}

1660 1661
static void __init tsb_phys_patch(void)
{
1662
	struct tsb_ldquad_phys_patch_entry *pquad;
1663 1664
	struct tsb_phys_patch_entry *p;

1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680
	pquad = &__tsb_ldquad_phys_patch;
	while (pquad < &__tsb_ldquad_phys_patch_end) {
		unsigned long addr = pquad->addr;

		if (tlb_type == hypervisor)
			*(unsigned int *) addr = pquad->sun4v_insn;
		else
			*(unsigned int *) addr = pquad->sun4u_insn;
		wmb();
		__asm__ __volatile__("flush	%0"
				     : /* no outputs */
				     : "r" (addr));

		pquad++;
	}

1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694
	p = &__tsb_phys_patch;
	while (p < &__tsb_phys_patch_end) {
		unsigned long addr = p->addr;

		*(unsigned int *) addr = p->insn;
		wmb();
		__asm__ __volatile__("flush	%0"
				     : /* no outputs */
				     : "r" (addr));

		p++;
	}
}

1695
/* Don't mark as init, we give this to the Hypervisor.  */
1696 1697 1698 1699 1700 1701
#ifndef CONFIG_DEBUG_PAGEALLOC
#define NUM_KTSB_DESCR	2
#else
#define NUM_KTSB_DESCR	1
#endif
static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1702 1703
extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];

1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730
static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
{
	pa >>= KTSB_PHYS_SHIFT;

	while (start < end) {
		unsigned int *ia = (unsigned int *)(unsigned long)*start;

		ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
		__asm__ __volatile__("flush	%0" : : "r" (ia));

		ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
		__asm__ __volatile__("flush	%0" : : "r" (ia + 1));

		start++;
	}
}

static void ktsb_phys_patch(void)
{
	extern unsigned int __swapper_tsb_phys_patch;
	extern unsigned int __swapper_tsb_phys_patch_end;
	unsigned long ktsb_pa;

	ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
	patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
			    &__swapper_tsb_phys_patch_end, ktsb_pa);
#ifndef CONFIG_DEBUG_PAGEALLOC
1731 1732 1733
	{
	extern unsigned int __swapper_4m_tsb_phys_patch;
	extern unsigned int __swapper_4m_tsb_phys_patch_end;
1734 1735 1736 1737
	ktsb_pa = (kern_base +
		   ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
	patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
			    &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1738
	}
1739 1740 1741
#endif
}

1742 1743 1744 1745
static void __init sun4v_ktsb_init(void)
{
	unsigned long ktsb_pa;

1746
	/* First KTSB for PAGE_SIZE mappings.  */
1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769
	ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);

	switch (PAGE_SIZE) {
	case 8 * 1024:
	default:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
		break;

	case 64 * 1024:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
		break;

	case 512 * 1024:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
		break;

	case 4 * 1024 * 1024:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
		break;
1770
	}
1771

1772
	ktsb_descr[0].assoc = 1;
1773 1774 1775 1776 1777
	ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
	ktsb_descr[0].ctx_idx = 0;
	ktsb_descr[0].tsb_base = ktsb_pa;
	ktsb_descr[0].resv = 0;

1778
#ifndef CONFIG_DEBUG_PAGEALLOC
1779
	/* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
1780 1781 1782 1783
	ktsb_pa = (kern_base +
		   ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));

	ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1784 1785 1786 1787 1788
	ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
				    HV_PGSZ_MASK_256MB |
				    HV_PGSZ_MASK_2GB |
				    HV_PGSZ_MASK_16GB) &
				   cpu_pgsz_mask);
1789 1790 1791 1792 1793
	ktsb_descr[1].assoc = 1;
	ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
	ktsb_descr[1].ctx_idx = 0;
	ktsb_descr[1].tsb_base = ktsb_pa;
	ktsb_descr[1].resv = 0;
1794
#endif
1795 1796
}

1797
void sun4v_ktsb_register(void)
1798
{
1799
	unsigned long pa, ret;
1800 1801 1802

	pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);

1803 1804 1805 1806 1807 1808
	ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
	if (ret != 0) {
		prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
			    "errors with %lx\n", pa, ret);
		prom_halt();
	}
1809 1810
}

1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824
static void __init sun4u_linear_pte_xor_finalize(void)
{
#ifndef CONFIG_DEBUG_PAGEALLOC
	/* This is where we would add Panther support for
	 * 32MB and 256MB pages.
	 */
#endif
}

static void __init sun4v_linear_pte_xor_finalize(void)
{
#ifndef CONFIG_DEBUG_PAGEALLOC
	if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
		kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1825
			PAGE_OFFSET;
1826 1827 1828 1829 1830 1831 1832 1833
		kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
					   _PAGE_P_4V | _PAGE_W_4V);
	} else {
		kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
	}

	if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
		kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1834
			PAGE_OFFSET;
1835 1836 1837 1838 1839 1840 1841 1842
		kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
					   _PAGE_P_4V | _PAGE_W_4V);
	} else {
		kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
	}

	if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
		kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1843
			PAGE_OFFSET;
1844 1845 1846 1847 1848 1849 1850 1851
		kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
					   _PAGE_P_4V | _PAGE_W_4V);
	} else {
		kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
	}
#endif
}

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1852 1853 1854
/* paging_init() sets up the page tables */

static unsigned long last_valid_pfn;
1855
pgd_t swapper_pg_dir[PTRS_PER_PGD];
L
Linus Torvalds 已提交
1856

1857 1858 1859
static void sun4u_pgprot_init(void);
static void sun4v_pgprot_init(void);

L
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1860 1861
void __init paging_init(void)
{
D
David S. Miller 已提交
1862
	unsigned long end_pfn, shift, phys_base;
1863
	unsigned long real_end, i;
1864
	int node;
1865

1866 1867
	setup_page_offset();

1868 1869 1870 1871 1872 1873 1874 1875
	/* These build time checkes make sure that the dcache_dirty_cpu()
	 * page->flags usage will work.
	 *
	 * When a page gets marked as dcache-dirty, we store the
	 * cpu number starting at bit 32 in the page->flags.  Also,
	 * functions like clear_dcache_dirty_cpu use the cpu mask
	 * in 13-bit signed-immediate instruction fields.
	 */
1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887

	/*
	 * Page flags must not reach into upper 32 bits that are used
	 * for the cpu number
	 */
	BUILD_BUG_ON(NR_PAGEFLAGS > 32);

	/*
	 * The bit fields placed in the high range must not reach below
	 * the 32 bit boundary. Otherwise we cannot place the cpu field
	 * at the 32 bit boundary.
	 */
1888
	BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1889 1890
		ilog2(roundup_pow_of_two(NR_CPUS)) > 32);

1891 1892
	BUILD_BUG_ON(NR_CPUS > 4096);

1893
	kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
1894 1895
	kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;

1896
	/* Invalidate both kernel TSBs.  */
1897
	memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1898
#ifndef CONFIG_DEBUG_PAGEALLOC
1899
	memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1900
#endif
1901

1902 1903 1904 1905 1906
	if (tlb_type == hypervisor)
		sun4v_pgprot_init();
	else
		sun4u_pgprot_init();

1907
	if (tlb_type == cheetah_plus ||
1908
	    tlb_type == hypervisor) {
1909
		tsb_phys_patch();
1910 1911
		ktsb_phys_patch();
	}
1912

1913
	if (tlb_type == hypervisor)
1914 1915
		sun4v_patch_tlb_handlers();

1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926
	/* Find available physical memory...
	 *
	 * Read it twice in order to work around a bug in openfirmware.
	 * The call to grab this table itself can cause openfirmware to
	 * allocate memory, which in turn can take away some space from
	 * the list of available memory.  Reading it twice makes sure
	 * we really do get the final value.
	 */
	read_obp_translations();
	read_obp_memory("reg", &pall[0], &pall_ents);
	read_obp_memory("available", &pavail[0], &pavail_ents);
1927
	read_obp_memory("available", &pavail[0], &pavail_ents);
1928 1929

	phys_base = 0xffffffffffffffffUL;
1930
	for (i = 0; i < pavail_ents; i++) {
1931
		phys_base = min(phys_base, pavail[i].phys_addr);
Y
Yinghai Lu 已提交
1932
		memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
1933 1934
	}

Y
Yinghai Lu 已提交
1935
	memblock_reserve(kern_base, kern_size);
1936

1937 1938
	find_ramdisk(phys_base);

Y
Yinghai Lu 已提交
1939
	memblock_enforce_memory_limit(cmdline_memory_size);
1940

1941
	memblock_allow_resize();
Y
Yinghai Lu 已提交
1942
	memblock_dump_all();
1943

L
Linus Torvalds 已提交
1944 1945
	set_bit(0, mmu_context_bmap);

1946 1947
	shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);

L
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1948
	real_end = (unsigned long)_end;
1949
	num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
1950 1951
	printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
	       num_kernel_image_mappings);
1952 1953

	/* Set kernel pgd to upper alias so physical page computations
L
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1954 1955 1956 1957
	 * work.
	 */
	init_mm.pgd += ((shift) / (sizeof(pgd_t)));
	
1958
	memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
L
Linus Torvalds 已提交
1959 1960 1961

	/* Now can init the kernel/bad page tables. */
	pud_set(pud_offset(&swapper_pg_dir[0], 0),
1962
		swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
L
Linus Torvalds 已提交
1963
	
1964
	inherit_prom_mappings();
1965
	
1966 1967
	init_kpte_bitmap();

1968 1969
	/* Ok, we can use our TLB miss and window trap handlers safely.  */
	setup_tba();
L
Linus Torvalds 已提交
1970

1971
	__flush_tlb_all();
1972

1973
	prom_build_devicetree();
1974
	of_populate_present_mask();
1975 1976 1977
#ifndef CONFIG_SMP
	of_fill_in_cpu_data();
#endif
1978

1979
	if (tlb_type == hypervisor) {
1980
		sun4v_mdesc_init();
1981
		mdesc_populate_present_mask(cpu_all_mask);
1982 1983 1984
#ifndef CONFIG_SMP
		mdesc_fill_in_cpu_data(cpu_all_mask);
#endif
1985
		mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
1986 1987 1988 1989 1990

		sun4v_linear_pte_xor_finalize();

		sun4v_ktsb_init();
		sun4v_ktsb_register();
1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001
	} else {
		unsigned long impl, ver;

		cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
				 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);

		__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
		impl = ((ver >> 32) & 0xffff);
		if (impl == PANTHER_IMPL)
			cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
					  HV_PGSZ_MASK_256MB);
2002 2003

		sun4u_linear_pte_xor_finalize();
2004
	}
2005

2006 2007 2008 2009 2010 2011 2012 2013 2014
	/* Flush the TLBs and the 4M TSB so that the updated linear
	 * pte XOR settings are realized for all mappings.
	 */
	__flush_tlb_all();
#ifndef CONFIG_DEBUG_PAGEALLOC
	memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
#endif
	__flush_tlb_all();

2015 2016 2017
	/* Setup bootmem... */
	last_valid_pfn = end_pfn = bootmem_init(phys_base);

D
David S. Miller 已提交
2018 2019 2020 2021 2022
	/* Once the OF device tree and MDESC have been setup, we know
	 * the list of possible cpus.  Therefore we can allocate the
	 * IRQ stacks.
	 */
	for_each_possible_cpu(i) {
2023
		node = cpu_to_node(i);
2024 2025 2026 2027 2028 2029 2030

		softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
							THREAD_SIZE,
							THREAD_SIZE, 0);
		hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
							THREAD_SIZE,
							THREAD_SIZE, 0);
D
David S. Miller 已提交
2031 2032
	}

2033 2034
	kernel_physical_mapping_init();

L
Linus Torvalds 已提交
2035
	{
D
David S. Miller 已提交
2036
		unsigned long max_zone_pfns[MAX_NR_ZONES];
L
Linus Torvalds 已提交
2037

D
David S. Miller 已提交
2038
		memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
L
Linus Torvalds 已提交
2039

D
David S. Miller 已提交
2040
		max_zone_pfns[ZONE_NORMAL] = end_pfn;
L
Linus Torvalds 已提交
2041

D
David S. Miller 已提交
2042
		free_area_init_nodes(max_zone_pfns);
L
Linus Torvalds 已提交
2043 2044
	}

2045
	printk("Booting Linux...\n");
L
Linus Torvalds 已提交
2046 2047
}

2048
int page_in_phys_avail(unsigned long paddr)
D
David S. Miller 已提交
2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082
{
	int i;

	paddr &= PAGE_MASK;

	for (i = 0; i < pavail_ents; i++) {
		unsigned long start, end;

		start = pavail[i].phys_addr;
		end = start + pavail[i].reg_size;

		if (paddr >= start && paddr < end)
			return 1;
	}
	if (paddr >= kern_base && paddr < (kern_base + kern_size))
		return 1;
#ifdef CONFIG_BLK_DEV_INITRD
	if (paddr >= __pa(initrd_start) &&
	    paddr < __pa(PAGE_ALIGN(initrd_end)))
		return 1;
#endif

	return 0;
}

static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
static int pavail_rescan_ents __initdata;

/* Certain OBP calls, such as fetching "available" properties, can
 * claim physical memory.  So, along with initializing the valid
 * address bitmap, what we do here is refetch the physical available
 * memory list again, and make sure it provides at least as much
 * memory as 'pavail' does.
 */
2083
static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
L
Linus Torvalds 已提交
2084 2085 2086
{
	int i;

2087
	read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
L
Linus Torvalds 已提交
2088

2089
	for (i = 0; i < pavail_ents; i++) {
L
Linus Torvalds 已提交
2090 2091
		unsigned long old_start, old_end;

2092
		old_start = pavail[i].phys_addr;
D
David S. Miller 已提交
2093
		old_end = old_start + pavail[i].reg_size;
L
Linus Torvalds 已提交
2094 2095 2096
		while (old_start < old_end) {
			int n;

2097
			for (n = 0; n < pavail_rescan_ents; n++) {
L
Linus Torvalds 已提交
2098 2099
				unsigned long new_start, new_end;

2100 2101 2102
				new_start = pavail_rescan[n].phys_addr;
				new_end = new_start +
					pavail_rescan[n].reg_size;
L
Linus Torvalds 已提交
2103 2104 2105

				if (new_start <= old_start &&
				    new_end >= (old_start + PAGE_SIZE)) {
2106
					set_bit(old_start >> ILOG2_4MB, bitmap);
L
Linus Torvalds 已提交
2107 2108 2109
					goto do_next_page;
				}
			}
D
David S. Miller 已提交
2110 2111 2112 2113 2114 2115 2116 2117 2118 2119

			prom_printf("mem_init: Lost memory in pavail\n");
			prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
				    pavail[i].phys_addr,
				    pavail[i].reg_size);
			prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
				    pavail_rescan[i].phys_addr,
				    pavail_rescan[i].reg_size);
			prom_printf("mem_init: Cannot continue, aborting.\n");
			prom_halt();
L
Linus Torvalds 已提交
2120 2121 2122 2123 2124 2125 2126

		do_next_page:
			old_start += PAGE_SIZE;
		}
	}
}

2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137
static void __init patch_tlb_miss_handler_bitmap(void)
{
	extern unsigned int valid_addr_bitmap_insn[];
	extern unsigned int valid_addr_bitmap_patch[];

	valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
	mb();
	valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
	flushi(&valid_addr_bitmap_insn[0]);
}

2138 2139 2140 2141 2142 2143 2144 2145 2146 2147
static void __init register_page_bootmem_info(void)
{
#ifdef CONFIG_NEED_MULTIPLE_NODES
	int i;

	for_each_online_node(i)
		if (NODE_DATA(i)->node_spanned_pages)
			register_page_bootmem_info_node(NODE_DATA(i));
#endif
}
L
Linus Torvalds 已提交
2148 2149 2150 2151 2152 2153 2154
void __init mem_init(void)
{
	unsigned long addr, last;

	addr = PAGE_OFFSET + kern_base;
	last = PAGE_ALIGN(kern_size) + addr;
	while (addr < last) {
2155
		set_bit(__pa(addr) >> ILOG2_4MB, sparc64_valid_addr_bitmap);
L
Linus Torvalds 已提交
2156 2157 2158
		addr += PAGE_SIZE;
	}

2159 2160
	setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
	patch_tlb_miss_handler_bitmap();
L
Linus Torvalds 已提交
2161 2162 2163

	high_memory = __va(last_valid_pfn << PAGE_SHIFT);

2164
	register_page_bootmem_info();
2165
	free_all_bootmem();
D
David S. Miller 已提交
2166

L
Linus Torvalds 已提交
2167 2168 2169 2170 2171 2172 2173 2174 2175
	/*
	 * Set up the zero page, mark it reserved, so that page count
	 * is not manipulated when freeing the page from user ptes.
	 */
	mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
	if (mem_map_zero == NULL) {
		prom_printf("paging_init: Cannot alloc zero page.\n");
		prom_halt();
	}
2176
	mark_page_reserved(mem_map_zero);
L
Linus Torvalds 已提交
2177

2178
	mem_init_print_info(NULL);
L
Linus Torvalds 已提交
2179 2180 2181 2182 2183

	if (tlb_type == cheetah || tlb_type == cheetah_plus)
		cheetah_ecache_flush_init();
}

2184
void free_initmem(void)
L
Linus Torvalds 已提交
2185 2186
{
	unsigned long addr, initend;
2187 2188 2189 2190 2191 2192 2193 2194 2195
	int do_free = 1;

	/* If the physical memory maps were trimmed by kernel command
	 * line options, don't even try freeing this initmem stuff up.
	 * The kernel image could have been in the trimmed out region
	 * and if so the freeing below will free invalid page structs.
	 */
	if (cmdline_memory_size)
		do_free = 0;
L
Linus Torvalds 已提交
2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207

	/*
	 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
	 */
	addr = PAGE_ALIGN((unsigned long)(__init_begin));
	initend = (unsigned long)(__init_end) & PAGE_MASK;
	for (; addr < initend; addr += PAGE_SIZE) {
		unsigned long page;

		page = (addr +
			((unsigned long) __va(kern_base)) -
			((unsigned long) KERNBASE));
2208
		memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
L
Linus Torvalds 已提交
2209

2210 2211
		if (do_free)
			free_reserved_page(virt_to_page(page));
L
Linus Torvalds 已提交
2212 2213 2214 2215 2216 2217
	}
}

#ifdef CONFIG_BLK_DEV_INITRD
void free_initrd_mem(unsigned long start, unsigned long end)
{
2218 2219
	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
			   "initrd");
L
Linus Torvalds 已提交
2220 2221
}
#endif
2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234

#define _PAGE_CACHE_4U	(_PAGE_CP_4U | _PAGE_CV_4U)
#define _PAGE_CACHE_4V	(_PAGE_CP_4V | _PAGE_CV_4V)
#define __DIRTY_BITS_4U	 (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
#define __DIRTY_BITS_4V	 (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)

pgprot_t PAGE_KERNEL __read_mostly;
EXPORT_SYMBOL(PAGE_KERNEL);

pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
pgprot_t PAGE_COPY __read_mostly;
2235 2236 2237 2238

pgprot_t PAGE_SHARED __read_mostly;
EXPORT_SYMBOL(PAGE_SHARED);

2239 2240 2241
unsigned long pg_iobits __read_mostly;

unsigned long _PAGE_IE __read_mostly;
2242
EXPORT_SYMBOL(_PAGE_IE);
2243

2244
unsigned long _PAGE_E __read_mostly;
2245 2246
EXPORT_SYMBOL(_PAGE_E);

2247
unsigned long _PAGE_CACHE __read_mostly;
2248
EXPORT_SYMBOL(_PAGE_CACHE);
2249

D
David Miller 已提交
2250 2251 2252
#ifdef CONFIG_SPARSEMEM_VMEMMAP
unsigned long vmemmap_table[VMEMMAP_SIZE];

2253 2254 2255
static long __meminitdata addr_start, addr_end;
static int __meminitdata node_start;

2256 2257
int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
			       int node)
D
David Miller 已提交
2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278
{
	unsigned long phys_start = (vstart - VMEMMAP_BASE);
	unsigned long phys_end = (vend - VMEMMAP_BASE);
	unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
	unsigned long end = VMEMMAP_ALIGN(phys_end);
	unsigned long pte_base;

	pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
		    _PAGE_CP_4U | _PAGE_CV_4U |
		    _PAGE_P_4U | _PAGE_W_4U);
	if (tlb_type == hypervisor)
		pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
			    _PAGE_CP_4V | _PAGE_CV_4V |
			    _PAGE_P_4V | _PAGE_W_4V);

	for (; addr < end; addr += VMEMMAP_CHUNK) {
		unsigned long *vmem_pp =
			vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
		void *block;

		if (!(*vmem_pp & _PAGE_VALID)) {
2279
			block = vmemmap_alloc_block(1UL << ILOG2_4MB, node);
D
David Miller 已提交
2280 2281 2282 2283 2284
			if (!block)
				return -ENOMEM;

			*vmem_pp = pte_base | __pa(block);

2285 2286 2287 2288 2289 2290 2291 2292 2293
			/* check to see if we have contiguous blocks */
			if (addr_end != addr || node_start != node) {
				if (addr_start)
					printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
					       addr_start, addr_end-1, node_start);
				addr_start = addr;
				node_start = node;
			}
			addr_end = addr + VMEMMAP_CHUNK;
D
David Miller 已提交
2294 2295 2296 2297
		}
	}
	return 0;
}
2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308

void __meminit vmemmap_populate_print_last(void)
{
	if (addr_start) {
		printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
		       addr_start, addr_end-1, node_start);
		addr_start = 0;
		addr_end = 0;
		node_start = 0;
	}
}
2309

2310
void vmemmap_free(unsigned long start, unsigned long end)
2311 2312 2313
{
}

D
David Miller 已提交
2314 2315
#endif /* CONFIG_SPARSEMEM_VMEMMAP */

2316 2317 2318 2319 2320 2321 2322
static void prot_init_common(unsigned long page_none,
			     unsigned long page_shared,
			     unsigned long page_copy,
			     unsigned long page_readonly,
			     unsigned long page_exec_bit)
{
	PAGE_COPY = __pgprot(page_copy);
2323
	PAGE_SHARED = __pgprot(page_shared);
2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346

	protection_map[0x0] = __pgprot(page_none);
	protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
	protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
	protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
	protection_map[0x4] = __pgprot(page_readonly);
	protection_map[0x5] = __pgprot(page_readonly);
	protection_map[0x6] = __pgprot(page_copy);
	protection_map[0x7] = __pgprot(page_copy);
	protection_map[0x8] = __pgprot(page_none);
	protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
	protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
	protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
	protection_map[0xc] = __pgprot(page_readonly);
	protection_map[0xd] = __pgprot(page_readonly);
	protection_map[0xe] = __pgprot(page_shared);
	protection_map[0xf] = __pgprot(page_shared);
}

static void __init sun4u_pgprot_init(void)
{
	unsigned long page_none, page_shared, page_copy, page_readonly;
	unsigned long page_exec_bit;
2347
	int i;
2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364

	PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
				_PAGE_CACHE_4U | _PAGE_P_4U |
				__ACCESS_BITS_4U | __DIRTY_BITS_4U |
				_PAGE_EXEC_4U);
	PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
				       _PAGE_CACHE_4U | _PAGE_P_4U |
				       __ACCESS_BITS_4U | __DIRTY_BITS_4U |
				       _PAGE_EXEC_4U | _PAGE_L_4U);

	_PAGE_IE = _PAGE_IE_4U;
	_PAGE_E = _PAGE_E_4U;
	_PAGE_CACHE = _PAGE_CACHE_4U;

	pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
		     __ACCESS_BITS_4U | _PAGE_E_4U);

2365
#ifdef CONFIG_DEBUG_PAGEALLOC
2366
	kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2367
#else
2368
	kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2369
		PAGE_OFFSET;
2370
#endif
2371 2372 2373
	kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
				   _PAGE_P_4U | _PAGE_W_4U);

2374 2375
	for (i = 1; i < 4; i++)
		kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399

	_PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
			      _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
			      _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);


	page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
	page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
		       __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
	page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
		       __ACCESS_BITS_4U | _PAGE_EXEC_4U);
	page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
			   __ACCESS_BITS_4U | _PAGE_EXEC_4U);

	page_exec_bit = _PAGE_EXEC_4U;

	prot_init_common(page_none, page_shared, page_copy, page_readonly,
			 page_exec_bit);
}

static void __init sun4v_pgprot_init(void)
{
	unsigned long page_none, page_shared, page_copy, page_readonly;
	unsigned long page_exec_bit;
2400
	int i;
2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411

	PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
				_PAGE_CACHE_4V | _PAGE_P_4V |
				__ACCESS_BITS_4V | __DIRTY_BITS_4V |
				_PAGE_EXEC_4V);
	PAGE_KERNEL_LOCKED = PAGE_KERNEL;

	_PAGE_IE = _PAGE_IE_4V;
	_PAGE_E = _PAGE_E_4V;
	_PAGE_CACHE = _PAGE_CACHE_4V;

2412
#ifdef CONFIG_DEBUG_PAGEALLOC
2413
	kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2414
#else
2415
	kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2416
		PAGE_OFFSET;
2417
#endif
2418 2419 2420
	kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
				   _PAGE_P_4V | _PAGE_W_4V);

2421 2422
	for (i = 1; i < 4; i++)
		kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2423

2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458
	pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
		     __ACCESS_BITS_4V | _PAGE_E_4V);

	_PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
			     _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
			     _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
			     _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);

	page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
	page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
		       __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
	page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
		       __ACCESS_BITS_4V | _PAGE_EXEC_4V);
	page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
			 __ACCESS_BITS_4V | _PAGE_EXEC_4V);

	page_exec_bit = _PAGE_EXEC_4V;

	prot_init_common(page_none, page_shared, page_copy, page_readonly,
			 page_exec_bit);
}

unsigned long pte_sz_bits(unsigned long sz)
{
	if (tlb_type == hypervisor) {
		switch (sz) {
		case 8 * 1024:
		default:
			return _PAGE_SZ8K_4V;
		case 64 * 1024:
			return _PAGE_SZ64K_4V;
		case 512 * 1024:
			return _PAGE_SZ512K_4V;
		case 4 * 1024 * 1024:
			return _PAGE_SZ4MB_4V;
2459
		}
2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470
	} else {
		switch (sz) {
		case 8 * 1024:
		default:
			return _PAGE_SZ8K_4U;
		case 64 * 1024:
			return _PAGE_SZ64K_4U;
		case 512 * 1024:
			return _PAGE_SZ512K_4U;
		case 4 * 1024 * 1024:
			return _PAGE_SZ4MB_4U;
2471
		}
2472 2473 2474 2475 2476 2477
	}
}

pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
{
	pte_t pte;
2478 2479

	pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2480 2481 2482
	pte_val(pte) |= (((unsigned long)space) << 32);
	pte_val(pte) |= pte_sz_bits(page_size);

2483
	return pte;
2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511
}

static unsigned long kern_large_tte(unsigned long paddr)
{
	unsigned long val;

	val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
	       _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
	       _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
	if (tlb_type == hypervisor)
		val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
		       _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
		       _PAGE_EXEC_4V | _PAGE_W_4V);

	return val | paddr;
}

/* If not locked, zap it. */
void __flush_tlb_all(void)
{
	unsigned long pstate;
	int i;

	__asm__ __volatile__("flushw\n\t"
			     "rdpr	%%pstate, %0\n\t"
			     "wrpr	%0, %1, %%pstate"
			     : "=r" (pstate)
			     : "i" (PSTATE_IE));
2512 2513 2514
	if (tlb_type == hypervisor) {
		sun4v_mmu_demap_all();
	} else if (tlb_type == spitfire) {
2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558
		for (i = 0; i < 64; i++) {
			/* Spitfire Errata #32 workaround */
			/* NOTE: Always runs on spitfire, so no
			 *       cheetah+ page size encodings.
			 */
			__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
					     "flush	%%g6"
					     : /* No outputs */
					     : "r" (0),
					     "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));

			if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
				__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
						     "membar #Sync"
						     : /* no outputs */
						     : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
				spitfire_put_dtlb_data(i, 0x0UL);
			}

			/* Spitfire Errata #32 workaround */
			/* NOTE: Always runs on spitfire, so no
			 *       cheetah+ page size encodings.
			 */
			__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
					     "flush	%%g6"
					     : /* No outputs */
					     : "r" (0),
					     "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));

			if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
				__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
						     "membar #Sync"
						     : /* no outputs */
						     : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
				spitfire_put_itlb_data(i, 0x0UL);
			}
		}
	} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
		cheetah_flush_dtlb_all();
		cheetah_flush_itlb_all();
	}
	__asm__ __volatile__("wrpr	%0, 0, %%pstate"
			     : : "r" (pstate));
}
2559 2560 2561 2562

pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
			    unsigned long address)
{
2563 2564 2565
	struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
				       __GFP_REPEAT | __GFP_ZERO);
	pte_t *pte = NULL;
2566 2567 2568 2569 2570 2571 2572 2573 2574 2575

	if (page)
		pte = (pte_t *) page_address(page);

	return pte;
}

pgtable_t pte_alloc_one(struct mm_struct *mm,
			unsigned long address)
{
2576 2577
	struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
				       __GFP_REPEAT | __GFP_ZERO);
2578 2579 2580 2581 2582
	if (!page)
		return NULL;
	if (!pgtable_page_ctor(page)) {
		free_hot_cold_page(page, 0);
		return NULL;
2583
	}
2584
	return (pte_t *) page_address(page);
2585 2586 2587 2588
}

void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
{
2589
	free_page((unsigned long)pte);
2590 2591 2592 2593 2594
}

static void __pte_free(pgtable_t pte)
{
	struct page *page = virt_to_page(pte);
2595 2596 2597

	pgtable_page_dtor(page);
	__free_page(page);
2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611
}

void pte_free(struct mm_struct *mm, pgtable_t pte)
{
	__pte_free(pte);
}

void pgtable_free(void *table, bool is_page)
{
	if (is_page)
		__pte_free(table);
	else
		kmem_cache_free(pgtable_cache, table);
}
2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623

#ifdef CONFIG_TRANSPARENT_HUGEPAGE
void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
			  pmd_t *pmd)
{
	unsigned long pte, flags;
	struct mm_struct *mm;
	pmd_t entry = *pmd;

	if (!pmd_large(entry) || !pmd_young(entry))
		return;

2624
	pte = pmd_val(entry);
2625

2626 2627 2628 2629
	/* Don't insert a non-valid PMD into the TSB, we'll deadlock.  */
	if (!(pte & _PAGE_VALID))
		return;

2630 2631
	/* We are fabricating 8MB pages using 4MB real hw pages.  */
	pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2632 2633 2634 2635 2636 2637

	mm = vma->vm_mm;

	spin_lock_irqsave(&mm->context.lock, flags);

	if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2638
		__update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653
					addr, pte);

	spin_unlock_irqrestore(&mm->context.lock, flags);
}
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */

#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
static void context_reload(void *__data)
{
	struct mm_struct *mm = __data;

	if (mm == current->mm)
		load_secondary_context(mm);
}

2654
void hugetlb_setup(struct pt_regs *regs)
2655
{
2656 2657
	struct mm_struct *mm = current->mm;
	struct tsb_config *tp;
2658

2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674
	if (in_atomic() || !mm) {
		const struct exception_table_entry *entry;

		entry = search_exception_tables(regs->tpc);
		if (entry) {
			regs->tpc = entry->fixup;
			regs->tnpc = regs->tpc + 4;
			return;
		}
		pr_alert("Unexpected HugeTLB setup in atomic context.\n");
		die_if_kernel("HugeTSB in atomic", regs);
	}

	tp = &mm->context.tsb_block[MM_TSB_HUGE];
	if (likely(tp->tsb == NULL))
		tsb_grow(mm, MM_TSB_HUGE, 0);
2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709

	tsb_context_switch(mm);
	smp_tsb_sync(mm);

	/* On UltraSPARC-III+ and later, configure the second half of
	 * the Data-TLB for huge pages.
	 */
	if (tlb_type == cheetah_plus) {
		unsigned long ctx;

		spin_lock(&ctx_alloc_lock);
		ctx = mm->context.sparc64_ctx_val;
		ctx &= ~CTX_PGSZ_MASK;
		ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
		ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;

		if (ctx != mm->context.sparc64_ctx_val) {
			/* When changing the page size fields, we
			 * must perform a context flush so that no
			 * stale entries match.  This flush must
			 * occur with the original context register
			 * settings.
			 */
			do_flush_tlb_mm(mm);

			/* Reload the context register of all processors
			 * also executing in this address space.
			 */
			mm->context.sparc64_ctx_val = ctx;
			on_each_cpu(context_reload, mm, 0);
		}
		spin_unlock(&ctx_alloc_lock);
	}
}
#endif