rt2800lib.c 176.4 KB
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/*
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	Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
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	Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
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	Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
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	Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
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	Based on the original rt2800pci.c and rt2800usb.c.
	  Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
	  Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
	  Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
	  Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
	  Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
	  Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
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	  <http://rt2x00.serialmonkey.com>

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the
	Free Software Foundation, Inc.,
	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/*
	Module: rt2800lib
	Abstract: rt2800 generic device routines.
 */

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#include <linux/crc-ccitt.h>
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#include <linux/kernel.h>
#include <linux/module.h>
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#include <linux/slab.h>
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#include "rt2x00.h"
#include "rt2800lib.h"
#include "rt2800.h"

/*
 * Register access.
 * All access to the CSR registers will go through the methods
 * rt2800_register_read and rt2800_register_write.
 * BBP and RF register require indirect register access,
 * and use the CSR registers BBPCSR and RFCSR to achieve this.
 * These indirect registers work with busy bits,
 * and we will try maximal REGISTER_BUSY_COUNT times to access
 * the register while taking a REGISTER_BUSY_DELAY us delay
 * between each attampt. When the busy bit is still set at that time,
 * the access attempt is considered to have failed,
 * and we will print an error.
 * The _lock versions must be used if you already hold the csr_mutex
 */
#define WAIT_FOR_BBP(__dev, __reg) \
	rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
#define WAIT_FOR_RFCSR(__dev, __reg) \
	rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
#define WAIT_FOR_RF(__dev, __reg) \
	rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
#define WAIT_FOR_MCU(__dev, __reg) \
	rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
			    H2M_MAILBOX_CSR_OWNER, (__reg))

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static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
{
	/* check for rt2872 on SoC */
	if (!rt2x00_is_soc(rt2x00dev) ||
	    !rt2x00_rt(rt2x00dev, RT2872))
		return false;

	/* we know for sure that these rf chipsets are used on rt305x boards */
	if (rt2x00_rf(rt2x00dev, RF3020) ||
	    rt2x00_rf(rt2x00dev, RF3021) ||
	    rt2x00_rf(rt2x00dev, RF3022))
		return true;

	NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
	return false;
}

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static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
			     const unsigned int word, const u8 value)
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{
	u32 reg;

	mutex_lock(&rt2x00dev->csr_mutex);

	/*
	 * Wait until the BBP becomes available, afterwards we
	 * can safely write the new data into the register.
	 */
	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
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		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
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		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
	}

	mutex_unlock(&rt2x00dev->csr_mutex);
}

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static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
			    const unsigned int word, u8 *value)
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{
	u32 reg;

	mutex_lock(&rt2x00dev->csr_mutex);

	/*
	 * Wait until the BBP becomes available, afterwards we
	 * can safely write the read request into the register.
	 * After the data has been written, we wait until hardware
	 * returns the correct value, if at any time the register
	 * doesn't become available in time, reg will be 0xffffffff
	 * which means we return 0xff to the caller.
	 */
	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
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		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
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		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);

		WAIT_FOR_BBP(rt2x00dev, &reg);
	}

	*value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);

	mutex_unlock(&rt2x00dev->csr_mutex);
}

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static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
			       const unsigned int word, const u8 value)
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{
	u32 reg;

	mutex_lock(&rt2x00dev->csr_mutex);

	/*
	 * Wait until the RFCSR becomes available, afterwards we
	 * can safely write the new data into the register.
	 */
	if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
		rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
		rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
		rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);

		rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
	}

	mutex_unlock(&rt2x00dev->csr_mutex);
}

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static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
			      const unsigned int word, u8 *value)
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{
	u32 reg;

	mutex_lock(&rt2x00dev->csr_mutex);

	/*
	 * Wait until the RFCSR becomes available, afterwards we
	 * can safely write the read request into the register.
	 * After the data has been written, we wait until hardware
	 * returns the correct value, if at any time the register
	 * doesn't become available in time, reg will be 0xffffffff
	 * which means we return 0xff to the caller.
	 */
	if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
		rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
		rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);

		rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);

		WAIT_FOR_RFCSR(rt2x00dev, &reg);
	}

	*value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);

	mutex_unlock(&rt2x00dev->csr_mutex);
}

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static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
			    const unsigned int word, const u32 value)
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{
	u32 reg;

	mutex_lock(&rt2x00dev->csr_mutex);

	/*
	 * Wait until the RF becomes available, afterwards we
	 * can safely write the new data into the register.
	 */
	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
		rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
		rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
		rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);

		rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
		rt2x00_rf_write(rt2x00dev, word, value);
	}

	mutex_unlock(&rt2x00dev->csr_mutex);
}

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static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;
	int i, count;

	rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
	if (rt2x00_get_field32(reg, WLAN_EN))
		return 0;

	rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
	rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
	rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
	rt2x00_set_field32(&reg, WLAN_EN, 1);
	rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);

	udelay(REGISTER_BUSY_DELAY);

	count = 0;
	do {
		/*
		 * Check PLL_LD & XTAL_RDY.
		 */
		for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
			rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
			if (rt2x00_get_field32(reg, PLL_LD) &&
			    rt2x00_get_field32(reg, XTAL_RDY))
				break;
			udelay(REGISTER_BUSY_DELAY);
		}

		if (i >= REGISTER_BUSY_COUNT) {

			if (count >= 10)
				return -EIO;

			rt2800_register_write(rt2x00dev, 0x58, 0x018);
			udelay(REGISTER_BUSY_DELAY);
			rt2800_register_write(rt2x00dev, 0x58, 0x418);
			udelay(REGISTER_BUSY_DELAY);
			rt2800_register_write(rt2x00dev, 0x58, 0x618);
			udelay(REGISTER_BUSY_DELAY);
			count++;
		} else {
			count = 0;
		}

		rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
		rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
		rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
		rt2x00_set_field32(&reg, WLAN_RESET, 1);
		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
		udelay(10);
		rt2x00_set_field32(&reg, WLAN_RESET, 0);
		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
		udelay(10);
		rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
	} while (count != 0);

	return 0;
}

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void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
			const u8 command, const u8 token,
			const u8 arg0, const u8 arg1)
{
	u32 reg;

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	/*
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	 * SOC devices don't support MCU requests.
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	 */
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	if (rt2x00_is_soc(rt2x00dev))
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		return;
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	mutex_lock(&rt2x00dev->csr_mutex);

	/*
	 * Wait until the MCU becomes available, afterwards we
	 * can safely write the new data into the register.
	 */
	if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
		rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);

		reg = 0;
		rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
		rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
	}

	mutex_unlock(&rt2x00dev->csr_mutex);
}
EXPORT_SYMBOL_GPL(rt2800_mcu_request);
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int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
{
	unsigned int i = 0;
	u32 reg;

	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
		rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
		if (reg && reg != ~0)
			return 0;
		msleep(1);
	}

	ERROR(rt2x00dev, "Unstable hardware.\n");
	return -EBUSY;
}
EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);

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int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
{
	unsigned int i;
	u32 reg;

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	/*
	 * Some devices are really slow to respond here. Wait a whole second
	 * before timing out.
	 */
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	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
		rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
		if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
		    !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
			return 0;

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		msleep(10);
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	}

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	ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
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	return -EACCES;
}
EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);

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void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;

	rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
}
EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);

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static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
{
	u16 fw_crc;
	u16 crc;

	/*
	 * The last 2 bytes in the firmware array are the crc checksum itself,
	 * this means that we should never pass those 2 bytes to the crc
	 * algorithm.
	 */
	fw_crc = (data[len - 2] << 8 | data[len - 1]);

	/*
	 * Use the crc ccitt algorithm.
	 * This will return the same value as the legacy driver which
	 * used bit ordering reversion on the both the firmware bytes
	 * before input input as well as on the final output.
	 * Obviously using crc ccitt directly is much more efficient.
	 */
	crc = crc_ccitt(~0, data, len - 2);

	/*
	 * There is a small difference between the crc-itu-t + bitrev and
	 * the crc-ccitt crc calculation. In the latter method the 2 bytes
	 * will be swapped, use swab16 to convert the crc to the correct
	 * value.
	 */
	crc = swab16(crc);

	return fw_crc == crc;
}

int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
			  const u8 *data, const size_t len)
{
	size_t offset = 0;
	size_t fw_len;
	bool multiple;

	/*
	 * PCI(e) & SOC devices require firmware with a length
	 * of 8kb. USB devices require firmware files with a length
	 * of 4kb. Certain USB chipsets however require different firmware,
	 * which Ralink only provides attached to the original firmware
	 * file. Thus for USB devices, firmware files have a length
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	 * which is a multiple of 4kb. The firmware for rt3290 chip also
	 * have a length which is a multiple of 4kb.
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	 */
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	if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
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		fw_len = 4096;
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	else
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		fw_len = 8192;

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	multiple = true;
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	/*
	 * Validate the firmware length
	 */
	if (len != fw_len && (!multiple || (len % fw_len) != 0))
		return FW_BAD_LENGTH;

	/*
	 * Check if the chipset requires one of the upper parts
	 * of the firmware.
	 */
	if (rt2x00_is_usb(rt2x00dev) &&
	    !rt2x00_rt(rt2x00dev, RT2860) &&
	    !rt2x00_rt(rt2x00dev, RT2872) &&
	    !rt2x00_rt(rt2x00dev, RT3070) &&
	    ((len / fw_len) == 1))
		return FW_BAD_VERSION;

	/*
	 * 8kb firmware files must be checked as if it were
	 * 2 separate firmware files.
	 */
	while (offset < len) {
		if (!rt2800_check_firmware_crc(data + offset, fw_len))
			return FW_BAD_CRC;

		offset += fw_len;
	}

	return FW_OK;
}
EXPORT_SYMBOL_GPL(rt2800_check_firmware);

int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
			 const u8 *data, const size_t len)
{
	unsigned int i;
	u32 reg;
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	int retval;

	if (rt2x00_rt(rt2x00dev, RT3290)) {
		retval = rt2800_enable_wlan_rt3290(rt2x00dev);
		if (retval)
			return -EBUSY;
	}
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	/*
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	 * If driver doesn't wake up firmware here,
	 * rt2800_load_firmware will hang forever when interface is up again.
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	 */
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	rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
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	/*
	 * Wait for stable hardware.
	 */
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	if (rt2800_wait_csr_ready(rt2x00dev))
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		return -EBUSY;

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	if (rt2x00_is_pci(rt2x00dev)) {
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		if (rt2x00_rt(rt2x00dev, RT3290) ||
		    rt2x00_rt(rt2x00dev, RT3572) ||
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		    rt2x00_rt(rt2x00dev, RT5390) ||
		    rt2x00_rt(rt2x00dev, RT5392)) {
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			rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
			rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
			rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
			rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
		}
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		rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
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	}
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	rt2800_disable_wpdma(rt2x00dev);

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	/*
	 * Write firmware to the device.
	 */
	rt2800_drv_write_firmware(rt2x00dev, data, len);

	/*
	 * Wait for device to stabilize.
	 */
	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
		rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
		if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
			break;
		msleep(1);
	}

	if (i == REGISTER_BUSY_COUNT) {
		ERROR(rt2x00dev, "PBF system register not ready.\n");
		return -EBUSY;
	}

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	/*
	 * Disable DMA, will be reenabled later when enabling
	 * the radio.
	 */
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	rt2800_disable_wpdma(rt2x00dev);
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	/*
	 * Initialize firmware.
	 */
	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
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	if (rt2x00_is_usb(rt2x00dev))
		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
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	msleep(1);

	return 0;
}
EXPORT_SYMBOL_GPL(rt2800_load_firmware);

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void rt2800_write_tx_data(struct queue_entry *entry,
			  struct txentry_desc *txdesc)
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{
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	__le32 *txwi = rt2800_drv_get_txwi(entry);
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	u32 word;

	/*
	 * Initialize TX Info descriptor
	 */
	rt2x00_desc_read(txwi, 0, &word);
	rt2x00_set_field32(&word, TXWI_W0_FRAG,
			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
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	rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
			   test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
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	rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
	rt2x00_set_field32(&word, TXWI_W0_TS,
			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
	rt2x00_set_field32(&word, TXWI_W0_AMPDU,
			   test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
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	rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
			   txdesc->u.ht.mpdu_density);
	rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
	rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
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	rt2x00_set_field32(&word, TXWI_W0_BW,
			   test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
	rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
			   test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
565
	rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
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	rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
	rt2x00_desc_write(txwi, 0, word);

	rt2x00_desc_read(txwi, 1, &word);
	rt2x00_set_field32(&word, TXWI_W1_ACK,
			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
	rt2x00_set_field32(&word, TXWI_W1_NSEQ,
			   test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
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	rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
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	rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
			   test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
577
			   txdesc->key_idx : txdesc->u.ht.wcid);
578 579
	rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
			   txdesc->length);
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	rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
581
	rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
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	rt2x00_desc_write(txwi, 1, word);

	/*
	 * Always write 0 to IV/EIV fields, hardware will insert the IV
	 * from the IVEIV register when TXD_W3_WIV is set to 0.
	 * When TXD_W3_WIV is set to 1 it will use the IV data
	 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
	 * crypto entry in the registers should be used to encrypt the frame.
	 */
	_rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
	_rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
}
594
EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
595

596
static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
597
{
598 599 600
	s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
	s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
	s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
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	u16 eeprom;
	u8 offset0;
	u8 offset1;
	u8 offset2;

606
	if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
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		rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
		rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
	} else {
		rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
		rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
	}

	/*
	 * Convert the value from the descriptor into the RSSI value
	 * If the value in the descriptor is 0, it is considered invalid
	 * and the default (extremely low) rssi value is assumed
	 */
	rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
	rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
	rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;

	/*
	 * mac80211 only accepts a single RSSI value. Calculating the
	 * average doesn't deliver a fair answer either since -60:-60 would
	 * be considered equally good as -50:-70 while the second is the one
	 * which gives less energy...
	 */
	rssi0 = max(rssi0, rssi1);
636
	return (int)max(rssi0, rssi2);
637 638 639 640 641 642
}

void rt2800_process_rxwi(struct queue_entry *entry,
			 struct rxdone_entry_desc *rxdesc)
{
	__le32 *rxwi = (__le32 *) entry->skb->data;
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	u32 word;

	rt2x00_desc_read(rxwi, 0, &word);

	rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
	rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);

	rt2x00_desc_read(rxwi, 1, &word);

	if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
		rxdesc->flags |= RX_FLAG_SHORT_GI;

	if (rt2x00_get_field32(word, RXWI_W1_BW))
		rxdesc->flags |= RX_FLAG_40MHZ;

	/*
	 * Detect RX rate, always use MCS as signal type.
	 */
	rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
	rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
	rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);

	/*
	 * Mask of 0x8 bit to remove the short preamble flag.
	 */
	if (rxdesc->rate_mode == RATE_MODE_CCK)
		rxdesc->signal &= ~0x8;

	rt2x00_desc_read(rxwi, 2, &word);

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	/*
	 * Convert descriptor AGC value to RSSI value.
	 */
	rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
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	/*
	 * Remove RXWI descriptor from start of buffer.
	 */
681
	skb_pull(entry->skb, RXWI_DESC_SIZE);
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}
EXPORT_SYMBOL_GPL(rt2800_process_rxwi);

685
void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
686 687
{
	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
688
	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
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	struct txdone_entry_desc txdesc;
	u32 word;
	u16 mcs, real_mcs;
692
	int aggr, ampdu;
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	/*
	 * Obtain the status about this packet.
	 */
	txdesc.flags = 0;
	rt2x00_desc_read(txwi, 0, &word);
699

700
	mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
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	ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);

703
	real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
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	aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);

	/*
	 * If a frame was meant to be sent as a single non-aggregated MPDU
	 * but ended up in an aggregate the used tx rate doesn't correlate
	 * with the one specified in the TXWI as the whole aggregate is sent
	 * with the same rate.
	 *
	 * For example: two frames are sent to rt2x00, the first one sets
	 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
	 * and requests MCS15. If the hw aggregates both frames into one
	 * AMDPU the tx status for both frames will contain MCS7 although
	 * the frame was sent successfully.
	 *
	 * Hence, replace the requested rate with the real tx rate to not
	 * confuse the rate control algortihm by providing clearly wrong
	 * data.
	 */
722
	if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
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		skbdesc->tx_rate_idx = real_mcs;
		mcs = real_mcs;
	}
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727 728 729
	if (aggr == 1 || ampdu == 1)
		__set_bit(TXDONE_AMPDU, &txdesc.flags);

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	/*
	 * Ralink has a retry mechanism using a global fallback
	 * table. We setup this fallback table to try the immediate
	 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
	 * always contains the MCS used for the last transmission, be
	 * it successful or not.
	 */
	if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
		/*
		 * Transmission succeeded. The number of retries is
		 * mcs - real_mcs
		 */
		__set_bit(TXDONE_SUCCESS, &txdesc.flags);
		txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
	} else {
		/*
		 * Transmission failed. The number of retries is
		 * always 7 in this case (for a total number of 8
		 * frames sent).
		 */
		__set_bit(TXDONE_FAILURE, &txdesc.flags);
		txdesc.retry = rt2x00dev->long_retry;
	}

	/*
	 * the frame was retried at least once
	 * -> hw used fallback rates
	 */
	if (txdesc.retry)
		__set_bit(TXDONE_FALLBACK, &txdesc.flags);

	rt2x00lib_txdone(entry, &txdesc);
}
EXPORT_SYMBOL_GPL(rt2800_txdone_entry);

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void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
{
	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
	unsigned int beacon_base;
770
	unsigned int padding_len;
771
	u32 orig_reg, reg;
772 773 774 775 776 777

	/*
	 * Disable beaconing while we are reloading the beacon data,
	 * otherwise we might be sending out invalid data.
	 */
	rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
778
	orig_reg = reg;
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	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);

	/*
	 * Add space for the TXWI in front of the skb.
	 */
785
	memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
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	/*
	 * Register descriptor details in skb frame descriptor.
	 */
	skbdesc->flags |= SKBDESC_DESC_IN_SKB;
	skbdesc->desc = entry->skb->data;
	skbdesc->desc_len = TXWI_DESC_SIZE;

	/*
	 * Add the TXWI for the beacon to the skb.
	 */
797
	rt2800_write_tx_data(entry, txdesc);
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	/*
	 * Dump beacon to userspace through debugfs.
	 */
	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);

	/*
805
	 * Write entire beacon with TXWI and padding to register.
806
	 */
807
	padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
808 809 810 811 812 813 814 815
	if (padding_len && skb_pad(entry->skb, padding_len)) {
		ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
		/* skb freed by skb_pad() on failure */
		entry->skb = NULL;
		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
		return;
	}

816
	beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
817 818
	rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
				   entry->skb->len + padding_len);
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	/*
	 * Enable beaconing again.
	 */
	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);

	/*
	 * Clean up beacon skb.
	 */
	dev_kfree_skb_any(entry->skb);
	entry->skb = NULL;
}
832
EXPORT_SYMBOL_GPL(rt2800_write_beacon);
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834 835
static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
						unsigned int beacon_base)
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{
	int i;

	/*
	 * For the Beacon base registers we only need to clear
	 * the whole TXWI which (when set to 0) will invalidate
	 * the entire beacon.
	 */
	for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
		rt2800_register_write(rt2x00dev, beacon_base + i, 0);
}

848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874
void rt2800_clear_beacon(struct queue_entry *entry)
{
	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
	u32 reg;

	/*
	 * Disable beaconing while we are reloading the beacon data,
	 * otherwise we might be sending out invalid data.
	 */
	rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);

	/*
	 * Clear beacon.
	 */
	rt2800_clear_beacon_register(rt2x00dev,
				     HW_BEACON_OFFSET(entry->entry_idx));

	/*
	 * Enabled beaconing again.
	 */
	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
}
EXPORT_SYMBOL_GPL(rt2800_clear_beacon);

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#ifdef CONFIG_RT2X00_LIB_DEBUGFS
const struct rt2x00debug rt2800_rt2x00debug = {
	.owner	= THIS_MODULE,
	.csr	= {
		.read		= rt2800_register_read,
		.write		= rt2800_register_write,
		.flags		= RT2X00DEBUGFS_OFFSET,
		.word_base	= CSR_REG_BASE,
		.word_size	= sizeof(u32),
		.word_count	= CSR_REG_SIZE / sizeof(u32),
	},
	.eeprom	= {
		.read		= rt2x00_eeprom_read,
		.write		= rt2x00_eeprom_write,
		.word_base	= EEPROM_BASE,
		.word_size	= sizeof(u16),
		.word_count	= EEPROM_SIZE / sizeof(u16),
	},
	.bbp	= {
		.read		= rt2800_bbp_read,
		.write		= rt2800_bbp_write,
		.word_base	= BBP_BASE,
		.word_size	= sizeof(u8),
		.word_count	= BBP_SIZE / sizeof(u8),
	},
	.rf	= {
		.read		= rt2x00_rf_read,
		.write		= rt2800_rf_write,
		.word_base	= RF_BASE,
		.word_size	= sizeof(u32),
		.word_count	= RF_SIZE / sizeof(u32),
	},
907 908 909 910 911 912 913
	.rfcsr	= {
		.read		= rt2800_rfcsr_read,
		.write		= rt2800_rfcsr_write,
		.word_base	= RFCSR_BASE,
		.word_size	= sizeof(u8),
		.word_count	= RFCSR_SIZE / sizeof(u8),
	},
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};
EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */

int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;

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	if (rt2x00_rt(rt2x00dev, RT3290)) {
		rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
		return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
	} else {
926 927
		rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
		return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
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	}
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}
EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);

#ifdef CONFIG_RT2X00_LIB_LEDS
static void rt2800_brightness_set(struct led_classdev *led_cdev,
				  enum led_brightness brightness)
{
	struct rt2x00_led *led =
	    container_of(led_cdev, struct rt2x00_led, led_dev);
	unsigned int enabled = brightness != LED_OFF;
	unsigned int bg_mode =
	    (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
	unsigned int polarity =
		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
				   EEPROM_FREQ_LED_POLARITY);
	unsigned int ledmode =
		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
				   EEPROM_FREQ_LED_MODE);
947
	u32 reg;
948

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	/* Check for SoC (SOC devices don't support MCU requests) */
	if (rt2x00_is_soc(led->rt2x00dev)) {
		rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);

		/* Set LED Polarity */
		rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);

		/* Set LED Mode */
		if (led->type == LED_TYPE_RADIO) {
			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
					   enabled ? 3 : 0);
		} else if (led->type == LED_TYPE_ASSOC) {
			rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
					   enabled ? 3 : 0);
		} else if (led->type == LED_TYPE_QUALITY) {
			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
					   enabled ? 3 : 0);
		}

		rt2800_register_write(led->rt2x00dev, LED_CFG, reg);

	} else {
		if (led->type == LED_TYPE_RADIO) {
			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
					      enabled ? 0x20 : 0);
		} else if (led->type == LED_TYPE_ASSOC) {
			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
					      enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
		} else if (led->type == LED_TYPE_QUALITY) {
			/*
			 * The brightness is divided into 6 levels (0 - 5),
			 * The specs tell us the following levels:
			 *	0, 1 ,3, 7, 15, 31
			 * to determine the level in a simple way we can simply
			 * work with bitshifting:
			 *	(1 << level) - 1
			 */
			rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
					      (1 << brightness / (LED_FULL / 6)) - 1,
					      polarity);
		}
990 991 992
	}
}

993
static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
994 995 996 997 998 999 1000 1001 1002 1003 1004 1005
		     struct rt2x00_led *led, enum led_type type)
{
	led->rt2x00dev = rt2x00dev;
	led->type = type;
	led->led_dev.brightness_set = rt2800_brightness_set;
	led->flags = LED_INITIALIZED;
}
#endif /* CONFIG_RT2X00_LIB_LEDS */

/*
 * Configuration handlers.
 */
1006 1007 1008
static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
			       const u8 *address,
			       int wcid)
1009 1010
{
	struct mac_wcid_entry wcid_entry;
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	u32 offset;

	offset = MAC_WCID_ENTRY(wcid);

	memset(&wcid_entry, 0xff, sizeof(wcid_entry));
	if (address)
		memcpy(wcid_entry.mac, address, ETH_ALEN);

	rt2800_register_multiwrite(rt2x00dev, offset,
				      &wcid_entry, sizeof(wcid_entry));
}

static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
{
	u32 offset;
	offset = MAC_WCID_ATTR_ENTRY(wcid);
	rt2800_register_write(rt2x00dev, offset, 0);
}

static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
					   int wcid, u32 bssidx)
{
	u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
	u32 reg;

	/*
	 * The BSS Idx numbers is split in a main value of 3 bits,
	 * and a extended field for adding one additional bit to the value.
	 */
	rt2800_register_read(rt2x00dev, offset, &reg);
	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
			   (bssidx & 0x8) >> 3);
	rt2800_register_write(rt2x00dev, offset, reg);
}

static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
					   struct rt2x00lib_crypto *crypto,
					   struct ieee80211_key_conf *key)
{
1051 1052 1053 1054 1055 1056
	struct mac_iveiv_entry iveiv_entry;
	u32 offset;
	u32 reg;

	offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);

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	if (crypto->cmd == SET_KEY) {
		rt2800_register_read(rt2x00dev, offset, &reg);
		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
				   !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
		/*
		 * Both the cipher as the BSS Idx numbers are split in a main
		 * value of 3 bits, and a extended field for adding one additional
		 * bit to the value.
		 */
		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
				   (crypto->cipher & 0x7));
		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
				   (crypto->cipher & 0x8) >> 3);
		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
		rt2800_register_write(rt2x00dev, offset, reg);
	} else {
1073 1074 1075 1076 1077 1078 1079
		/* Delete the cipher without touching the bssidx */
		rt2800_register_read(rt2x00dev, offset, &reg);
		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
		rt2800_register_write(rt2x00dev, offset, reg);
1080
	}
1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137

	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);

	memset(&iveiv_entry, 0, sizeof(iveiv_entry));
	if ((crypto->cipher == CIPHER_TKIP) ||
	    (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
	    (crypto->cipher == CIPHER_AES))
		iveiv_entry.iv[3] |= 0x20;
	iveiv_entry.iv[3] |= key->keyidx << 6;
	rt2800_register_multiwrite(rt2x00dev, offset,
				      &iveiv_entry, sizeof(iveiv_entry));
}

int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
			     struct rt2x00lib_crypto *crypto,
			     struct ieee80211_key_conf *key)
{
	struct hw_key_entry key_entry;
	struct rt2x00_field32 field;
	u32 offset;
	u32 reg;

	if (crypto->cmd == SET_KEY) {
		key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;

		memcpy(key_entry.key, crypto->key,
		       sizeof(key_entry.key));
		memcpy(key_entry.tx_mic, crypto->tx_mic,
		       sizeof(key_entry.tx_mic));
		memcpy(key_entry.rx_mic, crypto->rx_mic,
		       sizeof(key_entry.rx_mic));

		offset = SHARED_KEY_ENTRY(key->hw_key_idx);
		rt2800_register_multiwrite(rt2x00dev, offset,
					      &key_entry, sizeof(key_entry));
	}

	/*
	 * The cipher types are stored over multiple registers
	 * starting with SHARED_KEY_MODE_BASE each word will have
	 * 32 bits and contains the cipher types for 2 bssidx each.
	 * Using the correct defines correctly will cause overhead,
	 * so just calculate the correct offset.
	 */
	field.bit_offset = 4 * (key->hw_key_idx % 8);
	field.bit_mask = 0x7 << field.bit_offset;

	offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);

	rt2800_register_read(rt2x00dev, offset, &reg);
	rt2x00_set_field32(&reg, field,
			   (crypto->cmd == SET_KEY) * crypto->cipher);
	rt2800_register_write(rt2x00dev, offset, reg);

	/*
	 * Update WCID information
	 */
1138 1139 1140 1141
	rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
	rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
				       crypto->bssidx);
	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1142 1143 1144 1145 1146

	return 0;
}
EXPORT_SYMBOL_GPL(rt2800_config_shared_key);

1147
static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1148
{
1149
	struct mac_wcid_entry wcid_entry;
1150
	int idx;
1151
	u32 offset;
1152 1153

	/*
1154 1155
	 * Search for the first free WCID entry and return the corresponding
	 * index.
1156 1157 1158 1159 1160 1161 1162 1163 1164
	 *
	 * Make sure the WCID starts _after_ the last possible shared key
	 * entry (>32).
	 *
	 * Since parts of the pairwise key table might be shared with
	 * the beacon frame buffers 6 & 7 we should only write into the
	 * first 222 entries.
	 */
	for (idx = 33; idx <= 222; idx++) {
1165 1166 1167 1168
		offset = MAC_WCID_ENTRY(idx);
		rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
					  sizeof(wcid_entry));
		if (is_broadcast_ether_addr(wcid_entry.mac))
1169 1170
			return idx;
	}
1171 1172 1173 1174 1175

	/*
	 * Use -1 to indicate that we don't have any more space in the WCID
	 * table.
	 */
1176 1177 1178
	return -1;
}

1179 1180 1181 1182 1183 1184 1185 1186
int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
			       struct rt2x00lib_crypto *crypto,
			       struct ieee80211_key_conf *key)
{
	struct hw_key_entry key_entry;
	u32 offset;

	if (crypto->cmd == SET_KEY) {
1187 1188 1189 1190 1191
		/*
		 * Allow key configuration only for STAs that are
		 * known by the hw.
		 */
		if (crypto->wcid < 0)
1192
			return -ENOSPC;
1193
		key->hw_key_idx = crypto->wcid;
1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209

		memcpy(key_entry.key, crypto->key,
		       sizeof(key_entry.key));
		memcpy(key_entry.tx_mic, crypto->tx_mic,
		       sizeof(key_entry.tx_mic));
		memcpy(key_entry.rx_mic, crypto->rx_mic,
		       sizeof(key_entry.rx_mic));

		offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
		rt2800_register_multiwrite(rt2x00dev, offset,
					      &key_entry, sizeof(key_entry));
	}

	/*
	 * Update WCID information
	 */
1210
	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1211 1212 1213 1214 1215

	return 0;
}
EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);

1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262
int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
		   struct ieee80211_sta *sta)
{
	int wcid;
	struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);

	/*
	 * Find next free WCID.
	 */
	wcid = rt2800_find_wcid(rt2x00dev);

	/*
	 * Store selected wcid even if it is invalid so that we can
	 * later decide if the STA is uploaded into the hw.
	 */
	sta_priv->wcid = wcid;

	/*
	 * No space left in the device, however, we can still communicate
	 * with the STA -> No error.
	 */
	if (wcid < 0)
		return 0;

	/*
	 * Clean up WCID attributes and write STA address to the device.
	 */
	rt2800_delete_wcid_attr(rt2x00dev, wcid);
	rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
	rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
				       rt2x00lib_get_bssidx(rt2x00dev, vif));
	return 0;
}
EXPORT_SYMBOL_GPL(rt2800_sta_add);

int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
{
	/*
	 * Remove WCID entry, no need to clean the attributes as they will
	 * get renewed when the WCID is reused.
	 */
	rt2800_config_wcid(rt2x00dev, NULL, wcid);

	return 0;
}
EXPORT_SYMBOL_GPL(rt2800_sta_remove);

1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298
void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
			  const unsigned int filter_flags)
{
	u32 reg;

	/*
	 * Start configuration steps.
	 * Note that the version error will always be dropped
	 * and broadcast frames will always be accepted since
	 * there is no filter for it at this time.
	 */
	rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
			   !(filter_flags & FIF_FCSFAIL));
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
			   !(filter_flags & FIF_PLCPFAIL));
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
			   !(filter_flags & FIF_PROMISC_IN_BSS));
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
			   !(filter_flags & FIF_ALLMULTI));
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
			   !(filter_flags & FIF_CONTROL));
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
			   !(filter_flags & FIF_CONTROL));
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
			   !(filter_flags & FIF_CONTROL));
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
			   !(filter_flags & FIF_CONTROL));
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
			   !(filter_flags & FIF_CONTROL));
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
			   !(filter_flags & FIF_PSPOLL));
1299 1300 1301 1302
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
			   !(filter_flags & FIF_CONTROL));
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
			   !(filter_flags & FIF_CONTROL));
1303 1304 1305 1306 1307 1308 1309 1310 1311 1312
	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
			   !(filter_flags & FIF_CONTROL));
	rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
}
EXPORT_SYMBOL_GPL(rt2800_config_filter);

void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
			struct rt2x00intf_conf *conf, const unsigned int flags)
{
	u32 reg;
1313
	bool update_bssid = false;
1314 1315 1316 1317 1318 1319 1320 1321

	if (flags & CONFIG_UPDATE_TYPE) {
		/*
		 * Enable synchronisation.
		 */
		rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340

		if (conf->sync == TSF_SYNC_AP_NONE) {
			/*
			 * Tune beacon queue transmit parameters for AP mode
			 */
			rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
		} else {
			rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
		}
1341 1342 1343
	}

	if (flags & CONFIG_UPDATE_MAC) {
1344 1345 1346 1347 1348 1349 1350 1351 1352 1353
		if (flags & CONFIG_UPDATE_TYPE &&
		    conf->sync == TSF_SYNC_AP_NONE) {
			/*
			 * The BSSID register has to be set to our own mac
			 * address in AP mode.
			 */
			memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
			update_bssid = true;
		}

1354 1355 1356 1357 1358
		if (!is_zero_ether_addr((const u8 *)conf->mac)) {
			reg = le32_to_cpu(conf->mac[1]);
			rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
			conf->mac[1] = cpu_to_le32(reg);
		}
1359 1360 1361 1362 1363

		rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
					      conf->mac, sizeof(conf->mac));
	}

1364
	if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1365 1366 1367 1368 1369 1370
		if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
			reg = le32_to_cpu(conf->bssid[1]);
			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
			conf->bssid[1] = cpu_to_le32(reg);
		}
1371 1372 1373 1374 1375 1376 1377

		rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
					      conf->bssid, sizeof(conf->bssid));
	}
}
EXPORT_SYMBOL_GPL(rt2800_config_intf);

1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445
static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
				    struct rt2x00lib_erp *erp)
{
	bool any_sta_nongf = !!(erp->ht_opmode &
				IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
	u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
	u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
	u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
	u32 reg;

	/* default protection rate for HT20: OFDM 24M */
	mm20_rate = gf20_rate = 0x4004;

	/* default protection rate for HT40: duplicate OFDM 24M */
	mm40_rate = gf40_rate = 0x4084;

	switch (protection) {
	case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
		/*
		 * All STAs in this BSS are HT20/40 but there might be
		 * STAs not supporting greenfield mode.
		 * => Disable protection for HT transmissions.
		 */
		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;

		break;
	case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
		/*
		 * All STAs in this BSS are HT20 or HT20/40 but there
		 * might be STAs not supporting greenfield mode.
		 * => Protect all HT40 transmissions.
		 */
		mm20_mode = gf20_mode = 0;
		mm40_mode = gf40_mode = 2;

		break;
	case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
		/*
		 * Nonmember protection:
		 * According to 802.11n we _should_ protect all
		 * HT transmissions (but we don't have to).
		 *
		 * But if cts_protection is enabled we _shall_ protect
		 * all HT transmissions using a CCK rate.
		 *
		 * And if any station is non GF we _shall_ protect
		 * GF transmissions.
		 *
		 * We decide to protect everything
		 * -> fall through to mixed mode.
		 */
	case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
		/*
		 * Legacy STAs are present
		 * => Protect all HT transmissions.
		 */
		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;

		/*
		 * If erp protection is needed we have to protect HT
		 * transmissions with CCK 11M long preamble.
		 */
		if (erp->cts_protection) {
			/* don't duplicate RTS/CTS in CCK mode */
			mm20_rate = mm40_rate = 0x0003;
			gf20_rate = gf40_rate = 0x0003;
		}
		break;
1446
	}
1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473

	/* check for STAs not supporting greenfield mode */
	if (any_sta_nongf)
		gf20_mode = gf40_mode = 2;

	/* Update HT protection config */
	rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
}

1474 1475
void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
		       u32 changed)
1476 1477 1478
{
	u32 reg;

1479 1480 1481 1482 1483 1484 1485 1486
	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
		rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
		rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
				   !!erp->short_preamble);
		rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
				   !!erp->short_preamble);
		rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
	}
1487

1488 1489 1490 1491 1492 1493
	if (changed & BSS_CHANGED_ERP_CTS_PROT) {
		rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
		rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
				   erp->cts_protection ? 2 : 0);
		rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
	}
1494

1495 1496 1497 1498 1499
	if (changed & BSS_CHANGED_BASIC_RATES) {
		rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
					 erp->basic_rates);
		rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
	}
1500

1501 1502 1503 1504 1505
	if (changed & BSS_CHANGED_ERP_SLOT) {
		rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
		rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
				   erp->slot_time);
		rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1506

1507 1508 1509 1510
		rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
		rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
		rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
	}
1511

1512 1513 1514 1515 1516 1517
	if (changed & BSS_CHANGED_BEACON_INT) {
		rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
				   erp->beacon_int * 16);
		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
	}
1518 1519 1520

	if (changed & BSS_CHANGED_HT)
		rt2800_config_ht_opmode(rt2x00dev, erp);
1521 1522 1523
}
EXPORT_SYMBOL_GPL(rt2800_config_erp);

1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557
static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;
	u16 eeprom;
	u8 led_ctrl, led_g_mode, led_r_mode;

	rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
	if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
	} else {
		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
	}
	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);

	rt2800_register_read(rt2x00dev, LED_CFG, &reg);
	led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
	led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
	if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
	    led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
		rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
		led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
		if (led_ctrl == 0 || led_ctrl > 0x40) {
			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
			rt2800_register_write(rt2x00dev, LED_CFG, reg);
		} else {
			rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
					   (led_g_mode << 2) | led_r_mode, 1);
		}
	}
}

1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572
static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
				     enum antenna ant)
{
	u32 reg;
	u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
	u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;

	if (rt2x00_is_pci(rt2x00dev)) {
		rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
		rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
		rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
	} else if (rt2x00_is_usb(rt2x00dev))
		rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
				   eesk_pin, 0);

1573 1574 1575 1576
	rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
	rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
	rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1577 1578
}

1579 1580 1581 1582
void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
{
	u8 r1;
	u8 r3;
1583
	u16 eeprom;
1584 1585 1586 1587

	rt2800_bbp_read(rt2x00dev, 1, &r1);
	rt2800_bbp_read(rt2x00dev, 3, &r3);

1588 1589 1590 1591
	if (rt2x00_rt(rt2x00dev, RT3572) &&
	    test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
		rt2800_config_3572bt_ant(rt2x00dev);

1592 1593 1594
	/*
	 * Configure the TX antenna.
	 */
1595
	switch (ant->tx_chain_num) {
1596 1597 1598 1599
	case 1:
		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
		break;
	case 2:
1600 1601 1602 1603 1604
		if (rt2x00_rt(rt2x00dev, RT3572) &&
		    test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
		else
			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1605 1606
		break;
	case 3:
1607
		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1608 1609 1610 1611 1612 1613
		break;
	}

	/*
	 * Configure the RX antenna.
	 */
1614
	switch (ant->rx_chain_num) {
1615
	case 1:
1616 1617
		if (rt2x00_rt(rt2x00dev, RT3070) ||
		    rt2x00_rt(rt2x00dev, RT3090) ||
1618
		    rt2x00_rt(rt2x00dev, RT3352) ||
1619 1620 1621 1622 1623 1624 1625 1626
		    rt2x00_rt(rt2x00dev, RT3390)) {
			rt2x00_eeprom_read(rt2x00dev,
					   EEPROM_NIC_CONF1, &eeprom);
			if (rt2x00_get_field16(eeprom,
						EEPROM_NIC_CONF1_ANT_DIVERSITY))
				rt2800_set_ant_diversity(rt2x00dev,
						rt2x00dev->default_ant.rx);
		}
1627 1628 1629
		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
		break;
	case 2:
1630 1631 1632 1633 1634 1635 1636 1637 1638
		if (rt2x00_rt(rt2x00dev, RT3572) &&
		    test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
			rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
				rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
			rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
		} else {
			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
		}
1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672
		break;
	case 3:
		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
		break;
	}

	rt2800_bbp_write(rt2x00dev, 3, r3);
	rt2800_bbp_write(rt2x00dev, 1, r1);
}
EXPORT_SYMBOL_GPL(rt2800_config_ant);

static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
				   struct rt2x00lib_conf *libconf)
{
	u16 eeprom;
	short lna_gain;

	if (libconf->rf.channel <= 14) {
		rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
	} else if (libconf->rf.channel <= 64) {
		rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
	} else if (libconf->rf.channel <= 128) {
		rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
		lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
	} else {
		rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
		lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
	}

	rt2x00dev->lna_gain = lna_gain;
}

1673 1674 1675 1676
static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
					 struct ieee80211_conf *conf,
					 struct rf_channel *rf,
					 struct channel_info *info)
1677 1678 1679
{
	rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);

1680
	if (rt2x00dev->default_ant.tx_chain_num == 1)
1681 1682
		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);

1683
	if (rt2x00dev->default_ant.rx_chain_num == 1) {
1684 1685
		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1686
	} else if (rt2x00dev->default_ant.rx_chain_num == 2)
1687 1688 1689 1690 1691
		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);

	if (rf->channel > 14) {
		/*
		 * When TX power is below 0, we should increase it by 7 to
L
Lucas De Marchi 已提交
1692
		 * make it a positive value (Minimum value is -7).
1693 1694 1695 1696
		 * However this means that values between 0 and 7 have
		 * double meaning, and we should set a 7DBm boost flag.
		 */
		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1697
				   (info->default_power1 >= 0));
1698

1699 1700
		if (info->default_power1 < 0)
			info->default_power1 += 7;
1701

1702
		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1703 1704

		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1705
				   (info->default_power2 >= 0));
1706

1707 1708
		if (info->default_power2 < 0)
			info->default_power2 += 7;
1709

1710
		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1711
	} else {
1712 1713
		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737
	}

	rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));

	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
	rt2800_rf_write(rt2x00dev, 4, rf->rf4);

	udelay(200);

	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
	rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
	rt2800_rf_write(rt2x00dev, 4, rf->rf4);

	udelay(200);

	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
}

1738 1739 1740 1741
static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
					 struct ieee80211_conf *conf,
					 struct rf_channel *rf,
					 struct channel_info *info)
1742
{
1743
	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1744
	u8 rfcsr, calib_tx, calib_rx;
1745 1746

	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1747 1748 1749 1750

	rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1751 1752

	rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1753
	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1754 1755 1756
	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1757
	rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1758 1759
	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);

1760
	rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1761
	rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1762
	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1763 1764 1765

	rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1766 1767 1768 1769
	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
			  rt2x00dev->default_ant.rx_chain_num <= 1);
	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
			  rt2x00dev->default_ant.rx_chain_num <= 2);
1770
	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1771 1772 1773 1774
	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
			  rt2x00dev->default_ant.tx_chain_num <= 1);
	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
			  rt2x00dev->default_ant.tx_chain_num <= 2);
1775
	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1776

1777 1778 1779 1780 1781 1782 1783
	rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
	msleep(1);
	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);

1784 1785 1786 1787
	rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);

1788 1789 1790 1791
	if (rt2x00_rt(rt2x00dev, RT3390)) {
		calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
		calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
	} else {
1792 1793 1794 1795 1796 1797 1798
		if (conf_is_ht40(conf)) {
			calib_tx = drv_data->calibration_bw40;
			calib_rx = drv_data->calibration_bw40;
		} else {
			calib_tx = drv_data->calibration_bw20;
			calib_rx = drv_data->calibration_bw20;
		}
1799 1800 1801 1802 1803 1804 1805 1806 1807
	}

	rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1808

1809
	rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1810
	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1811
	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1812 1813 1814 1815 1816 1817 1818

	rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
	msleep(1);
	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1819 1820
}

1821 1822 1823 1824 1825
static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
					 struct ieee80211_conf *conf,
					 struct rf_channel *rf,
					 struct channel_info *info)
{
1826
	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1827 1828 1829 1830
	u8 rfcsr;
	u32 reg;

	if (rf->channel <= 14) {
1831 1832
		rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
		rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859
	} else {
		rt2800_bbp_write(rt2x00dev, 25, 0x09);
		rt2800_bbp_write(rt2x00dev, 26, 0xff);
	}

	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
	rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);

	rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
	if (rf->channel <= 14)
		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
	else
		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
	if (rf->channel <= 14)
		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
	else
		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
	rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
	if (rf->channel <= 14) {
		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1860
				  info->default_power1);
1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872
	} else {
		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
				(info->default_power1 & 0x3) |
				((info->default_power1 & 0xC) << 1));
	}
	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
	if (rf->channel <= 14) {
		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1873
				  info->default_power2);
1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886
	} else {
		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
				(info->default_power2 & 0x3) |
				((info->default_power2 & 0xC) << 1));
	}
	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1887 1888
	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918
	if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
		if (rf->channel <= 14) {
			rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
			rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
		}
		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
	} else {
		switch (rt2x00dev->default_ant.tx_chain_num) {
		case 1:
			rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
		case 2:
			rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
			break;
		}

		switch (rt2x00dev->default_ant.rx_chain_num) {
		case 1:
			rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
		case 2:
			rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
			break;
		}
	}
	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);

1919 1920 1921 1922 1923 1924 1925
	if (conf_is_ht40(conf)) {
		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
	} else {
		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
	}
1926 1927 1928 1929 1930 1931 1932

	if (rf->channel <= 14) {
		rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
		rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
		rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
		rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1933 1934 1935 1936
		rfcsr = 0x4c;
		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
				  drv_data->txmixer_gain_24g);
		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1937 1938 1939 1940 1941 1942 1943 1944
		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
		rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
		rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
		rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
		rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
		rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
	} else {
1945 1946 1947 1948 1949 1950
		rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
		rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
		rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
		rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1951 1952 1953 1954
		rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
		rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1955 1956 1957 1958
		rfcsr = 0x7a;
		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
				  drv_data->txmixer_gain_5g);
		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977
		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
		if (rf->channel <= 64) {
			rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
			rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
			rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
		} else if (rf->channel <= 128) {
			rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
			rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
		} else {
			rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
			rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
		}
		rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
		rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
		rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
	}

1978 1979
	rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
	rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
1980
	if (rf->channel <= 14)
1981
		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
1982
	else
1983 1984
		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1985 1986 1987 1988 1989

	rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
}
1990

1991 1992
#define POWER_BOUND		0x27
#define FREQ_OFFSET_BOUND	0x5f
1993

W
Woody Hung 已提交
1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007
static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
					 struct ieee80211_conf *conf,
					 struct rf_channel *rf,
					 struct channel_info *info)
{
	u8 rfcsr;

	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
	rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2008 2009
	if (info->default_power1 > POWER_BOUND)
		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
W
Woody Hung 已提交
2010 2011 2012 2013 2014
	else
		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2015 2016
	if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
		rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
W
Woody Hung 已提交
2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035
	else
		rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);

	if (rf->channel <= 14) {
		if (rf->channel == 6)
			rt2800_bbp_write(rt2x00dev, 68, 0x0c);
		else
			rt2800_bbp_write(rt2x00dev, 68, 0x0b);

		if (rf->channel >= 1 && rf->channel <= 6)
			rt2800_bbp_write(rt2x00dev, 59, 0x0f);
		else if (rf->channel >= 7 && rf->channel <= 11)
			rt2800_bbp_write(rt2x00dev, 59, 0x0e);
		else if (rf->channel >= 12 && rf->channel <= 14)
			rt2800_bbp_write(rt2x00dev, 59, 0x0d);
	}
}

2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089
static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
					 struct ieee80211_conf *conf,
					 struct rf_channel *rf,
					 struct channel_info *info)
{
	u8 rfcsr;

	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);

	rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
	rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);

	if (info->default_power1 > POWER_BOUND)
		rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
	else
		rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);

	if (info->default_power2 > POWER_BOUND)
		rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
	else
		rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);

	rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
	if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
		rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
	else
		rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);

	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);

	if ( rt2x00dev->default_ant.tx_chain_num == 2 )
		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
	else
		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);

	if ( rt2x00dev->default_ant.rx_chain_num == 2 )
		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
	else
		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);

	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);

	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);

	rt2800_rfcsr_write(rt2x00dev, 31, 80);
}

2090
static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103
					 struct ieee80211_conf *conf,
					 struct rf_channel *rf,
					 struct channel_info *info)
{
	u8 rfcsr;

	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
	rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2104 2105
	if (info->default_power1 > POWER_BOUND)
		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2106 2107 2108 2109
	else
		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);

Z
Zero.Lin 已提交
2110 2111
	if (rt2x00_rt(rt2x00dev, RT5392)) {
		rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2112 2113
		if (info->default_power1 > POWER_BOUND)
			rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
Z
Zero.Lin 已提交
2114 2115 2116 2117 2118 2119
		else
			rt2x00_set_field8(&rfcsr, RFCSR50_TX,
					  info->default_power2);
		rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
	}

2120
	rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
Z
Zero.Lin 已提交
2121 2122 2123 2124
	if (rt2x00_rt(rt2x00dev, RT5392)) {
		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
	}
2125 2126 2127 2128 2129 2130 2131
	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);

	rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2132 2133
	if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
		rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2134 2135 2136 2137 2138 2139 2140
	else
		rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);

	if (rf->channel <= 14) {
		int idx = rf->channel-1;

2141
		if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174
			if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
				/* r55/r59 value array of channel 1~14 */
				static const char r55_bt_rev[] = {0x83, 0x83,
					0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
					0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
				static const char r59_bt_rev[] = {0x0e, 0x0e,
					0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
					0x07, 0x07, 0x07, 0x07, 0x07, 0x07};

				rt2800_rfcsr_write(rt2x00dev, 55,
						   r55_bt_rev[idx]);
				rt2800_rfcsr_write(rt2x00dev, 59,
						   r59_bt_rev[idx]);
			} else {
				static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
					0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
					0x88, 0x88, 0x86, 0x85, 0x84};

				rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
			}
		} else {
			if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
				static const char r55_nonbt_rev[] = {0x23, 0x23,
					0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
					0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
				static const char r59_nonbt_rev[] = {0x07, 0x07,
					0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
					0x07, 0x07, 0x06, 0x05, 0x04, 0x04};

				rt2800_rfcsr_write(rt2x00dev, 55,
						   r55_nonbt_rev[idx]);
				rt2800_rfcsr_write(rt2x00dev, 59,
						   r59_nonbt_rev[idx]);
J
John Li 已提交
2175
			} else if (rt2x00_rt(rt2x00dev, RT5390) ||
2176
				   rt2x00_rt(rt2x00dev, RT5392)) {
2177 2178 2179 2180 2181 2182 2183 2184 2185
				static const char r59_non_bt[] = {0x8f, 0x8f,
					0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
					0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};

				rt2800_rfcsr_write(rt2x00dev, 59,
						   r59_non_bt[idx]);
			}
		}
	}
2186 2187
}

2188 2189 2190 2191 2192 2193 2194
static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
				  struct ieee80211_conf *conf,
				  struct rf_channel *rf,
				  struct channel_info *info)
{
	u32 reg;
	unsigned int tx_pin;
W
Woody Hung 已提交
2195
	u8 bbp, rfcsr;
2196

2197
	if (rf->channel <= 14) {
2198 2199
		info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
		info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2200
	} else {
2201 2202
		info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
		info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2203 2204
	}

2205 2206 2207 2208 2209 2210
	switch (rt2x00dev->chip.rf) {
	case RF2020:
	case RF3020:
	case RF3021:
	case RF3022:
	case RF3320:
2211
		rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2212 2213
		break;
	case RF3052:
2214
		rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2215
		break;
W
Woody Hung 已提交
2216 2217 2218
	case RF3290:
		rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
		break;
2219 2220 2221
	case RF3322:
		rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
		break;
2222
	case RF5360:
2223
	case RF5370:
J
John Li 已提交
2224
	case RF5372:
2225
	case RF5390:
Z
Zero.Lin 已提交
2226
	case RF5392:
2227
		rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2228 2229
		break;
	default:
2230
		rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2231
	}
2232

W
Woody Hung 已提交
2233
	if (rt2x00_rf(rt2x00dev, RF3290) ||
2234
	    rt2x00_rf(rt2x00dev, RF3322) ||
W
Woody Hung 已提交
2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249
	    rt2x00_rf(rt2x00dev, RF5360) ||
	    rt2x00_rf(rt2x00dev, RF5370) ||
	    rt2x00_rf(rt2x00dev, RF5372) ||
	    rt2x00_rf(rt2x00dev, RF5390) ||
	    rt2x00_rf(rt2x00dev, RF5392)) {
		rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
		rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
		rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);

		rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
	}

2250 2251 2252
	/*
	 * Change BBP settings
	 */
2253 2254
	if (rt2x00_rt(rt2x00dev, RT3352)) {
		rt2800_bbp_write(rt2x00dev, 27, 0x0);
2255
		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2256
		rt2800_bbp_write(rt2x00dev, 27, 0x20);
2257
		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2258 2259 2260 2261 2262 2263
	} else {
		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
		rt2800_bbp_write(rt2x00dev, 86, 0);
	}
2264 2265

	if (rf->channel <= 14) {
J
John Li 已提交
2266
		if (!rt2x00_rt(rt2x00dev, RT5390) &&
2267
		    !rt2x00_rt(rt2x00dev, RT5392)) {
I
Ivo van Doorn 已提交
2268 2269
			if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
				     &rt2x00dev->cap_flags)) {
2270 2271 2272 2273 2274 2275
				rt2800_bbp_write(rt2x00dev, 82, 0x62);
				rt2800_bbp_write(rt2x00dev, 75, 0x46);
			} else {
				rt2800_bbp_write(rt2x00dev, 82, 0x84);
				rt2800_bbp_write(rt2x00dev, 75, 0x50);
			}
2276 2277
		}
	} else {
2278 2279 2280 2281
		if (rt2x00_rt(rt2x00dev, RT3572))
			rt2800_bbp_write(rt2x00dev, 82, 0x94);
		else
			rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2282

I
Ivo van Doorn 已提交
2283
		if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2284 2285 2286 2287 2288 2289
			rt2800_bbp_write(rt2x00dev, 75, 0x46);
		else
			rt2800_bbp_write(rt2x00dev, 75, 0x50);
	}

	rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2290
	rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2291 2292 2293 2294
	rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
	rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
	rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);

2295 2296 2297
	if (rt2x00_rt(rt2x00dev, RT3572))
		rt2800_rfcsr_write(rt2x00dev, 8, 0);

2298 2299 2300
	tx_pin = 0;

	/* Turn on unused PA or LNA when not using 1T or 1R */
2301
	if (rt2x00dev->default_ant.tx_chain_num == 2) {
2302 2303 2304 2305
		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
				   rf->channel > 14);
		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
				   rf->channel <= 14);
2306 2307 2308
	}

	/* Turn on unused PA or LNA when not using 1T or 1R */
2309
	if (rt2x00dev->default_ant.rx_chain_num == 2) {
2310 2311 2312 2313 2314 2315 2316 2317
		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
	}

	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2318 2319 2320 2321 2322
	if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
	else
		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
				   rf->channel <= 14);
2323 2324 2325 2326
	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);

	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);

2327 2328 2329
	if (rt2x00_rt(rt2x00dev, RT3572))
		rt2800_rfcsr_write(rt2x00dev, 8, 0x80);

2330 2331 2332 2333 2334
	rt2800_bbp_read(rt2x00dev, 4, &bbp);
	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
	rt2800_bbp_write(rt2x00dev, 4, bbp);

	rt2800_bbp_read(rt2x00dev, 3, &bbp);
2335
	rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2336 2337
	rt2800_bbp_write(rt2x00dev, 3, bbp);

2338
	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350
		if (conf_is_ht40(conf)) {
			rt2800_bbp_write(rt2x00dev, 69, 0x1a);
			rt2800_bbp_write(rt2x00dev, 70, 0x0a);
			rt2800_bbp_write(rt2x00dev, 73, 0x16);
		} else {
			rt2800_bbp_write(rt2x00dev, 69, 0x16);
			rt2800_bbp_write(rt2x00dev, 70, 0x08);
			rt2800_bbp_write(rt2x00dev, 73, 0x11);
		}
	}

	msleep(1);
2351 2352 2353 2354 2355 2356 2357

	/*
	 * Clear channel statistic counters
	 */
	rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
	rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
	rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2358 2359 2360 2361 2362 2363 2364 2365 2366

	/*
	 * Clear update flag
	 */
	if (rt2x00_rt(rt2x00dev, RT3352)) {
		rt2800_bbp_read(rt2x00dev, 49, &bbp);
		rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
		rt2800_bbp_write(rt2x00dev, 49, bbp);
	}
2367 2368
}

2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451
static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
{
	u8 tssi_bounds[9];
	u8 current_tssi;
	u16 eeprom;
	u8 step;
	int i;

	/*
	 * Read TSSI boundaries for temperature compensation from
	 * the EEPROM.
	 *
	 * Array idx               0    1    2    3    4    5    6    7    8
	 * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
	 * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
	 */
	if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
		rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
		tssi_bounds[0] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_BG1_MINUS4);
		tssi_bounds[1] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_BG1_MINUS3);

		rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
		tssi_bounds[2] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_BG2_MINUS2);
		tssi_bounds[3] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_BG2_MINUS1);

		rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
		tssi_bounds[4] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_BG3_REF);
		tssi_bounds[5] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_BG3_PLUS1);

		rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
		tssi_bounds[6] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_BG4_PLUS2);
		tssi_bounds[7] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_BG4_PLUS3);

		rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
		tssi_bounds[8] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_BG5_PLUS4);

		step = rt2x00_get_field16(eeprom,
					  EEPROM_TSSI_BOUND_BG5_AGC_STEP);
	} else {
		rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
		tssi_bounds[0] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_A1_MINUS4);
		tssi_bounds[1] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_A1_MINUS3);

		rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
		tssi_bounds[2] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_A2_MINUS2);
		tssi_bounds[3] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_A2_MINUS1);

		rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
		tssi_bounds[4] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_A3_REF);
		tssi_bounds[5] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_A3_PLUS1);

		rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
		tssi_bounds[6] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_A4_PLUS2);
		tssi_bounds[7] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_A4_PLUS3);

		rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
		tssi_bounds[8] = rt2x00_get_field16(eeprom,
					EEPROM_TSSI_BOUND_A5_PLUS4);

		step = rt2x00_get_field16(eeprom,
					  EEPROM_TSSI_BOUND_A5_AGC_STEP);
	}

	/*
	 * Check if temperature compensation is supported.
	 */
2452
	if (tssi_bounds[4] == 0xff || step == 0xff)
2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478
		return 0;

	/*
	 * Read current TSSI (BBP 49).
	 */
	rt2800_bbp_read(rt2x00dev, 49, &current_tssi);

	/*
	 * Compare TSSI value (BBP49) with the compensation boundaries
	 * from the EEPROM and increase or decrease tx power.
	 */
	for (i = 0; i <= 3; i++) {
		if (current_tssi > tssi_bounds[i])
			break;
	}

	if (i == 4) {
		for (i = 8; i >= 5; i--) {
			if (current_tssi < tssi_bounds[i])
				break;
		}
	}

	return (i - 4) * step;
}

2479 2480 2481 2482 2483 2484
static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
				      enum ieee80211_band band)
{
	u16 eeprom;
	u8 comp_en;
	u8 comp_type;
2485
	int comp_value = 0;
2486 2487 2488

	rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);

2489 2490 2491 2492 2493
	/*
	 * HT40 compensation not required.
	 */
	if (eeprom == 0xffff ||
	    !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522
		return 0;

	if (band == IEEE80211_BAND_2GHZ) {
		comp_en = rt2x00_get_field16(eeprom,
				 EEPROM_TXPOWER_DELTA_ENABLE_2G);
		if (comp_en) {
			comp_type = rt2x00_get_field16(eeprom,
					   EEPROM_TXPOWER_DELTA_TYPE_2G);
			comp_value = rt2x00_get_field16(eeprom,
					    EEPROM_TXPOWER_DELTA_VALUE_2G);
			if (!comp_type)
				comp_value = -comp_value;
		}
	} else {
		comp_en = rt2x00_get_field16(eeprom,
				 EEPROM_TXPOWER_DELTA_ENABLE_5G);
		if (comp_en) {
			comp_type = rt2x00_get_field16(eeprom,
					   EEPROM_TXPOWER_DELTA_TYPE_5G);
			comp_value = rt2x00_get_field16(eeprom,
					    EEPROM_TXPOWER_DELTA_VALUE_5G);
			if (!comp_type)
				comp_value = -comp_value;
		}
	}

	return comp_value;
}

2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543
static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
					int power_level, int max_power)
{
	int delta;

	if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
		return 0;

	/*
	 * XXX: We don't know the maximum transmit power of our hardware since
	 * the EEPROM doesn't expose it. We only know that we are calibrated
	 * to 100% tx power.
	 *
	 * Hence, we assume the regulatory limit that cfg80211 calulated for
	 * the current channel is our maximum and if we are requested to lower
	 * the value we just reduce our tx power accordingly.
	 */
	delta = power_level - max_power;
	return min(delta, 0);
}

2544 2545 2546
static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
				   enum ieee80211_band band, int power_level,
				   u8 txpower, int delta)
2547 2548 2549 2550 2551 2552 2553
{
	u16 eeprom;
	u8 criterion;
	u8 eirp_txpower;
	u8 eirp_txpower_criterion;
	u8 reg_limit;

I
Ivo van Doorn 已提交
2554
	if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2555 2556 2557 2558 2559 2560 2561
		/*
		 * Check if eirp txpower exceed txpower_limit.
		 * We use OFDM 6M as criterion and its eirp txpower
		 * is stored at EEPROM_EIRP_MAX_TX_POWER.
		 * .11b data rate need add additional 4dbm
		 * when calculating eirp txpower.
		 */
2562 2563 2564 2565
		rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
				   &eeprom);
		criterion = rt2x00_get_field16(eeprom,
					       EEPROM_TXPOWER_BYRATE_RATE0);
2566

2567 2568
		rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
				   &eeprom);
2569 2570 2571 2572 2573 2574 2575 2576 2577

		if (band == IEEE80211_BAND_2GHZ)
			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
						 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
		else
			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
						 EEPROM_EIRP_MAX_TX_POWER_5GHZ);

		eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2578
			       (is_rate_b ? 4 : 0) + delta;
2579 2580 2581 2582 2583 2584

		reg_limit = (eirp_txpower > power_level) ?
					(eirp_txpower - power_level) : 0;
	} else
		reg_limit = 0;

2585 2586
	txpower = max(0, txpower + delta - reg_limit);
	return min_t(u8, txpower, 0xc);
2587 2588
}

2589 2590 2591 2592 2593 2594 2595 2596 2597
/*
 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
 * Reference per rate transmit power values are located in the EEPROM at
 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
 * current conditions (i.e. band, bandwidth, temperature, user settings).
 */
2598
static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2599
				  struct ieee80211_channel *chan,
2600
				  int power_level)
2601
{
2602
	u8 txpower, r1;
2603
	u16 eeprom;
2604 2605
	u32 reg, offset;
	int i, is_rate_b, delta, power_ctrl;
2606
	enum ieee80211_band band = chan->band;
2607 2608

	/*
2609 2610
	 * Calculate HT40 compensation. For 40MHz we need to add or subtract
	 * value read from EEPROM (different for 2GHz and for 5GHz).
2611 2612
	 */
	delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2613

2614
	/*
2615 2616 2617 2618 2619
	 * Calculate temperature compensation. Depends on measurement of current
	 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
	 * to temperature or maybe other factors) is smaller or bigger than
	 * expected. We adjust it, based on TSSI reference and boundaries values
	 * provided in EEPROM.
2620 2621
	 */
	delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2622

2623
	/*
2624 2625 2626
	 * Decrease power according to user settings, on devices with unknown
	 * maximum tx power. For other devices we take user power_level into
	 * consideration on rt2800_compensate_txpower().
2627 2628 2629 2630
	 */
	delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
					      chan->max_power);

2631
	/*
2632 2633 2634 2635 2636 2637
	 * BBP_R1 controls TX power for all rates, it allow to set the following
	 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
	 *
	 * TODO: we do not use +6 dBm option to do not increase power beyond
	 * regulatory limit, however this could be utilized for devices with
	 * CAPABILITY_POWER_LIMIT.
2638
	 */
2639
	rt2800_bbp_read(rt2x00dev, 1, &r1);
2640 2641 2642 2643 2644 2645 2646 2647 2648 2649
	if (delta <= -12) {
		power_ctrl = 2;
		delta += 12;
	} else if (delta <= -6) {
		power_ctrl = 1;
		delta += 6;
	} else {
		power_ctrl = 0;
	}
	rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
2650
	rt2800_bbp_write(rt2x00dev, 1, r1);
2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663
	offset = TX_PWR_CFG_0;

	for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
		/* just to be safe */
		if (offset > TX_PWR_CFG_4)
			break;

		rt2800_register_read(rt2x00dev, offset, &reg);

		/* read the next four txpower values */
		rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
				   &eeprom);

2664 2665 2666
		is_rate_b = i ? 0 : 1;
		/*
		 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2667
		 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2668 2669
		 * TX_PWR_CFG_4: unknown
		 */
2670 2671
		txpower = rt2x00_get_field16(eeprom,
					     EEPROM_TXPOWER_BYRATE_RATE0);
2672
		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2673
					     power_level, txpower, delta);
2674
		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2675

2676 2677
		/*
		 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2678
		 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2679 2680
		 * TX_PWR_CFG_4: unknown
		 */
2681 2682
		txpower = rt2x00_get_field16(eeprom,
					     EEPROM_TXPOWER_BYRATE_RATE1);
2683
		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2684
					     power_level, txpower, delta);
2685
		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2686

2687 2688
		/*
		 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2689
		 * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2690 2691
		 * TX_PWR_CFG_4: unknown
		 */
2692 2693
		txpower = rt2x00_get_field16(eeprom,
					     EEPROM_TXPOWER_BYRATE_RATE2);
2694
		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2695
					     power_level, txpower, delta);
2696
		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2697

2698 2699
		/*
		 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2700
		 * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2701 2702
		 * TX_PWR_CFG_4: unknown
		 */
2703 2704
		txpower = rt2x00_get_field16(eeprom,
					     EEPROM_TXPOWER_BYRATE_RATE3);
2705
		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2706
					     power_level, txpower, delta);
2707
		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2708 2709 2710 2711 2712

		/* read the next four txpower values */
		rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
				   &eeprom);

2713 2714 2715
		is_rate_b = 0;
		/*
		 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2716
		 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2717 2718
		 * TX_PWR_CFG_4: unknown
		 */
2719 2720
		txpower = rt2x00_get_field16(eeprom,
					     EEPROM_TXPOWER_BYRATE_RATE0);
2721
		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2722
					     power_level, txpower, delta);
2723
		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2724

2725 2726
		/*
		 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2727
		 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2728 2729
		 * TX_PWR_CFG_4: unknown
		 */
2730 2731
		txpower = rt2x00_get_field16(eeprom,
					     EEPROM_TXPOWER_BYRATE_RATE1);
2732
		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2733
					     power_level, txpower, delta);
2734
		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2735

2736 2737
		/*
		 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2738
		 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2739 2740
		 * TX_PWR_CFG_4: unknown
		 */
2741 2742
		txpower = rt2x00_get_field16(eeprom,
					     EEPROM_TXPOWER_BYRATE_RATE2);
2743
		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2744
					     power_level, txpower, delta);
2745
		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2746

2747 2748
		/*
		 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2749
		 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2750 2751
		 * TX_PWR_CFG_4: unknown
		 */
2752 2753
		txpower = rt2x00_get_field16(eeprom,
					     EEPROM_TXPOWER_BYRATE_RATE3);
2754
		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2755
					     power_level, txpower, delta);
2756
		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2757 2758 2759 2760 2761 2762

		rt2800_register_write(rt2x00dev, offset, reg);

		/* next TX_PWR_CFG register */
		offset += 4;
	}
2763 2764
}

2765 2766
void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
{
2767
	rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.channel,
2768 2769 2770 2771
			      rt2x00dev->tx_power);
}
EXPORT_SYMBOL_GPL(rt2800_gain_calibration);

J
John Li 已提交
2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799
void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
{
	u32	tx_pin;
	u8	rfcsr;

	/*
	 * A voltage-controlled oscillator(VCO) is an electronic oscillator
	 * designed to be controlled in oscillation frequency by a voltage
	 * input. Maybe the temperature will affect the frequency of
	 * oscillation to be shifted. The VCO calibration will be called
	 * periodically to adjust the frequency to be precision.
	*/

	rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
	tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);

	switch (rt2x00dev->chip.rf) {
	case RF2020:
	case RF3020:
	case RF3021:
	case RF3022:
	case RF3320:
	case RF3052:
		rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
		break;
W
Woody Hung 已提交
2800
	case RF3290:
2801
	case RF5360:
J
John Li 已提交
2802 2803 2804
	case RF5370:
	case RF5372:
	case RF5390:
Z
Zero.Lin 已提交
2805
	case RF5392:
J
John Li 已提交
2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848
		rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
		break;
	default:
		return;
	}

	mdelay(1);

	rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
	if (rt2x00dev->rf_channel <= 14) {
		switch (rt2x00dev->default_ant.tx_chain_num) {
		case 3:
			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
			/* fall through */
		case 2:
			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
			/* fall through */
		case 1:
		default:
			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
			break;
		}
	} else {
		switch (rt2x00dev->default_ant.tx_chain_num) {
		case 3:
			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
			/* fall through */
		case 2:
			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
			/* fall through */
		case 1:
		default:
			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
			break;
		}
	}
	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);

}
EXPORT_SYMBOL_GPL(rt2800_vco_calibration);

2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886
static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
				      struct rt2x00lib_conf *libconf)
{
	u32 reg;

	rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
			   libconf->conf->short_frame_max_tx_count);
	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
			   libconf->conf->long_frame_max_tx_count);
	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
}

static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
			     struct rt2x00lib_conf *libconf)
{
	enum dev_state state =
	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
		STATE_SLEEP : STATE_AWAKE;
	u32 reg;

	if (state == STATE_SLEEP) {
		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);

		rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
				   libconf->conf->listen_interval - 1);
		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);

		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
	} else {
		rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2887 2888

		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2889 2890 2891 2892 2893 2894 2895 2896 2897 2898
	}
}

void rt2800_config(struct rt2x00_dev *rt2x00dev,
		   struct rt2x00lib_conf *libconf,
		   const unsigned int flags)
{
	/* Always recalculate LNA gain before changing configuration */
	rt2800_config_lna_gain(rt2x00dev, libconf);

2899
	if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2900 2901
		rt2800_config_channel(rt2x00dev, libconf->conf,
				      &libconf->rf, &libconf->channel);
2902
		rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
2903
				      libconf->conf->power_level);
2904
	}
2905
	if (flags & IEEE80211_CONF_CHANGE_POWER)
2906
		rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
2907
				      libconf->conf->power_level);
2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931
	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
		rt2800_config_retry_limit(rt2x00dev, libconf);
	if (flags & IEEE80211_CONF_CHANGE_PS)
		rt2800_config_ps(rt2x00dev, libconf);
}
EXPORT_SYMBOL_GPL(rt2800_config);

/*
 * Link tuning
 */
void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
{
	u32 reg;

	/*
	 * Update FCS error count from register.
	 */
	rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
	qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
}
EXPORT_SYMBOL_GPL(rt2800_link_stats);

static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
{
2932 2933
	u8 vgc;

2934
	if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2935
		if (rt2x00_rt(rt2x00dev, RT3070) ||
2936
		    rt2x00_rt(rt2x00dev, RT3071) ||
2937
		    rt2x00_rt(rt2x00dev, RT3090) ||
W
Woody Hung 已提交
2938
		    rt2x00_rt(rt2x00dev, RT3290) ||
2939
		    rt2x00_rt(rt2x00dev, RT3390) ||
2940
		    rt2x00_rt(rt2x00dev, RT3572) ||
J
John Li 已提交
2941 2942
		    rt2x00_rt(rt2x00dev, RT5390) ||
		    rt2x00_rt(rt2x00dev, RT5392))
2943 2944 2945 2946
			vgc = 0x1c + (2 * rt2x00dev->lna_gain);
		else
			vgc = 0x2e + rt2x00dev->lna_gain;
	} else { /* 5GHZ band */
2947 2948 2949 2950 2951 2952 2953 2954
		if (rt2x00_rt(rt2x00dev, RT3572))
			vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
		else {
			if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
				vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
			else
				vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
		}
2955 2956
	}

2957
	return vgc;
2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978
}

static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
				  struct link_qual *qual, u8 vgc_level)
{
	if (qual->vgc_level != vgc_level) {
		rt2800_bbp_write(rt2x00dev, 66, vgc_level);
		qual->vgc_level = vgc_level;
		qual->vgc_level_reg = vgc_level;
	}
}

void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
{
	rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
}
EXPORT_SYMBOL_GPL(rt2800_reset_tuner);

void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
		       const u32 count)
{
2979
	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2980 2981 2982 2983 2984 2985 2986 2987 2988 2989
		return;

	/*
	 * When RSSI is better then -80 increase VGC level with 0x10
	 */
	rt2800_set_vgc(rt2x00dev, qual,
		       rt2800_get_default_vgc(rt2x00dev) +
		       ((qual->rssi > -80) * 0x10));
}
EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2990 2991 2992 2993

/*
 * Initialization functions.
 */
2994
static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2995 2996
{
	u32 reg;
2997
	u16 eeprom;
2998
	unsigned int i;
2999
	int ret;
3000

3001
	rt2800_disable_wpdma(rt2x00dev);
3002

3003 3004 3005
	ret = rt2800_drv_init_registers(rt2x00dev);
	if (ret)
		return ret;
3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026

	rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
	rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
	rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
	rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
	rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
	rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);

	rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
	rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
	rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
	rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
	rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
	rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);

	rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
	rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);

	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);

	rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
3027
	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
3028 3029 3030 3031 3032 3033 3034
	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
	rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
	rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);

3035 3036 3037 3038 3039 3040 3041
	rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);

	rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
	rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);

W
Woody Hung 已提交
3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077
	if (rt2x00_rt(rt2x00dev, RT3290)) {
		rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
		if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
			rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
			rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
		}

		rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
		if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
			rt2x00_set_field32(&reg, LDO0_EN, 1);
			rt2x00_set_field32(&reg, LDO_BGSEL, 3);
			rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
		}

		rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
		rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
		rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
		rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
		rt2800_register_write(rt2x00dev, OSC_CTRL, reg);

		rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
		rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
		rt2800_register_write(rt2x00dev, COEX_CFG0, reg);

		rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
		rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
		rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
		rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
		rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
		rt2800_register_write(rt2x00dev, COEX_CFG2, reg);

		rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
		rt2x00_set_field32(&reg, PLL_CONTROL, 1);
		rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
	}

3078
	if (rt2x00_rt(rt2x00dev, RT3071) ||
3079
	    rt2x00_rt(rt2x00dev, RT3090) ||
W
Woody Hung 已提交
3080
	    rt2x00_rt(rt2x00dev, RT3290) ||
3081
	    rt2x00_rt(rt2x00dev, RT3390)) {
W
Woody Hung 已提交
3082 3083 3084 3085 3086 3087 3088 3089

		if (rt2x00_rt(rt2x00dev, RT3290))
			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
					      0x00000404);
		else
			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
					      0x00000400);

3090
		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3091
		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3092 3093
		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
		    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
R
RA-Jay Hung 已提交
3094 3095
			rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3096 3097 3098 3099 3100 3101 3102 3103 3104
				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
						      0x0000002c);
			else
				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
						      0x0000000f);
		} else {
			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
		}
	} else if (rt2x00_rt(rt2x00dev, RT3070)) {
3105
		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3106 3107 3108 3109 3110 3111 3112 3113

		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
		} else {
			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
		}
3114 3115 3116
	} else if (rt2800_is_305x_soc(rt2x00dev)) {
		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3117
		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3118 3119 3120 3121
	} else if (rt2x00_rt(rt2x00dev, RT3352)) {
		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3122 3123 3124
	} else if (rt2x00_rt(rt2x00dev, RT3572)) {
		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
J
John Li 已提交
3125
	} else if (rt2x00_rt(rt2x00dev, RT5390) ||
3126
		   rt2x00_rt(rt2x00dev, RT5392)) {
3127 3128 3129
		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147
	} else {
		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
	}

	rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
	rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
	rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);

	rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
3148
	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
3149 3150 3151 3152 3153
	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
	rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);

	rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
3154
	if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
3155
	    rt2x00_rt(rt2x00dev, RT2883) ||
3156
	    rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
3157 3158 3159 3160 3161 3162 3163
		rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
	else
		rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
	rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);

3164 3165 3166 3167 3168 3169 3170 3171 3172 3173
	rt2800_register_read(rt2x00dev, LED_CFG, &reg);
	rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
	rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
	rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
	rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
	rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
	rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
	rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
	rt2800_register_write(rt2x00dev, LED_CFG, reg);

3174 3175
	rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);

3176 3177 3178 3179 3180 3181 3182 3183 3184
	rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
	rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
	rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
	rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);

3185 3186
	rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
3187
	rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
3188 3189
	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
3190
	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3191 3192 3193 3194 3195
	rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
	rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
	rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);

	rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3196
	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
3197
	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
3198
	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3199 3200 3201
	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3202
	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3203
	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3204 3205
	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
3206 3207 3208
	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3209
	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
3210
	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3211
	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3212 3213 3214
	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3215
	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3216
	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3217 3218
	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
3219 3220 3221 3222 3223
	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
3224
	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3225 3226 3227 3228 3229 3230
	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3231
	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
3232 3233 3234 3235
	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3236
	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
3237
	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3238 3239 3240 3241 3242 3243
	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3244
	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
3245 3246 3247 3248 3249
	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
3250
	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3251 3252 3253 3254 3255 3256
	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3257
	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
3258 3259 3260 3261 3262
	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
3263
	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3264 3265 3266 3267 3268 3269
	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3270
	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
3271 3272
	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);

3273
	if (rt2x00_is_usb(rt2x00dev)) {
3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288
		rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);

		rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
		rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
	}

3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305
	/*
	 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
	 * although it is reserved.
	 */
	rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
	rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);

3306 3307 3308 3309 3310 3311 3312 3313 3314 3315
	rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);

	rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
	rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
			   IEEE80211_MAX_RTS_THRESHOLD);
	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);

	rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3316

3317 3318 3319 3320 3321 3322 3323
	/*
	 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
	 * time should be set to 16. However, the original Ralink driver uses
	 * 16 for both and indeed using a value of 10 for CCK SIFS results in
	 * connection problems with 11g + CTS protection. Hence, use the same
	 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
	 */
3324
	rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3325 3326
	rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3327 3328 3329 3330 3331
	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
	rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
	rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
	rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);

3332 3333 3334 3335 3336 3337 3338 3339 3340 3341
	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);

	/*
	 * ASIC will keep garbage value after boot, clear encryption keys.
	 */
	for (i = 0; i < 4; i++)
		rt2800_register_write(rt2x00dev,
					 SHARED_KEY_MODE_ENTRY(i), 0);

	for (i = 0; i < 256; i++) {
3342 3343
		rt2800_config_wcid(rt2x00dev, NULL, i);
		rt2800_delete_wcid_attr(rt2x00dev, i);
3344 3345 3346 3347 3348 3349
		rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
	}

	/*
	 * Clear all beacons
	 */
3350 3351 3352 3353 3354 3355 3356 3357
	rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
	rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
	rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
	rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
	rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
	rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
	rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
	rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3358

3359
	if (rt2x00_is_usb(rt2x00dev)) {
3360 3361 3362
		rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3363 3364 3365 3366
	} else if (rt2x00_is_pcie(rt2x00dev)) {
		rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408
	}

	rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
	rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);

	rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
	rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);

	rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
	rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);

	rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
	rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);

3409 3410 3411 3412 3413 3414 3415 3416
	/*
	 * Do not force the BA window size, we use the TXWI to set it
	 */
	rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
	rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);

3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428
	/*
	 * We must clear the error counters.
	 * These registers are cleared on read,
	 * so we may pass a useless variable to store the value.
	 */
	rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
	rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
	rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
	rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
	rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
	rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);

3429 3430 3431 3432 3433 3434 3435
	/*
	 * Setup leadtime for pre tbtt interrupt to 6ms
	 */
	rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
	rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
	rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);

3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446
	/*
	 * Set up channel statistics timer
	 */
	rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
	rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
	rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
	rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
	rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
	rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
	rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);

3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490
	return 0;
}

static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
{
	unsigned int i;
	u32 reg;

	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
		rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
		if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
			return 0;

		udelay(REGISTER_BUSY_DELAY);
	}

	ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
	return -EACCES;
}

static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
{
	unsigned int i;
	u8 value;

	/*
	 * BBP was enabled after firmware was loaded,
	 * but we need to reactivate it now.
	 */
	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
	msleep(1);

	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
		rt2800_bbp_read(rt2x00dev, 0, &value);
		if ((value != 0xff) && (value != 0x00))
			return 0;
		udelay(REGISTER_BUSY_DELAY);
	}

	ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
	return -EACCES;
}

3491
static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3492 3493 3494 3495 3496 3497 3498 3499 3500 3501
{
	unsigned int i;
	u16 eeprom;
	u8 reg_id;
	u8 value;

	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
		     rt2800_wait_bbp_ready(rt2x00dev)))
		return -EACCES;

3502 3503 3504 3505 3506
	if (rt2x00_rt(rt2x00dev, RT3352)) {
		rt2800_bbp_write(rt2x00dev, 3, 0x00);
		rt2800_bbp_write(rt2x00dev, 4, 0x50);
	}

W
Woody Hung 已提交
3507 3508 3509
	if (rt2x00_rt(rt2x00dev, RT3290) ||
	    rt2x00_rt(rt2x00dev, RT5390) ||
	    rt2x00_rt(rt2x00dev, RT5392)) {
3510 3511 3512 3513
		rt2800_bbp_read(rt2x00dev, 4, &value);
		rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
		rt2800_bbp_write(rt2x00dev, 4, value);
	}
3514

3515
	if (rt2800_is_305x_soc(rt2x00dev) ||
W
Woody Hung 已提交
3516
	    rt2x00_rt(rt2x00dev, RT3290) ||
3517
	    rt2x00_rt(rt2x00dev, RT3352) ||
3518
	    rt2x00_rt(rt2x00dev, RT3572) ||
J
John Li 已提交
3519 3520
	    rt2x00_rt(rt2x00dev, RT5390) ||
	    rt2x00_rt(rt2x00dev, RT5392))
3521 3522
		rt2800_bbp_write(rt2x00dev, 31, 0x08);

3523 3524 3525
	if (rt2x00_rt(rt2x00dev, RT3352))
		rt2800_bbp_write(rt2x00dev, 47, 0x48);

3526 3527
	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
	rt2800_bbp_write(rt2x00dev, 66, 0x38);
3528

W
Woody Hung 已提交
3529
	if (rt2x00_rt(rt2x00dev, RT3290) ||
3530
	    rt2x00_rt(rt2x00dev, RT3352) ||
W
Woody Hung 已提交
3531 3532
	    rt2x00_rt(rt2x00dev, RT5390) ||
	    rt2x00_rt(rt2x00dev, RT5392))
3533
		rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3534

3535 3536 3537
	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
		rt2800_bbp_write(rt2x00dev, 69, 0x16);
		rt2800_bbp_write(rt2x00dev, 73, 0x12);
W
Woody Hung 已提交
3538
	} else if (rt2x00_rt(rt2x00dev, RT3290) ||
3539
		   rt2x00_rt(rt2x00dev, RT3352) ||
W
Woody Hung 已提交
3540 3541
		   rt2x00_rt(rt2x00dev, RT5390) ||
		   rt2x00_rt(rt2x00dev, RT5392)) {
3542 3543 3544 3545
		rt2800_bbp_write(rt2x00dev, 69, 0x12);
		rt2800_bbp_write(rt2x00dev, 73, 0x13);
		rt2800_bbp_write(rt2x00dev, 75, 0x46);
		rt2800_bbp_write(rt2x00dev, 76, 0x28);
W
Woody Hung 已提交
3546 3547 3548 3549 3550

		if (rt2x00_rt(rt2x00dev, RT3290))
			rt2800_bbp_write(rt2x00dev, 77, 0x58);
		else
			rt2800_bbp_write(rt2x00dev, 77, 0x59);
3551 3552 3553 3554 3555
	} else {
		rt2800_bbp_write(rt2x00dev, 69, 0x12);
		rt2800_bbp_write(rt2x00dev, 73, 0x10);
	}

3556
	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3557

3558
	if (rt2x00_rt(rt2x00dev, RT3070) ||
3559
	    rt2x00_rt(rt2x00dev, RT3071) ||
3560
	    rt2x00_rt(rt2x00dev, RT3090) ||
3561
	    rt2x00_rt(rt2x00dev, RT3390) ||
3562
	    rt2x00_rt(rt2x00dev, RT3572) ||
J
John Li 已提交
3563 3564
	    rt2x00_rt(rt2x00dev, RT5390) ||
	    rt2x00_rt(rt2x00dev, RT5392)) {
3565 3566 3567
		rt2800_bbp_write(rt2x00dev, 79, 0x13);
		rt2800_bbp_write(rt2x00dev, 80, 0x05);
		rt2800_bbp_write(rt2x00dev, 81, 0x33);
3568 3569 3570
	} else if (rt2800_is_305x_soc(rt2x00dev)) {
		rt2800_bbp_write(rt2x00dev, 78, 0x0e);
		rt2800_bbp_write(rt2x00dev, 80, 0x08);
3571 3572 3573 3574 3575
	} else if (rt2x00_rt(rt2x00dev, RT3290)) {
		rt2800_bbp_write(rt2x00dev, 74, 0x0b);
		rt2800_bbp_write(rt2x00dev, 79, 0x18);
		rt2800_bbp_write(rt2x00dev, 80, 0x09);
		rt2800_bbp_write(rt2x00dev, 81, 0x33);
3576 3577 3578 3579
	} else if (rt2x00_rt(rt2x00dev, RT3352)) {
		rt2800_bbp_write(rt2x00dev, 78, 0x0e);
		rt2800_bbp_write(rt2x00dev, 80, 0x08);
		rt2800_bbp_write(rt2x00dev, 81, 0x37);
3580 3581 3582 3583
	} else {
		rt2800_bbp_write(rt2x00dev, 81, 0x37);
	}

3584
	rt2800_bbp_write(rt2x00dev, 82, 0x62);
W
Woody Hung 已提交
3585 3586 3587
	if (rt2x00_rt(rt2x00dev, RT3290) ||
	    rt2x00_rt(rt2x00dev, RT5390) ||
	    rt2x00_rt(rt2x00dev, RT5392))
3588 3589 3590
		rt2800_bbp_write(rt2x00dev, 83, 0x7a);
	else
		rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3591

3592
	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3593
		rt2800_bbp_write(rt2x00dev, 84, 0x19);
W
Woody Hung 已提交
3594
	else if (rt2x00_rt(rt2x00dev, RT3290) ||
3595 3596
		 rt2x00_rt(rt2x00dev, RT5390) ||
		 rt2x00_rt(rt2x00dev, RT5392))
3597
		rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3598 3599 3600
	else
		rt2800_bbp_write(rt2x00dev, 84, 0x99);

W
Woody Hung 已提交
3601
	if (rt2x00_rt(rt2x00dev, RT3290) ||
3602
	    rt2x00_rt(rt2x00dev, RT3352) ||
W
Woody Hung 已提交
3603 3604
	    rt2x00_rt(rt2x00dev, RT5390) ||
	    rt2x00_rt(rt2x00dev, RT5392))
3605 3606 3607
		rt2800_bbp_write(rt2x00dev, 86, 0x38);
	else
		rt2800_bbp_write(rt2x00dev, 86, 0x00);
3608

3609 3610
	if (rt2x00_rt(rt2x00dev, RT3352) ||
	    rt2x00_rt(rt2x00dev, RT5392))
J
John Li 已提交
3611 3612
		rt2800_bbp_write(rt2x00dev, 88, 0x90);

3613
	rt2800_bbp_write(rt2x00dev, 91, 0x04);
3614

W
Woody Hung 已提交
3615
	if (rt2x00_rt(rt2x00dev, RT3290) ||
3616
	    rt2x00_rt(rt2x00dev, RT3352) ||
W
Woody Hung 已提交
3617 3618
	    rt2x00_rt(rt2x00dev, RT5390) ||
	    rt2x00_rt(rt2x00dev, RT5392))
3619 3620 3621
		rt2800_bbp_write(rt2x00dev, 92, 0x02);
	else
		rt2800_bbp_write(rt2x00dev, 92, 0x00);
3622

J
John Li 已提交
3623 3624 3625 3626 3627
	if (rt2x00_rt(rt2x00dev, RT5392)) {
		rt2800_bbp_write(rt2x00dev, 95, 0x9a);
		rt2800_bbp_write(rt2x00dev, 98, 0x12);
	}

3628
	if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3629
	    rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3630
	    rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3631
	    rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
W
Woody Hung 已提交
3632
	    rt2x00_rt(rt2x00dev, RT3290) ||
3633
	    rt2x00_rt(rt2x00dev, RT3352) ||
3634
	    rt2x00_rt(rt2x00dev, RT3572) ||
3635
	    rt2x00_rt(rt2x00dev, RT5390) ||
J
John Li 已提交
3636
	    rt2x00_rt(rt2x00dev, RT5392) ||
3637
	    rt2800_is_305x_soc(rt2x00dev))
3638 3639 3640 3641
		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
	else
		rt2800_bbp_write(rt2x00dev, 103, 0x00);

W
Woody Hung 已提交
3642
	if (rt2x00_rt(rt2x00dev, RT3290) ||
3643
	    rt2x00_rt(rt2x00dev, RT3352) ||
W
Woody Hung 已提交
3644 3645
	    rt2x00_rt(rt2x00dev, RT5390) ||
	    rt2x00_rt(rt2x00dev, RT5392))
3646
		rt2800_bbp_write(rt2x00dev, 104, 0x92);
3647

3648 3649
	if (rt2800_is_305x_soc(rt2x00dev))
		rt2800_bbp_write(rt2x00dev, 105, 0x01);
W
Woody Hung 已提交
3650 3651
	else if (rt2x00_rt(rt2x00dev, RT3290))
		rt2800_bbp_write(rt2x00dev, 105, 0x1c);
3652 3653
	else if (rt2x00_rt(rt2x00dev, RT3352))
		rt2800_bbp_write(rt2x00dev, 105, 0x34);
J
John Li 已提交
3654
	else if (rt2x00_rt(rt2x00dev, RT5390) ||
3655
		 rt2x00_rt(rt2x00dev, RT5392))
3656
		rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3657 3658
	else
		rt2800_bbp_write(rt2x00dev, 105, 0x05);
3659

W
Woody Hung 已提交
3660 3661
	if (rt2x00_rt(rt2x00dev, RT3290) ||
	    rt2x00_rt(rt2x00dev, RT5390))
3662
		rt2800_bbp_write(rt2x00dev, 106, 0x03);
3663 3664
	else if (rt2x00_rt(rt2x00dev, RT3352))
		rt2800_bbp_write(rt2x00dev, 106, 0x05);
J
John Li 已提交
3665 3666
	else if (rt2x00_rt(rt2x00dev, RT5392))
		rt2800_bbp_write(rt2x00dev, 106, 0x12);
3667 3668
	else
		rt2800_bbp_write(rt2x00dev, 106, 0x35);
3669

3670 3671 3672
	if (rt2x00_rt(rt2x00dev, RT3352))
		rt2800_bbp_write(rt2x00dev, 120, 0x50);

W
Woody Hung 已提交
3673 3674 3675
	if (rt2x00_rt(rt2x00dev, RT3290) ||
	    rt2x00_rt(rt2x00dev, RT5390) ||
	    rt2x00_rt(rt2x00dev, RT5392))
3676
		rt2800_bbp_write(rt2x00dev, 128, 0x12);
3677

J
John Li 已提交
3678 3679 3680 3681 3682
	if (rt2x00_rt(rt2x00dev, RT5392)) {
		rt2800_bbp_write(rt2x00dev, 134, 0xd0);
		rt2800_bbp_write(rt2x00dev, 135, 0xf6);
	}

3683 3684 3685
	if (rt2x00_rt(rt2x00dev, RT3352))
		rt2800_bbp_write(rt2x00dev, 137, 0x0f);

3686
	if (rt2x00_rt(rt2x00dev, RT3071) ||
3687
	    rt2x00_rt(rt2x00dev, RT3090) ||
3688
	    rt2x00_rt(rt2x00dev, RT3390) ||
3689
	    rt2x00_rt(rt2x00dev, RT3572) ||
J
John Li 已提交
3690 3691
	    rt2x00_rt(rt2x00dev, RT5390) ||
	    rt2x00_rt(rt2x00dev, RT5392)) {
3692
		rt2800_bbp_read(rt2x00dev, 138, &value);
3693

R
RA-Jay Hung 已提交
3694 3695
		rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3696
			value |= 0x20;
R
RA-Jay Hung 已提交
3697
		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3698
			value &= ~0x02;
3699

3700
		rt2800_bbp_write(rt2x00dev, 138, value);
3701 3702
	}

W
Woody Hung 已提交
3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725
	if (rt2x00_rt(rt2x00dev, RT3290)) {
		rt2800_bbp_write(rt2x00dev, 67, 0x24);
		rt2800_bbp_write(rt2x00dev, 143, 0x04);
		rt2800_bbp_write(rt2x00dev, 142, 0x99);
		rt2800_bbp_write(rt2x00dev, 150, 0x30);
		rt2800_bbp_write(rt2x00dev, 151, 0x2e);
		rt2800_bbp_write(rt2x00dev, 152, 0x20);
		rt2800_bbp_write(rt2x00dev, 153, 0x34);
		rt2800_bbp_write(rt2x00dev, 154, 0x40);
		rt2800_bbp_write(rt2x00dev, 155, 0x3b);
		rt2800_bbp_write(rt2x00dev, 253, 0x04);

		rt2800_bbp_read(rt2x00dev, 47, &value);
		rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
		rt2800_bbp_write(rt2x00dev, 47, value);

		/* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
		rt2800_bbp_read(rt2x00dev, 3, &value);
		rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
		rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
		rt2800_bbp_write(rt2x00dev, 3, value);
	}

3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747
	if (rt2x00_rt(rt2x00dev, RT3352)) {
		rt2800_bbp_write(rt2x00dev, 163, 0xbd);
		/* Set ITxBF timeout to 0x9c40=1000msec */
		rt2800_bbp_write(rt2x00dev, 179, 0x02);
		rt2800_bbp_write(rt2x00dev, 180, 0x00);
		rt2800_bbp_write(rt2x00dev, 182, 0x40);
		rt2800_bbp_write(rt2x00dev, 180, 0x01);
		rt2800_bbp_write(rt2x00dev, 182, 0x9c);
		rt2800_bbp_write(rt2x00dev, 179, 0x00);
		/* Reprogram the inband interface to put right values in RXWI */
		rt2800_bbp_write(rt2x00dev, 142, 0x04);
		rt2800_bbp_write(rt2x00dev, 143, 0x3b);
		rt2800_bbp_write(rt2x00dev, 142, 0x06);
		rt2800_bbp_write(rt2x00dev, 143, 0xa0);
		rt2800_bbp_write(rt2x00dev, 142, 0x07);
		rt2800_bbp_write(rt2x00dev, 143, 0xa1);
		rt2800_bbp_write(rt2x00dev, 142, 0x08);
		rt2800_bbp_write(rt2x00dev, 143, 0xa2);

		rt2800_bbp_write(rt2x00dev, 148, 0xc8);
	}

J
John Li 已提交
3748
	if (rt2x00_rt(rt2x00dev, RT5390) ||
3749
	    rt2x00_rt(rt2x00dev, RT5392)) {
3750 3751 3752 3753 3754 3755 3756 3757
		int ant, div_mode;

		rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
		div_mode = rt2x00_get_field16(eeprom,
					      EEPROM_NIC_CONF1_ANT_DIVERSITY);
		ant = (div_mode == 3) ? 1 : 0;

		/* check if this is a Bluetooth combo card */
3758
		if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3759 3760
			u32 reg;

3761 3762 3763 3764 3765
			rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
			rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
			rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
			rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
			rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
3766
			if (ant == 0)
3767
				rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
3768
			else if (ant == 1)
3769 3770
				rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
			rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3771 3772
		}

3773 3774 3775 3776 3777 3778 3779
		/* This chip has hardware antenna diversity*/
		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
			rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
			rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
			rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
		}

3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790
		rt2800_bbp_read(rt2x00dev, 152, &value);
		if (ant == 0)
			rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
		else
			rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
		rt2800_bbp_write(rt2x00dev, 152, value);

		/* Init frequency calibration */
		rt2800_bbp_write(rt2x00dev, 142, 1);
		rt2800_bbp_write(rt2x00dev, 143, 57);
	}
3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820

	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
		rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);

		if (eeprom != 0xffff && eeprom != 0x0000) {
			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
			rt2800_bbp_write(rt2x00dev, reg_id, value);
		}
	}

	return 0;
}

static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
				bool bw40, u8 rfcsr24, u8 filter_target)
{
	unsigned int i;
	u8 bbp;
	u8 rfcsr;
	u8 passband;
	u8 stopband;
	u8 overtuned = 0;

	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);

	rt2800_bbp_read(rt2x00dev, 4, &bbp);
	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
	rt2800_bbp_write(rt2x00dev, 4, bbp);

3821 3822 3823 3824
	rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);

3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868
	rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);

	/*
	 * Set power & frequency of passband test tone
	 */
	rt2800_bbp_write(rt2x00dev, 24, 0);

	for (i = 0; i < 100; i++) {
		rt2800_bbp_write(rt2x00dev, 25, 0x90);
		msleep(1);

		rt2800_bbp_read(rt2x00dev, 55, &passband);
		if (passband)
			break;
	}

	/*
	 * Set power & frequency of stopband test tone
	 */
	rt2800_bbp_write(rt2x00dev, 24, 0x06);

	for (i = 0; i < 100; i++) {
		rt2800_bbp_write(rt2x00dev, 25, 0x90);
		msleep(1);

		rt2800_bbp_read(rt2x00dev, 55, &stopband);

		if ((passband - stopband) <= filter_target) {
			rfcsr24++;
			overtuned += ((passband - stopband) == filter_target);
		} else
			break;

		rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
	}

	rfcsr24 -= !!overtuned;

	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
	return rfcsr24;
}

3869
static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3870
{
3871
	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3872 3873
	u8 rfcsr;
	u8 bbp;
3874 3875
	u32 reg;
	u16 eeprom;
3876

3877
	if (!rt2x00_rt(rt2x00dev, RT3070) &&
3878
	    !rt2x00_rt(rt2x00dev, RT3071) &&
3879
	    !rt2x00_rt(rt2x00dev, RT3090) &&
W
Woody Hung 已提交
3880
	    !rt2x00_rt(rt2x00dev, RT3290) &&
3881
	    !rt2x00_rt(rt2x00dev, RT3352) &&
3882
	    !rt2x00_rt(rt2x00dev, RT3390) &&
3883
	    !rt2x00_rt(rt2x00dev, RT3572) &&
3884
	    !rt2x00_rt(rt2x00dev, RT5390) &&
J
John Li 已提交
3885
	    !rt2x00_rt(rt2x00dev, RT5392) &&
3886
	    !rt2800_is_305x_soc(rt2x00dev))
3887 3888 3889 3890 3891
		return 0;

	/*
	 * Init RF calibration.
	 */
W
Woody Hung 已提交
3892 3893 3894
	if (rt2x00_rt(rt2x00dev, RT3290) ||
	    rt2x00_rt(rt2x00dev, RT5390) ||
	    rt2x00_rt(rt2x00dev, RT5392)) {
3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908
		rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
		rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
		msleep(1);
		rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
		rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
	} else {
		rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
		rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
		msleep(1);
		rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
		rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
	}
3909

3910
	if (rt2x00_rt(rt2x00dev, RT3070) ||
3911 3912
	    rt2x00_rt(rt2x00dev, RT3071) ||
	    rt2x00_rt(rt2x00dev, RT3090)) {
3913 3914 3915
		rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
		rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
		rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3916
		rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3917
		rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3918
		rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931
		rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
		rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
		rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
		rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
		rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
		rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
		rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
		rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
		rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
		rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
		rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
		rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
		rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
W
Woody Hung 已提交
3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978
	} else if (rt2x00_rt(rt2x00dev, RT3290)) {
		rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
		rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
		rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
		rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
		rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
		rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
		rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
		rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
		rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
		rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
		rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
		rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
		rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
		rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
		rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
		rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
		rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
		rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
		rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
		rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
		rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
		rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
		rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
		rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
		rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
		rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
		rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
		rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
		rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
		rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
		rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
		rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
		rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
		rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
		rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
		rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
3979 3980 3981 3982 3983
	} else if (rt2x00_rt(rt2x00dev, RT3390)) {
		rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
		rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
		rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
		rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3984
		rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3985 3986 3987 3988 3989 3990
		rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
		rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
		rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
		rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
		rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3991
		rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3992 3993
		rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
		rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3994
		rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3995 3996 3997 3998 3999 4000 4001
		rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
		rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
		rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
		rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
		rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
		rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
		rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
4002
		rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4003
		rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
4004
		rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4005 4006 4007 4008 4009 4010 4011
		rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
		rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
		rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
		rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
		rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
		rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043
	} else if (rt2x00_rt(rt2x00dev, RT3572)) {
		rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
		rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
		rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
		rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
		rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
		rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
		rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
		rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
		rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
		rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
		rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
		rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
		rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
		rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
		rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
		rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
		rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
		rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
		rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
		rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
		rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
		rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
		rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
		rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
		rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
		rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
4044
	} else if (rt2800_is_305x_soc(rt2x00dev)) {
4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074
		rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
		rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
		rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
		rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
		rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
		rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
		rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
		rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
		rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
		rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
		rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
		rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
		rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
		rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
		rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
		rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
		rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
		rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
		rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
		rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
		rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
		rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
		rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
		rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
		rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
		rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
		rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
		rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
		rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4075 4076 4077
		rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
		return 0;
4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141
	} else if (rt2x00_rt(rt2x00dev, RT3352)) {
		rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
		rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
		rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
		rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
		rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
		rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
		rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
		rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
		rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
		rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
		rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
		rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
		rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
		rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
		rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
		rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
		rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
		rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
		rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
		rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
		rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
		rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
		rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
		rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
		rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
		rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
		rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
		rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
		rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
		rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
		rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
		rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
		rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
		rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
		rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
		rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
		rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
		rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
		rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222
	} else if (rt2x00_rt(rt2x00dev, RT5390)) {
		rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
		rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
		rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
			rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
		else
			rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
		rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
		rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
		rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
		rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
		rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
		rt2800_rfcsr_write(rt2x00dev, 19, 0x00);

		rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
		rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
			rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
		else
			rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
		rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
		rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 29, 0x10);

		rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
		rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
		rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
		rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
		rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);

		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
			rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
		else
			rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
		rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
		rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
		rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
		rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
		rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
			rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
		else
			rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
		rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
		rt2800_rfcsr_write(rt2x00dev, 49, 0x94);

		rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
			rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
		else
			rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
		rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
		rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
		rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
		rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
		rt2800_rfcsr_write(rt2x00dev, 59, 0x63);

		rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
			rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
		else
			rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
		rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282
	} else if (rt2x00_rt(rt2x00dev, RT5392)) {
		rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
		rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
		rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
		rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
		rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
		rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
		rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
		rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
		rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
		rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
		rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
		rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
		rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
		rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
		rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
		rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
		rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
		rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
		rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
		rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
		rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
		rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
		rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
		rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
		rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
		rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
		rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
		rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
		rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
		rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
		rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
		rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
		rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
		rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
		rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
		rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
		rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
		rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
		rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
		rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
		rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
		rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
		rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
		rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
		rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
		rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
		rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
		rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4283 4284 4285 4286 4287 4288 4289
	}

	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
		rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
		rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4290 4291
	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
		   rt2x00_rt(rt2x00dev, RT3090)) {
4292 4293
		rt2800_rfcsr_write(rt2x00dev, 31, 0x14);

4294 4295 4296 4297 4298 4299
		rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
		rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);

		rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4300 4301
		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
R
RA-Jay Hung 已提交
4302 4303
			rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4304 4305 4306 4307 4308
				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
			else
				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
		}
		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4309 4310 4311 4312

		rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
		rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
		rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4313 4314 4315 4316
	} else if (rt2x00_rt(rt2x00dev, RT3390)) {
		rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
		rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
		rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327
	} else if (rt2x00_rt(rt2x00dev, RT3572)) {
		rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
		rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);

		rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
		rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
		msleep(1);
		rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4328
		rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4329 4330
		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4331 4332 4333 4334 4335
	}

	/*
	 * Set RX Filter calibration for 20MHz and 40MHz
	 */
4336
	if (rt2x00_rt(rt2x00dev, RT3070)) {
4337
		drv_data->calibration_bw20 =
4338
			rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4339
		drv_data->calibration_bw40 =
4340
			rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4341
	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
4342
		   rt2x00_rt(rt2x00dev, RT3090) ||
4343
		   rt2x00_rt(rt2x00dev, RT3352) ||
4344 4345
		   rt2x00_rt(rt2x00dev, RT3390) ||
		   rt2x00_rt(rt2x00dev, RT3572)) {
4346
		drv_data->calibration_bw20 =
4347
			rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4348
		drv_data->calibration_bw40 =
4349
			rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4350
	}
4351

4352 4353 4354 4355 4356 4357
	/*
	 * Save BBP 25 & 26 values for later use in channel switching
	 */
	rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
	rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);

J
John Li 已提交
4358
	if (!rt2x00_rt(rt2x00dev, RT5390) &&
4359
	    !rt2x00_rt(rt2x00dev, RT5392)) {
4360 4361 4362 4363
		/*
		 * Set back to initial state
		 */
		rt2800_bbp_write(rt2x00dev, 24, 0);
4364

4365 4366 4367
		rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
		rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4368

4369 4370 4371 4372 4373 4374 4375
		/*
		 * Set BBP back to BW20
		 */
		rt2800_bbp_read(rt2x00dev, 4, &bbp);
		rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
		rt2800_bbp_write(rt2x00dev, 4, bbp);
	}
4376

4377
	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4378
	    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4379 4380
	    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
	    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
4381 4382 4383 4384 4385 4386
		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);

	rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
	rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
	rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);

J
John Li 已提交
4387
	if (!rt2x00_rt(rt2x00dev, RT5390) &&
4388
	    !rt2x00_rt(rt2x00dev, RT5392)) {
4389 4390 4391 4392 4393 4394
		rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
		if (rt2x00_rt(rt2x00dev, RT3070) ||
		    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
		    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
I
Ivo van Doorn 已提交
4395 4396
			if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
				      &rt2x00dev->cap_flags))
4397 4398
				rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
		}
4399 4400
		rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
				  drv_data->txmixer_gain_24g);
4401 4402
		rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
	}
4403

4404 4405 4406
	if (rt2x00_rt(rt2x00dev, RT3090)) {
		rt2800_bbp_read(rt2x00dev, 138, &bbp);

4407
		/*  Turn off unused DAC1 and ADC1 to reduce power consumption */
R
RA-Jay Hung 已提交
4408 4409
		rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4410
			rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
R
RA-Jay Hung 已提交
4411
		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4412 4413 4414 4415 4416 4417
			rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);

		rt2800_bbp_write(rt2x00dev, 138, bbp);
	}

	if (rt2x00_rt(rt2x00dev, RT3071) ||
4418 4419
	    rt2x00_rt(rt2x00dev, RT3090) ||
	    rt2x00_rt(rt2x00dev, RT3390)) {
4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440
		rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
		rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);

		rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
		rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);

		rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
		rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);

		rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
		rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
	}

4441
	if (rt2x00_rt(rt2x00dev, RT3070)) {
4442
		rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4443
		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4444 4445 4446 4447 4448 4449 4450 4451 4452
			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
		else
			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
		rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
		rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
		rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
		rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
	}

W
Woody Hung 已提交
4453 4454 4455 4456 4457 4458
	if (rt2x00_rt(rt2x00dev, RT3290)) {
		rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
		rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
	}

J
John Li 已提交
4459
	if (rt2x00_rt(rt2x00dev, RT5390) ||
4460
	    rt2x00_rt(rt2x00dev, RT5392)) {
4461 4462 4463
		rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
		rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
4464

4465 4466 4467
		rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
4468

4469 4470 4471 4472
		rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
		rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
	}
4473

4474 4475
	return 0;
}
4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529

int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;
	u16 word;

	/*
	 * Initialize all registers.
	 */
	if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
		     rt2800_init_registers(rt2x00dev) ||
		     rt2800_init_bbp(rt2x00dev) ||
		     rt2800_init_rfcsr(rt2x00dev)))
		return -EIO;

	/*
	 * Send signal to firmware during boot time.
	 */
	rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);

	if (rt2x00_is_usb(rt2x00dev) &&
	    (rt2x00_rt(rt2x00dev, RT3070) ||
	     rt2x00_rt(rt2x00dev, RT3071) ||
	     rt2x00_rt(rt2x00dev, RT3572))) {
		udelay(200);
		rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
		udelay(10);
	}

	/*
	 * Enable RX.
	 */
	rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);

	udelay(50);

	rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);

	rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);

	/*
	 * Initialize LED control
	 */
R
RA-Jay Hung 已提交
4530 4531
	rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
	rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
4532 4533
			   word & 0xff, (word >> 8) & 0xff);

R
RA-Jay Hung 已提交
4534 4535
	rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
	rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
4536 4537
			   word & 0xff, (word >> 8) & 0xff);

R
RA-Jay Hung 已提交
4538 4539
	rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
	rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
4540 4541 4542 4543 4544 4545 4546 4547 4548 4549
			   word & 0xff, (word >> 8) & 0xff);

	return 0;
}
EXPORT_SYMBOL_GPL(rt2800_enable_radio);

void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;

4550
	rt2800_disable_wpdma(rt2x00dev);
4551 4552 4553 4554 4555 4556 4557 4558 4559 4560

	/* Wait for DMA, ignore error */
	rt2800_wait_wpdma_ready(rt2x00dev);

	rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
}
EXPORT_SYMBOL_GPL(rt2800_disable_radio);
4561

4562 4563 4564
int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;
W
Woody Hung 已提交
4565
	u16 efuse_ctrl_reg;
4566

W
Woody Hung 已提交
4567 4568 4569 4570
	if (rt2x00_rt(rt2x00dev, RT3290))
		efuse_ctrl_reg = EFUSE_CTRL_3290;
	else
		efuse_ctrl_reg = EFUSE_CTRL;
4571

W
Woody Hung 已提交
4572
	rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
4573 4574 4575 4576 4577 4578 4579
	return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
}
EXPORT_SYMBOL_GPL(rt2800_efuse_detect);

static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
{
	u32 reg;
W
Woody Hung 已提交
4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598
	u16 efuse_ctrl_reg;
	u16 efuse_data0_reg;
	u16 efuse_data1_reg;
	u16 efuse_data2_reg;
	u16 efuse_data3_reg;

	if (rt2x00_rt(rt2x00dev, RT3290)) {
		efuse_ctrl_reg = EFUSE_CTRL_3290;
		efuse_data0_reg = EFUSE_DATA0_3290;
		efuse_data1_reg = EFUSE_DATA1_3290;
		efuse_data2_reg = EFUSE_DATA2_3290;
		efuse_data3_reg = EFUSE_DATA3_3290;
	} else {
		efuse_ctrl_reg = EFUSE_CTRL;
		efuse_data0_reg = EFUSE_DATA0;
		efuse_data1_reg = EFUSE_DATA1;
		efuse_data2_reg = EFUSE_DATA2;
		efuse_data3_reg = EFUSE_DATA3;
	}
4599 4600
	mutex_lock(&rt2x00dev->csr_mutex);

W
Woody Hung 已提交
4601
	rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
4602 4603 4604
	rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
	rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
	rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
W
Woody Hung 已提交
4605
	rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
4606 4607

	/* Wait until the EEPROM has been loaded */
W
Woody Hung 已提交
4608
	rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
4609
	/* Apparently the data is read from end to start */
W
Woody Hung 已提交
4610
	rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
4611
	/* The returned value is in CPU order, but eeprom is le */
4612
	*(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
W
Woody Hung 已提交
4613
	rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
4614
	*(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
W
Woody Hung 已提交
4615
	rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
4616
	*(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
W
Woody Hung 已提交
4617
	rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
4618
	*(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
4619 4620

	mutex_unlock(&rt2x00dev->csr_mutex);
4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631
}

void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
{
	unsigned int i;

	for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
		rt2800_efuse_read(rt2x00dev, i);
}
EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);

4632
static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4633
{
4634
	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4635 4636 4637 4638
	u16 word;
	u8 *mac;
	u8 default_lna_gain;

4639 4640 4641 4642 4643
	/*
	 * Read the EEPROM.
	 */
	rt2800_read_eeprom(rt2x00dev);

4644 4645 4646 4647 4648
	/*
	 * Start validation of the data that has been read.
	 */
	mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
	if (!is_valid_ether_addr(mac)) {
J
Joe Perches 已提交
4649
		eth_random_addr(mac);
4650 4651 4652
		EEPROM(rt2x00dev, "MAC: %pM\n", mac);
	}

R
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4653
	rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
4654
	if (word == 0xffff) {
R
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4655 4656 4657 4658
		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4659
		EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
4660
	} else if (rt2x00_rt(rt2x00dev, RT2860) ||
4661
		   rt2x00_rt(rt2x00dev, RT2872)) {
4662 4663 4664
		/*
		 * There is a max of 2 RX streams for RT28x0 series
		 */
R
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4665 4666 4667
		if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
			rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4668 4669
	}

R
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4670
	rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
4671
	if (word == 0xffff) {
R
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4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
4688 4689 4690 4691 4692 4693
		EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
	}

	rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
	if ((word & 0x00ff) == 0x00ff) {
		rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
4694 4695 4696 4697
		rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
		EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
	}
	if ((word & 0xff00) == 0xff00) {
4698 4699 4700 4701
		rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
				   LED_MODE_TXRX_ACTIVITY);
		rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
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4702 4703 4704
		rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
4705
		EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722
	}

	/*
	 * During the LNA validation we are going to use
	 * lna0 as correct value. Note that EEPROM_LNA
	 * is never validated.
	 */
	rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
	default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);

	rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
	rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);

4723 4724 4725 4726 4727 4728 4729 4730
	rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
	if ((word & 0x00ff) != 0x00ff) {
		drv_data->txmixer_gain_24g =
			rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
	} else {
		drv_data->txmixer_gain_24g = 0;
	}

4731 4732 4733 4734 4735 4736 4737 4738 4739
	rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
		rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
	if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
	    rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
		rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
				   default_lna_gain);
	rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);

4740 4741 4742 4743 4744 4745 4746 4747
	rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
	if ((word & 0x00ff) != 0x00ff) {
		drv_data->txmixer_gain_5g =
			rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
	} else {
		drv_data->txmixer_gain_5g = 0;
	}

4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766
	rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
	rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);

	rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
		rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
	if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
	    rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
		rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
				   default_lna_gain);
	rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);

	return 0;
}

4767
static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4768 4769 4770 4771 4772 4773 4774 4775
{
	u32 reg;
	u16 value;
	u16 eeprom;

	/*
	 * Read EEPROM word for configuration.
	 */
R
RA-Jay Hung 已提交
4776
	rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4777 4778

	/*
4779 4780 4781
	 * Identify RF chipset by EEPROM value
	 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
	 * RT53xx: defined in "EEPROM_CHIP_ID" field
4782
	 */
W
Woody Hung 已提交
4783 4784 4785 4786 4787 4788 4789 4790
	if (rt2x00_rt(rt2x00dev, RT3290))
		rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
	else
		rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);

	if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
	    rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
	    rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
4791 4792 4793
		rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
	else
		value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
4794

4795 4796 4797
	rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
			value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));

4798 4799 4800 4801 4802 4803 4804
	switch (rt2x00dev->chip.rt) {
	case RT2860:
	case RT2872:
	case RT2883:
	case RT3070:
	case RT3071:
	case RT3090:
W
Woody Hung 已提交
4805
	case RT3290:
4806
	case RT3352:
4807 4808 4809
	case RT3390:
	case RT3572:
	case RT5390:
J
John Li 已提交
4810
	case RT5392:
4811 4812
		break;
	default:
4813
		ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
4814
		return -ENODEV;
4815
	}
4816

4817 4818 4819 4820 4821 4822 4823 4824 4825 4826
	switch (rt2x00dev->chip.rf) {
	case RF2820:
	case RF2850:
	case RF2720:
	case RF2750:
	case RF3020:
	case RF2020:
	case RF3021:
	case RF3022:
	case RF3052:
W
Woody Hung 已提交
4827
	case RF3290:
4828
	case RF3320:
4829
	case RF3322:
4830
	case RF5360:
4831
	case RF5370:
J
John Li 已提交
4832
	case RF5372:
4833
	case RF5390:
Z
Zero.Lin 已提交
4834
	case RF5392:
4835 4836
		break;
	default:
4837
		ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
4838
		      rt2x00dev->chip.rf);
4839 4840 4841 4842 4843 4844
		return -ENODEV;
	}

	/*
	 * Identify default antenna configuration.
	 */
4845
	rt2x00dev->default_ant.tx_chain_num =
R
RA-Jay Hung 已提交
4846
	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
4847
	rt2x00dev->default_ant.rx_chain_num =
R
RA-Jay Hung 已提交
4848
	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
4849

4850 4851 4852 4853
	rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);

	if (rt2x00_rt(rt2x00dev, RT3070) ||
	    rt2x00_rt(rt2x00dev, RT3090) ||
4854
	    rt2x00_rt(rt2x00dev, RT3352) ||
4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874
	    rt2x00_rt(rt2x00dev, RT3390)) {
		value = rt2x00_get_field16(eeprom,
				EEPROM_NIC_CONF1_ANT_DIVERSITY);
		switch (value) {
		case 0:
		case 1:
		case 2:
			rt2x00dev->default_ant.tx = ANTENNA_A;
			rt2x00dev->default_ant.rx = ANTENNA_A;
			break;
		case 3:
			rt2x00dev->default_ant.tx = ANTENNA_A;
			rt2x00dev->default_ant.rx = ANTENNA_B;
			break;
		}
	} else {
		rt2x00dev->default_ant.tx = ANTENNA_A;
		rt2x00dev->default_ant.rx = ANTENNA_A;
	}

4875 4876 4877 4878 4879
	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
		rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
		rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
	}

4880
	/*
4881
	 * Determine external LNA informations.
4882
	 */
R
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4883
	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
I
Ivo van Doorn 已提交
4884
		__set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
R
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4885
	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
I
Ivo van Doorn 已提交
4886
		__set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4887 4888 4889 4890

	/*
	 * Detect if this device has an hardware controlled radio.
	 */
R
RA-Jay Hung 已提交
4891
	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
I
Ivo van Doorn 已提交
4892
		__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4893

4894 4895 4896 4897 4898 4899
	/*
	 * Detect if this device has Bluetooth co-existence.
	 */
	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
		__set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);

4900 4901 4902 4903 4904 4905
	/*
	 * Read frequency offset and RF programming sequence.
	 */
	rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
	rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);

4906 4907 4908 4909 4910 4911 4912 4913
	/*
	 * Store led settings, for correct led behaviour.
	 */
#ifdef CONFIG_RT2X00_LIB_LEDS
	rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
	rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
	rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);

4914
	rt2x00dev->led_mcu_reg = eeprom;
4915 4916
#endif /* CONFIG_RT2X00_LIB_LEDS */

4917 4918 4919 4920 4921 4922 4923
	/*
	 * Check if support EIRP tx power limit feature.
	 */
	rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);

	if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
					EIRP_MAX_TX_POWER_LIMIT)
I
Ivo van Doorn 已提交
4924
		__set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4925

4926 4927 4928
	return 0;
}

4929
/*
4930
 * RF value list for rt28xx
4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004
 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
 */
static const struct rf_channel rf_vals[] = {
	{ 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
	{ 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
	{ 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
	{ 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
	{ 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
	{ 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
	{ 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
	{ 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
	{ 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
	{ 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
	{ 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
	{ 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
	{ 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
	{ 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },

	/* 802.11 UNI / HyperLan 2 */
	{ 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
	{ 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
	{ 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
	{ 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
	{ 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
	{ 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
	{ 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
	{ 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
	{ 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
	{ 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
	{ 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
	{ 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },

	/* 802.11 HyperLan 2 */
	{ 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
	{ 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
	{ 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
	{ 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
	{ 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
	{ 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
	{ 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
	{ 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
	{ 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
	{ 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
	{ 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
	{ 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
	{ 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
	{ 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
	{ 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
	{ 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },

	/* 802.11 UNII */
	{ 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
	{ 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
	{ 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
	{ 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
	{ 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
	{ 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
	{ 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
	{ 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
	{ 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
	{ 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
	{ 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },

	/* 802.11 Japan */
	{ 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
	{ 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
	{ 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
	{ 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
	{ 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
	{ 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
	{ 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
};

/*
5005 5006
 * RF value list for rt3xxx
 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
5007
 */
5008
static const struct rf_channel rf_vals_3x[] = {
5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022
	{1,  241, 2, 2 },
	{2,  241, 2, 7 },
	{3,  242, 2, 2 },
	{4,  242, 2, 7 },
	{5,  243, 2, 2 },
	{6,  243, 2, 7 },
	{7,  244, 2, 2 },
	{8,  244, 2, 7 },
	{9,  245, 2, 2 },
	{10, 245, 2, 7 },
	{11, 246, 2, 2 },
	{12, 246, 2, 7 },
	{13, 247, 2, 2 },
	{14, 248, 2, 4 },
5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067

	/* 802.11 UNI / HyperLan 2 */
	{36, 0x56, 0, 4},
	{38, 0x56, 0, 6},
	{40, 0x56, 0, 8},
	{44, 0x57, 0, 0},
	{46, 0x57, 0, 2},
	{48, 0x57, 0, 4},
	{52, 0x57, 0, 8},
	{54, 0x57, 0, 10},
	{56, 0x58, 0, 0},
	{60, 0x58, 0, 4},
	{62, 0x58, 0, 6},
	{64, 0x58, 0, 8},

	/* 802.11 HyperLan 2 */
	{100, 0x5b, 0, 8},
	{102, 0x5b, 0, 10},
	{104, 0x5c, 0, 0},
	{108, 0x5c, 0, 4},
	{110, 0x5c, 0, 6},
	{112, 0x5c, 0, 8},
	{116, 0x5d, 0, 0},
	{118, 0x5d, 0, 2},
	{120, 0x5d, 0, 4},
	{124, 0x5d, 0, 8},
	{126, 0x5d, 0, 10},
	{128, 0x5e, 0, 0},
	{132, 0x5e, 0, 4},
	{134, 0x5e, 0, 6},
	{136, 0x5e, 0, 8},
	{140, 0x5f, 0, 0},

	/* 802.11 UNII */
	{149, 0x5f, 0, 9},
	{151, 0x5f, 0, 11},
	{153, 0x60, 0, 1},
	{157, 0x60, 0, 5},
	{159, 0x60, 0, 7},
	{161, 0x60, 0, 9},
	{165, 0x61, 0, 1},
	{167, 0x61, 0, 3},
	{169, 0x61, 0, 5},
	{171, 0x61, 0, 7},
	{173, 0x61, 0, 9},
5068 5069
};

5070
static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5071 5072 5073
{
	struct hw_mode_spec *spec = &rt2x00dev->spec;
	struct channel_info *info;
5074 5075
	char *default_power1;
	char *default_power2;
5076 5077 5078
	unsigned int i;
	u16 eeprom;

5079 5080 5081
	/*
	 * Disable powersaving as default on PCI devices.
	 */
5082
	if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
5083 5084
		rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;

5085 5086 5087 5088 5089 5090
	/*
	 * Initialize all hw fields.
	 */
	rt2x00dev->hw->flags =
	    IEEE80211_HW_SIGNAL_DBM |
	    IEEE80211_HW_SUPPORTS_PS |
5091
	    IEEE80211_HW_PS_NULLFUNC_STACK |
5092 5093 5094
	    IEEE80211_HW_AMPDU_AGGREGATION |
	    IEEE80211_HW_REPORTS_TX_ACK_STATUS;

5095 5096 5097 5098 5099 5100 5101 5102 5103 5104
	/*
	 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
	 * unless we are capable of sending the buffered frames out after the
	 * DTIM transmission using rt2x00lib_beacondone. This will send out
	 * multicast and broadcast traffic immediately instead of buffering it
	 * infinitly and thus dropping it after some time.
	 */
	if (!rt2x00_is_usb(rt2x00dev))
		rt2x00dev->hw->flags |=
			IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
5105 5106 5107 5108 5109 5110

	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
				rt2x00_eeprom_addr(rt2x00dev,
						   EEPROM_MAC_ADDR_0));

5111 5112 5113 5114
	/*
	 * As rt2800 has a global fallback table we cannot specify
	 * more then one tx rate per frame but since the hw will
	 * try several rates (based on the fallback table) we should
5115
	 * initialize max_report_rates to the maximum number of rates
5116 5117 5118 5119
	 * we are going to try. Otherwise mac80211 will truncate our
	 * reported tx rates and the rc algortihm will end up with
	 * incorrect data.
	 */
5120 5121
	rt2x00dev->hw->max_rates = 1;
	rt2x00dev->hw->max_report_rates = 7;
5122 5123
	rt2x00dev->hw->max_rate_tries = 1;

R
RA-Jay Hung 已提交
5124
	rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5125 5126 5127 5128 5129 5130 5131

	/*
	 * Initialize hw_mode information.
	 */
	spec->supported_bands = SUPPORT_BAND_2GHZ;
	spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;

5132
	if (rt2x00_rf(rt2x00dev, RF2820) ||
5133
	    rt2x00_rf(rt2x00dev, RF2720)) {
5134 5135
		spec->num_channels = 14;
		spec->channels = rf_vals;
5136 5137
	} else if (rt2x00_rf(rt2x00dev, RF2850) ||
		   rt2x00_rf(rt2x00dev, RF2750)) {
5138 5139 5140
		spec->supported_bands |= SUPPORT_BAND_5GHZ;
		spec->num_channels = ARRAY_SIZE(rf_vals);
		spec->channels = rf_vals;
5141 5142 5143
	} else if (rt2x00_rf(rt2x00dev, RF3020) ||
		   rt2x00_rf(rt2x00dev, RF2020) ||
		   rt2x00_rf(rt2x00dev, RF3021) ||
5144
		   rt2x00_rf(rt2x00dev, RF3022) ||
W
Woody Hung 已提交
5145
		   rt2x00_rf(rt2x00dev, RF3290) ||
5146
		   rt2x00_rf(rt2x00dev, RF3320) ||
5147
		   rt2x00_rf(rt2x00dev, RF3322) ||
5148
		   rt2x00_rf(rt2x00dev, RF5360) ||
5149
		   rt2x00_rf(rt2x00dev, RF5370) ||
J
John Li 已提交
5150
		   rt2x00_rf(rt2x00dev, RF5372) ||
Z
Zero.Lin 已提交
5151 5152
		   rt2x00_rf(rt2x00dev, RF5390) ||
		   rt2x00_rf(rt2x00dev, RF5392)) {
5153 5154 5155 5156 5157 5158
		spec->num_channels = 14;
		spec->channels = rf_vals_3x;
	} else if (rt2x00_rf(rt2x00dev, RF3052)) {
		spec->supported_bands |= SUPPORT_BAND_5GHZ;
		spec->num_channels = ARRAY_SIZE(rf_vals_3x);
		spec->channels = rf_vals_3x;
5159 5160 5161 5162 5163
	}

	/*
	 * Initialize HT information.
	 */
5164
	if (!rt2x00_rf(rt2x00dev, RF2020))
5165 5166 5167 5168
		spec->ht.ht_supported = true;
	else
		spec->ht.ht_supported = false;

5169
	spec->ht.cap =
5170
	    IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
5171 5172
	    IEEE80211_HT_CAP_GRN_FLD |
	    IEEE80211_HT_CAP_SGI_20 |
5173
	    IEEE80211_HT_CAP_SGI_40;
5174

R
RA-Jay Hung 已提交
5175
	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
5176 5177
		spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;

5178
	spec->ht.cap |=
R
RA-Jay Hung 已提交
5179
	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
5180 5181
		IEEE80211_HT_CAP_RX_STBC_SHIFT;

5182 5183 5184 5185 5186
	spec->ht.ampdu_factor = 3;
	spec->ht.ampdu_density = 4;
	spec->ht.mcs.tx_params =
	    IEEE80211_HT_MCS_TX_DEFINED |
	    IEEE80211_HT_MCS_TX_RX_DIFF |
R
RA-Jay Hung 已提交
5187
	    ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
5188 5189
		IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);

R
RA-Jay Hung 已提交
5190
	switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203
	case 3:
		spec->ht.mcs.rx_mask[2] = 0xff;
	case 2:
		spec->ht.mcs.rx_mask[1] = 0xff;
	case 1:
		spec->ht.mcs.rx_mask[0] = 0xff;
		spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
		break;
	}

	/*
	 * Create channel information array
	 */
5204
	info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
5205 5206 5207 5208 5209
	if (!info)
		return -ENOMEM;

	spec->channels_info = info;

5210 5211
	default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
	default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
5212 5213

	for (i = 0; i < 14; i++) {
5214 5215
		info[i].default_power1 = default_power1[i];
		info[i].default_power2 = default_power2[i];
5216 5217 5218
	}

	if (spec->num_channels > 14) {
5219 5220
		default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
		default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
5221 5222

		for (i = 14; i < spec->num_channels; i++) {
5223 5224
			info[i].default_power1 = default_power1[i];
			info[i].default_power2 = default_power2[i];
5225 5226 5227
		}
	}

J
John Li 已提交
5228 5229 5230 5231 5232 5233 5234
	switch (rt2x00dev->chip.rf) {
	case RF2020:
	case RF3020:
	case RF3021:
	case RF3022:
	case RF3320:
	case RF3052:
W
Woody Hung 已提交
5235
	case RF3290:
5236
	case RF5360:
J
John Li 已提交
5237 5238 5239
	case RF5370:
	case RF5372:
	case RF5390:
Z
Zero.Lin 已提交
5240
	case RF5392:
J
John Li 已提交
5241 5242 5243 5244
		__set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
		break;
	}

5245 5246
	return 0;
}
5247 5248 5249 5250 5251 5252 5253 5254 5255 5256 5257 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273 5274 5275 5276 5277 5278 5279 5280 5281 5282 5283 5284 5285 5286 5287 5288 5289 5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312

int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
{
	int retval;
	u32 reg;

	/*
	 * Allocate eeprom data.
	 */
	retval = rt2800_validate_eeprom(rt2x00dev);
	if (retval)
		return retval;

	retval = rt2800_init_eeprom(rt2x00dev);
	if (retval)
		return retval;

	/*
	 * Enable rfkill polling by setting GPIO direction of the
	 * rfkill switch GPIO pin correctly.
	 */
	rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
	rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);

	/*
	 * Initialize hw specifications.
	 */
	retval = rt2800_probe_hw_mode(rt2x00dev);
	if (retval)
		return retval;

	/*
	 * Set device capabilities.
	 */
	__set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
	__set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
	if (!rt2x00_is_usb(rt2x00dev))
		__set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);

	/*
	 * Set device requirements.
	 */
	if (!rt2x00_is_soc(rt2x00dev))
		__set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
	__set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
	__set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
	if (!rt2800_hwcrypt_disabled(rt2x00dev))
		__set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
	__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
	__set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
	if (rt2x00_is_usb(rt2x00dev))
		__set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
	else {
		__set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
		__set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
	}

	/*
	 * Set the rssi offset.
	 */
	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;

	return 0;
}
EXPORT_SYMBOL_GPL(rt2800_probe_hw);
5313

5314 5315 5316
/*
 * IEEE80211 stack callback functions.
 */
5317 5318
void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
			 u16 *iv16)
5319 5320 5321 5322 5323 5324 5325 5326 5327
{
	struct rt2x00_dev *rt2x00dev = hw->priv;
	struct mac_iveiv_entry iveiv_entry;
	u32 offset;

	offset = MAC_IVEIV_ENTRY(hw_key_idx);
	rt2800_register_multiread(rt2x00dev, offset,
				      &iveiv_entry, sizeof(iveiv_entry));

5328 5329
	memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
	memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
5330
}
5331
EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
5332

5333
int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368
{
	struct rt2x00_dev *rt2x00dev = hw->priv;
	u32 reg;
	bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);

	rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);

	rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);

	rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);

	return 0;
}
5369
EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
5370

5371 5372
int rt2800_conf_tx(struct ieee80211_hw *hw,
		   struct ieee80211_vif *vif, u16 queue_idx,
5373
		   const struct ieee80211_tx_queue_params *params)
5374 5375 5376 5377 5378 5379 5380 5381 5382 5383 5384 5385 5386 5387
{
	struct rt2x00_dev *rt2x00dev = hw->priv;
	struct data_queue *queue;
	struct rt2x00_field32 field;
	int retval;
	u32 reg;
	u32 offset;

	/*
	 * First pass the configuration through rt2x00lib, that will
	 * update the queue settings and validate the input. After that
	 * we are free to update the registers based on the value
	 * in the queue parameter.
	 */
5388
	retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
5389 5390 5391 5392 5393 5394 5395 5396 5397 5398
	if (retval)
		return retval;

	/*
	 * We only need to perform additional register initialization
	 * for WMM queues/
	 */
	if (queue_idx >= 4)
		return 0;

5399
	queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414 5415 5416 5417 5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435 5436 5437

	/* Update WMM TXOP register */
	offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
	field.bit_offset = (queue_idx & 1) * 16;
	field.bit_mask = 0xffff << field.bit_offset;

	rt2800_register_read(rt2x00dev, offset, &reg);
	rt2x00_set_field32(&reg, field, queue->txop);
	rt2800_register_write(rt2x00dev, offset, reg);

	/* Update WMM registers */
	field.bit_offset = queue_idx * 4;
	field.bit_mask = 0xf << field.bit_offset;

	rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
	rt2x00_set_field32(&reg, field, queue->aifs);
	rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);

	rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
	rt2x00_set_field32(&reg, field, queue->cw_min);
	rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);

	rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
	rt2x00_set_field32(&reg, field, queue->cw_max);
	rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);

	/* Update EDCA registers */
	offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);

	rt2800_register_read(rt2x00dev, offset, &reg);
	rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
	rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
	rt2800_register_write(rt2x00dev, offset, reg);

	return 0;
}
5438
EXPORT_SYMBOL_GPL(rt2800_conf_tx);
5439

5440
u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
5441 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452
{
	struct rt2x00_dev *rt2x00dev = hw->priv;
	u64 tsf;
	u32 reg;

	rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
	tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
	rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
	tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);

	return tsf;
}
5453
EXPORT_SYMBOL_GPL(rt2800_get_tsf);
5454

5455 5456
int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
			enum ieee80211_ampdu_mlme_action action,
5457 5458
			struct ieee80211_sta *sta, u16 tid, u16 *ssn,
			u8 buf_size)
5459
{
5460
	struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
5461 5462
	int ret = 0;

5463 5464 5465 5466 5467 5468 5469 5470 5471 5472
	/*
	 * Don't allow aggregation for stations the hardware isn't aware
	 * of because tx status reports for frames to an unknown station
	 * always contain wcid=255 and thus we can't distinguish between
	 * multiple stations which leads to unwanted situations when the
	 * hw reorders frames due to aggregation.
	 */
	if (sta_priv->wcid < 0)
		return 1;

5473 5474 5475
	switch (action) {
	case IEEE80211_AMPDU_RX_START:
	case IEEE80211_AMPDU_RX_STOP:
5476 5477 5478 5479 5480 5481
		/*
		 * The hw itself takes care of setting up BlockAck mechanisms.
		 * So, we only have to allow mac80211 to nagotiate a BlockAck
		 * agreement. Once that is done, the hw will BlockAck incoming
		 * AMPDUs without further setup.
		 */
5482 5483 5484 5485 5486 5487 5488 5489 5490 5491
		break;
	case IEEE80211_AMPDU_TX_START:
		ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
		break;
	case IEEE80211_AMPDU_TX_STOP:
		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
		break;
	case IEEE80211_AMPDU_TX_OPERATIONAL:
		break;
	default:
5492
		WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
5493 5494 5495 5496
	}

	return ret;
}
5497
EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
I
Ivo van Doorn 已提交
5498

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int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
		      struct survey_info *survey)
{
	struct rt2x00_dev *rt2x00dev = hw->priv;
	struct ieee80211_conf *conf = &hw->conf;
	u32 idle, busy, busy_ext;

	if (idx != 0)
		return -ENOENT;

	survey->channel = conf->channel;

	rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
	rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
	rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);

	if (idle || busy) {
		survey->filled = SURVEY_INFO_CHANNEL_TIME |
				 SURVEY_INFO_CHANNEL_TIME_BUSY |
				 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;

		survey->channel_time = (idle + busy) / 1000;
		survey->channel_time_busy = busy / 1000;
		survey->channel_time_ext_busy = busy_ext / 1000;
	}

5525 5526 5527
	if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
		survey->filled |= SURVEY_INFO_IN_USE;

5528 5529 5530 5531 5532
	return 0;

}
EXPORT_SYMBOL_GPL(rt2800_get_survey);

I
Ivo van Doorn 已提交
5533 5534 5535 5536
MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("Ralink RT2800 library");
MODULE_LICENSE("GPL");