“2f324b42b7b24a48fe3f8a7af60ec3c9024255fa”上不存在“git@gitcode.net:openeuler/kernel.git”
sh_tmu.c 15.0 KB
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/*
 * SuperH Timer Support - TMU
 *
 *  Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

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#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/delay.h>
#include <linux/err.h>
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#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
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#include <linux/ioport.h>
25
#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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#include <linux/sh_timer.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
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enum sh_tmu_model {
	SH_TMU,
	SH_TMU_SH3,
};

40
struct sh_tmu_device;
41 42

struct sh_tmu_channel {
43
	struct sh_tmu_device *tmu;
44
	unsigned int index;
45

46
	void __iomem *base;
47
	int irq;
48

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	unsigned long rate;
	unsigned long periodic;
	struct clock_event_device ced;
	struct clocksource cs;
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	bool cs_enabled;
54
	unsigned int enable_count;
55 56
};

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struct sh_tmu_device {
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	struct platform_device *pdev;

	void __iomem *mapbase;
	struct clk *clk;

63 64
	enum sh_tmu_model model;

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	raw_spinlock_t lock; /* Protect the shared start/stop register */

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	struct sh_tmu_channel *channels;
	unsigned int num_channels;
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	bool has_clockevent;
	bool has_clocksource;
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};

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#define TSTR -1 /* shared register */
#define TCOR  0 /* channel register */
#define TCNT 1 /* channel register */
#define TCR 2 /* channel register */

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#define TCR_UNF			(1 << 8)
#define TCR_UNIE		(1 << 5)
#define TCR_TPSC_CLK4		(0 << 0)
#define TCR_TPSC_CLK16		(1 << 0)
#define TCR_TPSC_CLK64		(2 << 0)
#define TCR_TPSC_CLK256		(3 << 0)
#define TCR_TPSC_CLK1024	(4 << 0)
#define TCR_TPSC_MASK		(7 << 0)

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static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
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{
	unsigned long offs;

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	if (reg_nr == TSTR) {
		switch (ch->tmu->model) {
		case SH_TMU_SH3:
			return ioread8(ch->tmu->mapbase + 2);
		case SH_TMU:
			return ioread8(ch->tmu->mapbase + 4);
		}
	}
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	offs = reg_nr << 2;

	if (reg_nr == TCR)
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		return ioread16(ch->base + offs);
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	else
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		return ioread32(ch->base + offs);
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}

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static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
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				unsigned long value)
{
	unsigned long offs;

	if (reg_nr == TSTR) {
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		switch (ch->tmu->model) {
		case SH_TMU_SH3:
			return iowrite8(value, ch->tmu->mapbase + 2);
		case SH_TMU:
			return iowrite8(value, ch->tmu->mapbase + 4);
		}
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	}

	offs = reg_nr << 2;

	if (reg_nr == TCR)
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		iowrite16(value, ch->base + offs);
127
	else
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		iowrite32(value, ch->base + offs);
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}

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static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
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{
	unsigned long flags, value;

	/* start stop register shared by multiple timer channels */
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	raw_spin_lock_irqsave(&ch->tmu->lock, flags);
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	value = sh_tmu_read(ch, TSTR);
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	if (start)
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		value |= 1 << ch->index;
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	else
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		value &= ~(1 << ch->index);
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	sh_tmu_write(ch, TSTR, value);
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	raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);
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}

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static int __sh_tmu_enable(struct sh_tmu_channel *ch)
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{
	int ret;

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	/* enable clock */
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	ret = clk_enable(ch->tmu->clk);
154
	if (ret) {
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		dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
			ch->index);
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		return ret;
	}

	/* make sure channel is disabled */
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	sh_tmu_start_stop_ch(ch, 0);
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	/* maximum timeout */
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	sh_tmu_write(ch, TCOR, 0xffffffff);
	sh_tmu_write(ch, TCNT, 0xffffffff);
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	/* configure channel to parent clock / 4, irq off */
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	ch->rate = clk_get_rate(ch->tmu->clk) / 4;
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	sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
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	/* enable channel */
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	sh_tmu_start_stop_ch(ch, 1);
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	return 0;
}

177
static int sh_tmu_enable(struct sh_tmu_channel *ch)
178
{
179
	if (ch->enable_count++ > 0)
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		return 0;

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	pm_runtime_get_sync(&ch->tmu->pdev->dev);
	dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
184

185
	return __sh_tmu_enable(ch);
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}

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static void __sh_tmu_disable(struct sh_tmu_channel *ch)
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{
	/* disable channel */
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	sh_tmu_start_stop_ch(ch, 0);
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193
	/* disable interrupts in TMU block */
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	sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
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196
	/* stop clock */
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	clk_disable(ch->tmu->clk);
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}

200
static void sh_tmu_disable(struct sh_tmu_channel *ch)
201
{
202
	if (WARN_ON(ch->enable_count == 0))
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		return;

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	if (--ch->enable_count > 0)
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		return;

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	__sh_tmu_disable(ch);
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	dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
	pm_runtime_put(&ch->tmu->pdev->dev);
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}

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static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
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			    int periodic)
{
	/* stop timer */
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	sh_tmu_start_stop_ch(ch, 0);
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	/* acknowledge interrupt */
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	sh_tmu_read(ch, TCR);
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	/* enable interrupt */
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	sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
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	/* reload delta value in case of periodic timer */
	if (periodic)
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		sh_tmu_write(ch, TCOR, delta);
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	else
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		sh_tmu_write(ch, TCOR, 0xffffffff);
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	sh_tmu_write(ch, TCNT, delta);
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	/* start timer */
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	sh_tmu_start_stop_ch(ch, 1);
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}

static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
{
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	struct sh_tmu_channel *ch = dev_id;
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	/* disable or acknowledge interrupt */
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	if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
244
		sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
245
	else
246
		sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
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	/* notify clockevent layer */
249
	ch->ced.event_handler(&ch->ced);
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	return IRQ_HANDLED;
}

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static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
254
{
255
	return container_of(cs, struct sh_tmu_channel, cs);
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}

static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
{
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	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
261

262
	return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
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}

static int sh_tmu_clocksource_enable(struct clocksource *cs)
{
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	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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	int ret;
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270
	if (WARN_ON(ch->cs_enabled))
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		return 0;

273
	ret = sh_tmu_enable(ch);
274
	if (!ret) {
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		__clocksource_updatefreq_hz(cs, ch->rate);
		ch->cs_enabled = true;
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	}
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	return ret;
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}

static void sh_tmu_clocksource_disable(struct clocksource *cs)
{
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	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
285

286
	if (WARN_ON(!ch->cs_enabled))
287
		return;
288

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	sh_tmu_disable(ch);
	ch->cs_enabled = false;
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}

static void sh_tmu_clocksource_suspend(struct clocksource *cs)
{
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	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
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297
	if (!ch->cs_enabled)
298
		return;
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	if (--ch->enable_count == 0) {
		__sh_tmu_disable(ch);
		pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
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	}
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}

static void sh_tmu_clocksource_resume(struct clocksource *cs)
{
308
	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
309

310
	if (!ch->cs_enabled)
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		return;

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	if (ch->enable_count++ == 0) {
		pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
		__sh_tmu_enable(ch);
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	}
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}

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static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
320
				       const char *name)
321
{
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	struct clocksource *cs = &ch->cs;
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	cs->name = name;
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	cs->rating = 200;
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	cs->read = sh_tmu_clocksource_read;
	cs->enable = sh_tmu_clocksource_enable;
	cs->disable = sh_tmu_clocksource_disable;
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	cs->suspend = sh_tmu_clocksource_suspend;
	cs->resume = sh_tmu_clocksource_resume;
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	cs->mask = CLOCKSOURCE_MASK(32);
	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
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	dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
		 ch->index);
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	/* Register with dummy 1 Hz value, gets updated in ->enable() */
	clocksource_register_hz(cs, 1);
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	return 0;
}

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static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
343
{
344
	return container_of(ced, struct sh_tmu_channel, ced);
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}

347
static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
348
{
349
	struct clock_event_device *ced = &ch->ced;
350

351
	sh_tmu_enable(ch);
352

353
	clockevents_config(ced, ch->rate);
354 355

	if (periodic) {
356 357
		ch->periodic = (ch->rate + HZ/2) / HZ;
		sh_tmu_set_next(ch, ch->periodic, 1);
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	}
}

static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
				    struct clock_event_device *ced)
{
364
	struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
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	int disabled = 0;

	/* deal with old setting first */
	switch (ced->mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
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		sh_tmu_disable(ch);
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		disabled = 1;
		break;
	default:
		break;
	}

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
380
		dev_info(&ch->tmu->pdev->dev,
381
			 "ch%u: used for periodic clock events\n", ch->index);
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		sh_tmu_clock_event_start(ch, 1);
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		break;
	case CLOCK_EVT_MODE_ONESHOT:
385
		dev_info(&ch->tmu->pdev->dev,
386
			 "ch%u: used for oneshot clock events\n", ch->index);
387
		sh_tmu_clock_event_start(ch, 0);
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		break;
	case CLOCK_EVT_MODE_UNUSED:
		if (!disabled)
391
			sh_tmu_disable(ch);
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		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		break;
	}
}

static int sh_tmu_clock_event_next(unsigned long delta,
				   struct clock_event_device *ced)
{
402
	struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
403 404 405 406

	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);

	/* program new delta value */
407
	sh_tmu_set_next(ch, delta, 0);
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	return 0;
}

411 412
static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
{
413
	pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
414 415 416 417
}

static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
{
418
	pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
419 420
}

421
static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
422
				       const char *name)
423
{
424
	struct clock_event_device *ced = &ch->ced;
425 426 427 428 429
	int ret;

	ced->name = name;
	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	ced->features |= CLOCK_EVT_FEAT_ONESHOT;
430
	ced->rating = 200;
431 432 433
	ced->cpumask = cpumask_of(0);
	ced->set_next_event = sh_tmu_clock_event_next;
	ced->set_mode = sh_tmu_clock_event_mode;
434 435
	ced->suspend = sh_tmu_clock_event_suspend;
	ced->resume = sh_tmu_clock_event_resume;
436

437 438
	dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
		 ch->index);
439 440

	clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
441

442
	ret = request_irq(ch->irq, sh_tmu_interrupt,
443
			  IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
444
			  dev_name(&ch->tmu->pdev->dev), ch);
445
	if (ret) {
446 447
		dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
			ch->index, ch->irq);
448 449 450 451
		return;
	}
}

452
static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
453
			   bool clockevent, bool clocksource)
454
{
455 456
	if (clockevent) {
		ch->tmu->has_clockevent = true;
457
		sh_tmu_register_clockevent(ch, name);
458 459
	} else if (clocksource) {
		ch->tmu->has_clocksource = true;
460
		sh_tmu_register_clocksource(ch, name);
461
	}
462 463 464 465

	return 0;
}

466 467
static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
				bool clockevent, bool clocksource,
468 469
				struct sh_tmu_device *tmu)
{
470 471 472
	/* Skip unused channels. */
	if (!clockevent && !clocksource)
		return 0;
473 474

	ch->tmu = tmu;
475
	ch->index = index;
476

477 478 479 480
	if (tmu->model == SH_TMU_SH3)
		ch->base = tmu->mapbase + 4 + ch->index * 12;
	else
		ch->base = tmu->mapbase + 8 + ch->index * 12;
481

482
	ch->irq = platform_get_irq(tmu->pdev, index);
483
	if (ch->irq < 0) {
484 485
		dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
			ch->index);
486 487 488 489 490 491
		return ch->irq;
	}

	ch->cs_enabled = false;
	ch->enable_count = 0;

492
	return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
493
			       clockevent, clocksource);
494 495
}

496
static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
497 498 499
{
	struct resource *res;

500
	res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
501
	if (!res) {
502
		dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
503
		return -ENXIO;
504 505
	}

506 507 508 509 510 511
	tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
	if (tmu->mapbase == NULL)
		return -ENXIO;

	return 0;
}
512

513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530
static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
{
	struct device_node *np = tmu->pdev->dev.of_node;

	tmu->model = SH_TMU;
	tmu->num_channels = 3;

	of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);

	if (tmu->num_channels != 2 && tmu->num_channels != 3) {
		dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
			tmu->num_channels);
		return -EINVAL;
	}

	return 0;
}

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static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
{
	unsigned int i;
	int ret;

	tmu->pdev = pdev;

538 539
	raw_spin_lock_init(&tmu->lock);

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	if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
		ret = sh_tmu_parse_dt(tmu);
		if (ret < 0)
			return ret;
	} else if (pdev->dev.platform_data) {
		const struct platform_device_id *id = pdev->id_entry;
		struct sh_timer_config *cfg = pdev->dev.platform_data;

		tmu->model = id->driver_data;
		tmu->num_channels = hweight8(cfg->channels_mask);
	} else {
		dev_err(&tmu->pdev->dev, "missing platform data\n");
		return -ENXIO;
	}

555
	/* Get hold of clock. */
556
	tmu->clk = clk_get(&tmu->pdev->dev, "fck");
557 558
	if (IS_ERR(tmu->clk)) {
		dev_err(&tmu->pdev->dev, "cannot get clock\n");
559
		return PTR_ERR(tmu->clk);
560
	}
561

562
	ret = clk_prepare(tmu->clk);
563
	if (ret < 0)
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		goto err_clk_put;

	/* Map the memory resource. */
	ret = sh_tmu_map_memory(tmu);
	if (ret < 0) {
		dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
		goto err_clk_unprepare;
	}
572

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	/* Allocate and setup the channels. */
	tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels,
				GFP_KERNEL);
576 577
	if (tmu->channels == NULL) {
		ret = -ENOMEM;
578
		goto err_unmap;
579 580
	}

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	/*
	 * Use the first channel as a clock event device and the second channel
	 * as a clock source.
	 */
	for (i = 0; i < tmu->num_channels; ++i) {
		ret = sh_tmu_channel_setup(&tmu->channels[i], i,
					   i == 0, i == 1, tmu);
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		if (ret < 0)
			goto err_unmap;
	}
591

592
	platform_set_drvdata(pdev, tmu);
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	return 0;

596
err_unmap:
597
	kfree(tmu->channels);
598
	iounmap(tmu->mapbase);
599
err_clk_unprepare:
600
	clk_unprepare(tmu->clk);
601
err_clk_put:
602
	clk_put(tmu->clk);
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	return ret;
}

606
static int sh_tmu_probe(struct platform_device *pdev)
607
{
608
	struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
609 610
	int ret;

611
	if (!is_early_platform_device(pdev)) {
612 613
		pm_runtime_set_active(&pdev->dev);
		pm_runtime_enable(&pdev->dev);
614
	}
615

616
	if (tmu) {
617
		dev_info(&pdev->dev, "kept as earlytimer\n");
618
		goto out;
619 620
	}

621
	tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
622
	if (tmu == NULL)
623 624
		return -ENOMEM;

625
	ret = sh_tmu_setup(tmu, pdev);
626
	if (ret) {
627
		kfree(tmu);
628 629
		pm_runtime_idle(&pdev->dev);
		return ret;
630
	}
631 632 633 634
	if (is_early_platform_device(pdev))
		return 0;

 out:
635
	if (tmu->has_clockevent || tmu->has_clocksource)
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		pm_runtime_irq_safe(&pdev->dev);
	else
		pm_runtime_idle(&pdev->dev);

	return 0;
641 642
}

643
static int sh_tmu_remove(struct platform_device *pdev)
644 645 646 647
{
	return -EBUSY; /* cannot unregister clockevent and clocksource */
}

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static const struct platform_device_id sh_tmu_id_table[] = {
	{ "sh-tmu", SH_TMU },
	{ "sh-tmu-sh3", SH_TMU_SH3 },
	{ }
};
MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);

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static const struct of_device_id sh_tmu_of_table[] __maybe_unused = {
	{ .compatible = "renesas,tmu" },
	{ }
};
MODULE_DEVICE_TABLE(of, sh_tmu_of_table);

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static struct platform_driver sh_tmu_device_driver = {
	.probe		= sh_tmu_probe,
663
	.remove		= sh_tmu_remove,
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	.driver		= {
		.name	= "sh_tmu",
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		.of_match_table = of_match_ptr(sh_tmu_of_table),
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	},
	.id_table	= sh_tmu_id_table,
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};

static int __init sh_tmu_init(void)
{
	return platform_driver_register(&sh_tmu_device_driver);
}

static void __exit sh_tmu_exit(void)
{
	platform_driver_unregister(&sh_tmu_device_driver);
}

early_platform_init("earlytimer", &sh_tmu_device_driver);
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subsys_initcall(sh_tmu_init);
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module_exit(sh_tmu_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("SuperH TMU Timer Driver");
MODULE_LICENSE("GPL v2");
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