ata_piix.c 38.3 KB
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/*
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 *    ata_piix.c - Intel PATA/SATA controllers
 *
 *    Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *    		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *
 *	Copyright 2003-2005 Red Hat Inc
 *	Copyright 2003-2005 Jeff Garzik
 *
 *
 *	Copyright header from piix.c:
 *
 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available at http://developer.intel.com/
 *
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 * Documentation
 *	Publically available from Intel web site. Errata documentation
 * is also publically available. As an aide to anyone hacking on this
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 * driver the list of errata that are relevant is below, going back to
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 * PIIX4. Older device documentation is now a bit tricky to find.
 *
 * The chipsets all follow very much the same design. The orginal Triton
 * series chipsets do _not_ support independant device timings, but this
 * is fixed in Triton II. With the odd mobile exception the chips then
 * change little except in gaining more modes until SATA arrives. This
 * driver supports only the chips with independant timing (that is those
 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
 * for the early chip drivers.
 *
 * Errata of note:
 *
 * Unfixable
 *	PIIX4    errata #9	- Only on ultra obscure hw
 *	ICH3	 errata #13     - Not observed to affect real hw
 *				  by Intel
 *
 * Things we must deal with
 *	PIIX4	errata #10	- BM IDE hang with non UDMA
 *				  (must stop/start dma to recover)
 *	440MX   errata #15	- As PIIX4 errata #10
 *	PIIX4	errata #15	- Must not read control registers
 * 				  during a PIO transfer
 *	440MX   errata #13	- As PIIX4 errata #15
 *	ICH2	errata #21	- DMA mode 0 doesn't work right
 *	ICH0/1  errata #55	- As ICH2 errata #21
 *	ICH2	spec c #9	- Extra operations needed to handle
 *				  drive hotswap [NOT YET SUPPORTED]
 *	ICH2    spec c #20	- IDE PRD must not cross a 64K boundary
 *				  and must be dword aligned
 *	ICH2    spec c #24	- UDMA mode 4,5 t85/86 should be 6ns not 3.3
 *
 * Should have been BIOS fixed:
 *	450NX:	errata #19	- DMA hangs on old 450NX
 *	450NX:  errata #20	- DMA hangs on old 450NX
 *	450NX:  errata #25	- Corruption with DMA on old 450NX
 *	ICH3    errata #15      - IDE deadlock under high load
 *				  (BIOS must set dev 31 fn 0 bit 23)
 *	ICH3	errata #18	- Don't use native mode
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 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
#include <linux/libata.h>
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#include <linux/dmi.h>
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#define DRV_NAME	"ata_piix"
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#define DRV_VERSION	"2.12"
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enum {
	PIIX_IOCFG		= 0x54, /* IDE I/O configuration register */
	ICH5_PMR		= 0x90, /* port mapping register */
	ICH5_PCS		= 0x92,	/* port control and status */
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	PIIX_SCC		= 0x0A, /* sub-class code register */
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	PIIX_FLAG_SCR		= (1 << 26), /* SCR available */
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	PIIX_FLAG_AHCI		= (1 << 27), /* AHCI possible */
	PIIX_FLAG_CHECKINTR	= (1 << 28), /* make sure PCI INTx enabled */
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	PIIX_PATA_FLAGS		= ATA_FLAG_SLAVE_POSS,
	PIIX_SATA_FLAGS		= ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
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	/* combined mode.  if set, PATA is channel 0.
	 * if clear, PATA is channel 1.
	 */
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	PIIX_PORT_ENABLED	= (1 << 0),
	PIIX_PORT_PRESENT	= (1 << 4),
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	PIIX_80C_PRI		= (1 << 5) | (1 << 4),
	PIIX_80C_SEC		= (1 << 7) | (1 << 6),

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	/* controller IDs */
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	piix_pata_mwdma		= 0,	/* PIIX3 MWDMA only */
	piix_pata_33,			/* PIIX4 at 33Mhz */
	ich_pata_33,			/* ICH up to UDMA 33 only */
	ich_pata_66,			/* ICH up to 66 Mhz */
	ich_pata_100,			/* ICH up to UDMA 100 */
	ich5_sata,
	ich6_sata,
	ich6_sata_ahci,
	ich6m_sata_ahci,
	ich8_sata_ahci,
	ich8_2port_sata,
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	ich8m_apple_sata_ahci,		/* locks up on second port enable */
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	tolapai_sata_ahci,
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	/* constants for mapping table */
	P0			= 0,  /* port 0 */
	P1			= 1,  /* port 1 */
	P2			= 2,  /* port 2 */
	P3			= 3,  /* port 3 */
	IDE			= -1, /* IDE */
	NA			= -2, /* not avaliable */
	RV			= -3, /* reserved */

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	PIIX_AHCI_DEVICE	= 6,
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	/* host->flags bits */
	PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
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};

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struct piix_map_db {
	const u32 mask;
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	const u16 port_enable;
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	const int map[][4];
};

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struct piix_host_priv {
	const int *map;
};

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static int piix_init_one(struct pci_dev *pdev,
			 const struct pci_device_id *ent);
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static void piix_pata_error_handler(struct ata_port *ap);
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static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
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static int ich_pata_cable_detect(struct ata_port *ap);
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#ifdef CONFIG_PM
static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
static int piix_pci_device_resume(struct pci_dev *pdev);
#endif
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static unsigned int in_module_init = 1;

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static const struct pci_device_id piix_pci_tbl[] = {
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	/* Intel PIIX3 for the 430HX etc */
	{ 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
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	/* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
	/* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
	{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
	/* Intel PIIX4 */
	{ 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
	/* Intel PIIX4 */
	{ 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
	/* Intel PIIX */
	{ 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
	/* Intel ICH (i810, i815, i840) UDMA 66*/
	{ 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
	/* Intel ICH0 : UDMA 33*/
	{ 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
	/* Intel ICH2M */
	{ 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
	{ 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/*  Intel ICH3M */
	{ 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* Intel ICH3 (E7500/1) UDMA 100 */
	{ 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
	{ 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	{ 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* Intel ICH5 */
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	{ 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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	/* C-ICH (i810E2) */
	{ 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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	/* ESB (855GME/875P + 6300ESB) UDMA 100  */
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	{ 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* ICH6 (and 6) (i915) UDMA 100 */
	{ 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* ICH7/7-R (i945, i975) UDMA 100*/
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	{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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	{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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	/* ICH8 Mobile PATA Controller */
	{ 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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	/* NOTE: The following PCI ids must be kept in sync with the
	 * list in drivers/pci/quirks.c.
	 */

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	/* 82801EB (ICH5) */
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	{ 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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	/* 82801EB (ICH5) */
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	{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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	/* 6300ESB (ICH5 variant with broken PCS present bits) */
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	{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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	/* 6300ESB pretending RAID */
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	{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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	/* 82801FB/FW (ICH6/ICH6W) */
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	{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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	/* 82801FR/FRW (ICH6R/ICH6RW) */
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	{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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	/* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
	{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
	/* 82801GB/GR/GH (ICH7, identical to ICH6) */
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	{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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	/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
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	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
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	/* Enterprise Southbridge 2 (631xESB/632xESB) */
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	{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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	/* SATA Controller 1 IDE (ICH8) */
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	{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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	/* SATA Controller 2 IDE (ICH8) */
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	{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* Mobile SATA Controller IDE (ICH8M) */
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	{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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	/* Mobile SATA Controller IDE (ICH8M), Apple */
	{ 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
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	/* SATA Controller IDE (ICH9) */
	{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
	/* SATA Controller IDE (ICH9) */
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	{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* SATA Controller IDE (ICH9) */
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	{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* SATA Controller IDE (ICH9M) */
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	{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* SATA Controller IDE (ICH9M) */
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	{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* SATA Controller IDE (ICH9M) */
	{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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	/* SATA Controller IDE (Tolapai) */
	{ 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
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	{ }	/* terminate list */
};

static struct pci_driver piix_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= piix_pci_tbl,
	.probe			= piix_init_one,
	.remove			= ata_pci_remove_one,
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#ifdef CONFIG_PM
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	.suspend		= piix_pci_device_suspend,
	.resume			= piix_pci_device_resume,
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#endif
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};

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static struct scsi_host_template piix_sht = {
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	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
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	.slave_destroy		= ata_scsi_slave_destroy,
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	.bios_param		= ata_std_bios_param,
};

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static const struct ata_port_operations piix_pata_ops = {
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	.set_piomode		= piix_set_piomode,
	.set_dmamode		= piix_set_dmamode,
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	.mode_filter		= ata_pci_default_filter,
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	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
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	.data_xfer		= ata_data_xfer,
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	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
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	.error_handler		= piix_pata_error_handler,
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	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
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	.cable_detect		= ata_cable_40wire,
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	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
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	.irq_on			= ata_irq_on,
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	.port_start		= ata_port_start,
};

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static const struct ata_port_operations ich_pata_ops = {
	.set_piomode		= piix_set_piomode,
	.set_dmamode		= ich_set_dmamode,
	.mode_filter		= ata_pci_default_filter,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
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	.data_xfer		= ata_data_xfer,
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	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
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	.error_handler		= piix_pata_error_handler,
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	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
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	.cable_detect		= ich_pata_cable_detect,
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	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
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	.irq_on			= ata_irq_on,
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	.port_start		= ata_port_start,
};

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static const struct ata_port_operations piix_sata_ops = {
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	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
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	.data_xfer		= ata_data_xfer,
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	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
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	.error_handler		= ata_bmdma_error_handler,
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	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
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	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
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	.irq_on			= ata_irq_on,
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	.port_start		= ata_port_start,
};

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static const struct piix_map_db ich5_map_db = {
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	.mask = 0x7,
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	.port_enable = 0x3,
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	.map = {
		/* PM   PS   SM   SS       MAP  */
		{  P0,  NA,  P1,  NA }, /* 000b */
		{  P1,  NA,  P0,  NA }, /* 001b */
		{  RV,  RV,  RV,  RV },
		{  RV,  RV,  RV,  RV },
		{  P0,  P1, IDE, IDE }, /* 100b */
		{  P1,  P0, IDE, IDE }, /* 101b */
		{ IDE, IDE,  P0,  P1 }, /* 110b */
		{ IDE, IDE,  P1,  P0 }, /* 111b */
	},
};

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static const struct piix_map_db ich6_map_db = {
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	.mask = 0x3,
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	.port_enable = 0xf,
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	.map = {
		/* PM   PS   SM   SS       MAP */
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		{  P0,  P2,  P1,  P3 }, /* 00b */
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		{ IDE, IDE,  P1,  P3 }, /* 01b */
		{  P0,  P2, IDE, IDE }, /* 10b */
		{  RV,  RV,  RV,  RV },
	},
};

414
static const struct piix_map_db ich6m_map_db = {
415
	.mask = 0x3,
416
	.port_enable = 0x5,
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	/* Map 01b isn't specified in the doc but some notebooks use
419 420
	 * it anyway.  MAP 01b have been spotted on both ICH6M and
	 * ICH7M.
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	 */
	.map = {
		/* PM   PS   SM   SS       MAP */
424
		{  P0,  P2,  NA,  NA }, /* 00b */
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		{ IDE, IDE,  P1,  P3 }, /* 01b */
		{  P0,  P2, IDE, IDE }, /* 10b */
		{  RV,  RV,  RV,  RV },
	},
};

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static const struct piix_map_db ich8_map_db = {
	.mask = 0x3,
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	.port_enable = 0xf,
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	.map = {
		/* PM   PS   SM   SS       MAP */
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		{  P0,  P2,  P1,  P3 }, /* 00b (hardwired when in AHCI) */
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		{  RV,  RV,  RV,  RV },
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		{  P0,  P2, IDE, IDE }, /* 10b (IDE mode) */
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		{  RV,  RV,  RV,  RV },
	},
};

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static const struct piix_map_db ich8_2port_map_db = {
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	.mask = 0x3,
	.port_enable = 0x3,
	.map = {
		/* PM   PS   SM   SS       MAP */
		{  P0,  NA,  P1,  NA }, /* 00b */
		{  RV,  RV,  RV,  RV }, /* 01b */
		{  RV,  RV,  RV,  RV }, /* 10b */
		{  RV,  RV,  RV,  RV },
	},
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};

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static const struct piix_map_db ich8m_apple_map_db = {
	.mask = 0x3,
	.port_enable = 0x1,
	.map = {
		/* PM   PS   SM   SS       MAP */
		{  P0,  NA,  NA,  NA }, /* 00b */
		{  RV,  RV,  RV,  RV },
		{  P0,  P2, IDE, IDE }, /* 10b */
		{  RV,  RV,  RV,  RV },
	},
};

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static const struct piix_map_db tolapai_map_db = {
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	.mask = 0x3,
	.port_enable = 0x3,
	.map = {
		/* PM   PS   SM   SS       MAP */
		{  P0,  NA,  P1,  NA }, /* 00b */
		{  RV,  RV,  RV,  RV }, /* 01b */
		{  RV,  RV,  RV,  RV }, /* 10b */
		{  RV,  RV,  RV,  RV },
	},
};

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static const struct piix_map_db *piix_map_db_table[] = {
	[ich5_sata]		= &ich5_map_db,
	[ich6_sata]		= &ich6_map_db,
	[ich6_sata_ahci]	= &ich6_map_db,
	[ich6m_sata_ahci]	= &ich6m_map_db,
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	[ich8_sata_ahci]	= &ich8_map_db,
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	[ich8_2port_sata]	= &ich8_2port_map_db,
486
	[ich8m_apple_sata_ahci]	= &ich8m_apple_map_db,
487
	[tolapai_sata_ahci]	= &tolapai_map_db,
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};

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static struct ata_port_info piix_port_info[] = {
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	[piix_pata_mwdma] = 	/* PIIX3 MWDMA only */
	{
		.sht		= &piix_sht,
		.flags		= PIIX_PATA_FLAGS,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
		.port_ops	= &piix_pata_ops,
	},

500
	[piix_pata_33] =	/* PIIX4 at 33MHz */
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	{
		.sht		= &piix_sht,
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		.flags		= PIIX_PATA_FLAGS,
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		.pio_mask	= 0x1f,	/* pio0-4 */
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		.mwdma_mask	= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
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		.udma_mask	= ATA_UDMA_MASK_40C,
		.port_ops	= &piix_pata_ops,
	},

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	[ich_pata_33] = 	/* ICH0 - ICH at 33Mhz*/
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	{
		.sht		= &piix_sht,
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		.flags		= PIIX_PATA_FLAGS,
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		.pio_mask 	= 0x1f,	/* pio 0-4 */
		.mwdma_mask	= 0x06, /* Check: maybe 0x07  */
		.udma_mask	= ATA_UDMA2, /* UDMA33 */
		.port_ops	= &ich_pata_ops,
	},
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	[ich_pata_66] = 	/* ICH controllers up to 66MHz */
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	{
		.sht		= &piix_sht,
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		.flags		= PIIX_PATA_FLAGS,
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		.pio_mask 	= 0x1f,	/* pio 0-4 */
		.mwdma_mask	= 0x06, /* MWDMA0 is broken on chip */
		.udma_mask	= ATA_UDMA4,
		.port_ops	= &ich_pata_ops,
	},
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	[ich_pata_100] =
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	{
		.sht		= &piix_sht,
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		.flags		= PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
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		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x06, /* mwdma1-2 */
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		.udma_mask	= ATA_UDMA5, /* udma0-5 */
		.port_ops	= &ich_pata_ops,
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	},

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	[ich5_sata] =
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	{
		.sht		= &piix_sht,
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		.flags		= PIIX_SATA_FLAGS,
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		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &piix_sata_ops,
	},

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	[ich6_sata] =
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	{
		.sht		= &piix_sht,
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		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
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		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &piix_sata_ops,
	},

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	[ich6_sata_ahci] =
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	{
		.sht		= &piix_sht,
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		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
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				  PIIX_FLAG_AHCI,
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		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &piix_sata_ops,
	},
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	[ich6m_sata_ahci] =
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	{
		.sht		= &piix_sht,
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		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
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				  PIIX_FLAG_AHCI,
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		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &piix_sata_ops,
	},
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	[ich8_sata_ahci] =
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	{
		.sht		= &piix_sht,
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		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
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				  PIIX_FLAG_AHCI,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &piix_sata_ops,
	},
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	[ich8_2port_sata] =
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	{
		.sht		= &piix_sht,
		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
				  PIIX_FLAG_AHCI,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &piix_sata_ops,
	},
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	[tolapai_sata_ahci] =
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	{
		.sht		= &piix_sht,
		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
				  PIIX_FLAG_AHCI,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &piix_sata_ops,
	},
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	[ich8m_apple_sata_ahci] =
	{
		.sht		= &piix_sht,
		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
				  PIIX_FLAG_AHCI,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &piix_sata_ops,
	},

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};

static struct pci_bits piix_enable_bits[] = {
	{ 0x41U, 1U, 0x80UL, 0x80UL },	/* port 0 */
	{ 0x43U, 1U, 0x80UL, 0x80UL },	/* port 1 */
};

MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
MODULE_VERSION(DRV_VERSION);

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struct ich_laptop {
	u16 device;
	u16 subvendor;
	u16 subdevice;
};

/*
 *	List of laptops that use short cables rather than 80 wire
 */

static const struct ich_laptop ich_laptop[] = {
	/* devid, subvendor, subdev */
	{ 0x27DF, 0x0005, 0x0280 },	/* ICH7 on Acer 5602WLMi */
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	{ 0x27DF, 0x1025, 0x0102 },	/* ICH7 on Acer 5602aWLMi */
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	{ 0x27DF, 0x1025, 0x0110 },	/* ICH7 on Acer 3682WLMi */
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	{ 0x27DF, 0x1043, 0x1267 },	/* ICH7 on Asus W5F */
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	{ 0x27DF, 0x103C, 0x30A1 },	/* ICH7 on HP Compaq nc2400 */
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	{ 0x24CA, 0x1025, 0x0061 },	/* ICH4 on ACER Aspire 2023WLMi */
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	/* end marker */
	{ 0, }
};

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/**
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 *	ich_pata_cable_detect - Probe host controller cable detect info
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 *	@ap: Port for which cable detect info is desired
 *
 *	Read 80c cable indicator from ATA PCI device's PCI config
 *	register.  This register is normally set by firmware (BIOS).
 *
 *	LOCKING:
 *	None (inherited from caller).
 */
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static int ich_pata_cable_detect(struct ata_port *ap)
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{
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	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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	const struct ich_laptop *lap = &ich_laptop[0];
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	u8 tmp, mask;

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	/* Check for specials - Acer Aspire 5602WLMi */
	while (lap->device) {
		if (lap->device == pdev->device &&
		    lap->subvendor == pdev->subsystem_vendor &&
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		    lap->subdevice == pdev->subsystem_device)
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			return ATA_CBL_PATA40_SHORT;
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		lap++;
	}

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	/* check BIOS cable detect results */
689
	mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
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	pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
	if ((tmp & mask) == 0)
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		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
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}

/**
697
 *	piix_pata_prereset - prereset for PATA host controller
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 *	@link: Target link
699
 *	@deadline: deadline jiffies for the operation
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 *
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 *	LOCKING:
 *	None (inherited from caller).
 */
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static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
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{
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	struct ata_port *ap = link->ap;
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	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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	if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
		return -ENOENT;
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	return ata_std_prereset(link, deadline);
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}

static void piix_pata_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
			   ata_std_postreset);
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}

/**
 *	piix_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: um
 *
 *	Set PIO mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

731
static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
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	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
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	unsigned int is_slave	= (adev->devno != 0);
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	unsigned int master_port= ap->port_no ? 0x42 : 0x40;
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	unsigned int slave_port	= 0x44;
	u16 master_data;
	u8 slave_data;
740 741
	u8 udma_enable;
	int control = 0;
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743 744 745 746
	/*
	 *	See Intel Document 298600-004 for the timing programing rules
	 *	for ICH controllers.
	 */
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	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

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	if (pio >= 2)
		control |= 1;	/* TIME1 enable */
	if (ata_pio_need_iordy(adev))
		control |= 2;	/* IE enable */

760
	/* Intel specifies that the PPE functionality is for disk only */
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	if (adev->class == ATA_DEV_ATA)
		control |= 4;	/* PPE enable */

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	/* PIO configuration clears DTE unconditionally.  It will be
	 * programmed in set_dmamode which is guaranteed to be called
	 * after set_piomode if any DMA mode is available.
	 */
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	pci_read_config_word(dev, master_port, &master_data);
	if (is_slave) {
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		/* clear TIME1|IE1|PPE1|DTE1 */
		master_data &= 0xff0f;
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		/* Enable SITRE (seperate slave timing register) */
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		master_data |= 0x4000;
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		/* enable PPE1, IE1 and TIME1 as needed */
		master_data |= (control << 4);
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		pci_read_config_byte(dev, slave_port, &slave_data);
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		slave_data &= (ap->port_no ? 0x0f : 0xf0);
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		/* Load the timing nibble for this slave */
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		slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
						<< (ap->port_no ? 4 : 0);
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	} else {
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		/* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
		master_data &= 0xccf0;
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		/* Enable PPE, IE and TIME as appropriate */
		master_data |= control;
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		/* load ISP and RCT */
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		master_data |=
			(timings[pio][0] << 12) |
			(timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
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	/* Ensure the UDMA bit is off - it will be turned back on if
	   UDMA is selected */
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	if (ap->udma_mask) {
		pci_read_config_byte(dev, 0x48, &udma_enable);
		udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
		pci_write_config_byte(dev, 0x48, udma_enable);
	}
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}

/**
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 *	do_pata_set_dmamode - Initialize host controller PATA PIO timings
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 *	@ap: Port whose timings we are configuring
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 *	@adev: Drive in question
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 *	@udma: udma mode, 0 - 6
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 *	@isich: set if the chip is an ICH device
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 *
 *	Set UDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

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static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
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{
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	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
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	u8 master_port		= ap->port_no ? 0x42 : 0x40;
	u16 master_data;
	u8 speed		= adev->dma_mode;
	int devid		= adev->devno + 2 * ap->port_no;
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	u8 udma_enable		= 0;
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	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	pci_read_config_word(dev, master_port, &master_data);
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	if (ap->udma_mask)
		pci_read_config_byte(dev, 0x48, &udma_enable);
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	if (speed >= XFER_UDMA_0) {
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		unsigned int udma = adev->dma_mode - XFER_UDMA_0;
		u16 udma_timing;
		u16 ideconf;
		int u_clock, u_speed;
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844
		/*
845
		 * UDMA is handled by a combination of clock switching and
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		 * selection of dividers
		 *
848
		 * Handy rule: Odd modes are UDMATIMx 01, even are 02
849
		 *	       except UDMA0 which is 00
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		 */
		u_speed = min(2 - (udma & 1), udma);
		if (udma == 5)
			u_clock = 0x1000;	/* 100Mhz */
		else if (udma > 2)
			u_clock = 1;		/* 66Mhz */
		else
			u_clock = 0;		/* 33Mhz */
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859
		udma_enable |= (1 << devid);
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		/* Load the CT/RP selection */
		pci_read_config_word(dev, 0x4A, &udma_timing);
		udma_timing &= ~(3 << (4 * devid));
		udma_timing |= u_speed << (4 * devid);
		pci_write_config_word(dev, 0x4A, udma_timing);

867
		if (isich) {
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			/* Select a 33/66/100Mhz clock */
			pci_read_config_word(dev, 0x54, &ideconf);
			ideconf &= ~(0x1001 << devid);
			ideconf |= u_clock << devid;
			/* For ICH or later we should set bit 10 for better
			   performance (WR_PingPong_En) */
			pci_write_config_word(dev, 0x54, ideconf);
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		}
	} else {
877 878 879 880 881 882 883 884 885 886 887 888
		/*
		 * MWDMA is driven by the PIO timings. We must also enable
		 * IORDY unconditionally along with TIME1. PPE has already
		 * been set when the PIO timing was set.
		 */
		unsigned int mwdma	= adev->dma_mode - XFER_MW_DMA_0;
		unsigned int control;
		u8 slave_data;
		const unsigned int needed_pio[3] = {
			XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
		};
		int pio = needed_pio[mwdma] - XFER_PIO_0;
889

890
		control = 3;	/* IORDY|TIME1 */
891

892 893
		/* If the drive MWDMA is faster than it can do PIO then
		   we must force PIO into PIO0 */
894

895 896 897 898 899 900 901 902
		if (adev->pio_mode < needed_pio[mwdma])
			/* Enable DMA timing only */
			control |= 8;	/* PIO cycles in PIO0 */

		if (adev->devno) {	/* Slave */
			master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
			master_data |= control << 4;
			pci_read_config_byte(dev, 0x44, &slave_data);
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			slave_data &= (ap->port_no ? 0x0f : 0xf0);
904 905 906 907
			/* Load the matching timing */
			slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
			pci_write_config_byte(dev, 0x44, slave_data);
		} else { 	/* Master */
908
			master_data &= 0xCCF4;	/* Mask out IORDY|TIME1|DMAONLY
909 910 911 912 913 914
						   and master timing bits */
			master_data |= control;
			master_data |=
				(timings[pio][0] << 12) |
				(timings[pio][1] << 8);
		}
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		if (ap->udma_mask) {
			udma_enable &= ~(1 << devid);
			pci_write_config_word(dev, master_port, master_data);
		}
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	}
921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936
	/* Don't scribble on 0x48 if the controller does not support UDMA */
	if (ap->udma_mask)
		pci_write_config_byte(dev, 0x48, udma_enable);
}

/**
 *	piix_set_dmamode - Initialize host controller PATA DMA timings
 *	@ap: Port whose timings we are configuring
 *	@adev: um
 *
 *	Set MW/UDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

937
static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
938 939 940 941 942 943 944 945 946 947 948 949 950 951 952
{
	do_pata_set_dmamode(ap, adev, 0);
}

/**
 *	ich_set_dmamode - Initialize host controller PATA DMA timings
 *	@ap: Port whose timings we are configuring
 *	@adev: um
 *
 *	Set MW/UDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

953
static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
954 955
{
	do_pata_set_dmamode(ap, adev, 1);
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}

958
#ifdef CONFIG_PM
959 960
static int piix_broken_suspend(void)
{
961
	static const struct dmi_system_id sysids[] = {
962 963 964 965 966 967 968
		{
			.ident = "TECRA M3",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
			},
		},
969 970 971 972 973 974 975
		{
			.ident = "TECRA M3",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
			},
		},
976 977 978 979 980 981 982
		{
			.ident = "TECRA M4",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
			},
		},
983 984 985 986 987 988
		{
			.ident = "TECRA M5",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
			},
989
		},
990 991 992 993 994 995 996
		{
			.ident = "TECRA M7",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
			},
		},
997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010
		{
			.ident = "TECRA A8",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
			},
		},
		{
			.ident = "Satellite R25",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
			},
		},
1011 1012 1013 1014 1015 1016 1017
		{
			.ident = "Satellite U200",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
			},
		},
1018 1019 1020 1021 1022 1023 1024
		{
			.ident = "Satellite U200",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
			},
		},
1025 1026 1027 1028 1029 1030 1031
		{
			.ident = "Satellite Pro U200",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
			},
		},
1032 1033 1034 1035 1036 1037
		{
			.ident = "Satellite U205",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
			},
1038
		},
1039 1040 1041 1042 1043 1044 1045
		{
			.ident = "SATELLITE U205",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
			},
		},
1046 1047 1048 1049 1050 1051
		{
			.ident = "Portege M500",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
			},
1052
		},
1053 1054

		{ }	/* terminate list */
1055
	};
1056 1057 1058 1059
	static const char *oemstrs[] = {
		"Tecra M3,",
	};
	int i;
1060 1061 1062 1063

	if (dmi_check_system(sysids))
		return 1;

1064 1065 1066 1067
	for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
		if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
			return 1;

1068 1069
	return 0;
}
1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085

static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	unsigned long flags;
	int rc = 0;

	rc = ata_host_suspend(host, mesg);
	if (rc)
		return rc;

	/* Some braindamaged ACPI suspend implementations expect the
	 * controller to be awake on entry; otherwise, it burns cpu
	 * cycles and power trying to do something to the sleeping
	 * beauty.
	 */
1086
	if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120
		pci_save_state(pdev);

		/* mark its power state as "unknown", since we don't
		 * know if e.g. the BIOS will change its device state
		 * when we suspend.
		 */
		if (pdev->current_state == PCI_D0)
			pdev->current_state = PCI_UNKNOWN;

		/* tell resume that it's waking up from broken suspend */
		spin_lock_irqsave(&host->lock, flags);
		host->flags |= PIIX_HOST_BROKEN_SUSPEND;
		spin_unlock_irqrestore(&host->lock, flags);
	} else
		ata_pci_device_do_suspend(pdev, mesg);

	return 0;
}

static int piix_pci_device_resume(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	unsigned long flags;
	int rc;

	if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
		spin_lock_irqsave(&host->lock, flags);
		host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
		spin_unlock_irqrestore(&host->lock, flags);

		pci_set_power_state(pdev, PCI_D0);
		pci_restore_state(pdev);

		/* PCI device wasn't disabled during suspend.  Use
1121 1122
		 * pci_reenable_device() to avoid affecting the enable
		 * count.
1123
		 */
1124
		rc = pci_reenable_device(pdev);
1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137
		if (rc)
			dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
				   "device after resume (%d)\n", rc);
	} else
		rc = ata_pci_device_do_resume(pdev);

	if (rc == 0)
		ata_host_resume(host);

	return rc;
}
#endif

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#define AHCI_PCI_BAR 5
#define AHCI_GLOBAL_CTL 0x04
#define AHCI_ENABLE (1 << 31)
static int piix_disable_ahci(struct pci_dev *pdev)
{
1143
	void __iomem *mmio;
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	u32 tmp;
	int rc = 0;

	/* BUG: pci_enable_device has not yet been called.  This
	 * works because this device is usually set up by BIOS.
	 */

1151 1152
	if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
	    !pci_resource_len(pdev, AHCI_PCI_BAR))
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		return 0;
1154

1155
	mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
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	if (!mmio)
		return -ENOMEM;
1158

1159
	tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
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	if (tmp & AHCI_ENABLE) {
		tmp &= ~AHCI_ENABLE;
1162
		iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
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1163

1164
		tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
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1165 1166 1167
		if (tmp & AHCI_ENABLE)
			rc = -EIO;
	}
1168

1169
	pci_iounmap(pdev, mmio);
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	return rc;
}

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/**
 *	piix_check_450nx_errata	-	Check for problem 450NX setup
1175
 *	@ata_dev: the PCI device to check
1176
 *
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 *	Check for the present of 450NX errata #19 and errata #25. If
 *	they are found return an error code so we can turn off DMA
 */

static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
{
	struct pci_dev *pdev = NULL;
	u16 cfg;
	int no_piix_dma = 0;
1186

1187
	while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
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		/* Look for 450NX PXB. Check for problem configurations
		   A PCI quirk checks bit 6 already */
		pci_read_config_word(pdev, 0x41, &cfg);
		/* Only on the original revision: IDE DMA can hang */
1192
		if (pdev->revision == 0x00)
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1193 1194
			no_piix_dma = 1;
		/* On all revisions below 5 PXB bus lock must be disabled for IDE */
1195
		else if (cfg & (1<<14) && pdev->revision < 5)
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1196 1197
			no_piix_dma = 2;
	}
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1198
	if (no_piix_dma)
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1199
		dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
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1200
	if (no_piix_dma == 2)
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1201 1202
		dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
	return no_piix_dma;
1203
}
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1205
static void __devinit piix_init_pcs(struct pci_dev *pdev,
1206
				    struct ata_port_info *pinfo,
1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221
				    const struct piix_map_db *map_db)
{
	u16 pcs, new_pcs;

	pci_read_config_word(pdev, ICH5_PCS, &pcs);

	new_pcs = pcs | map_db->port_enable;

	if (new_pcs != pcs) {
		DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
		pci_write_config_word(pdev, ICH5_PCS, new_pcs);
		msleep(150);
	}
}

1222
static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1223 1224
					 struct ata_port_info *pinfo,
					 const struct piix_map_db *map_db)
1225
{
1226
	struct piix_host_priv *hpriv = pinfo[0].private_data;
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1227
	const int *map;
1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248
	int i, invalid_map = 0;
	u8 map_value;

	pci_read_config_byte(pdev, ICH5_PMR, &map_value);

	map = map_db->map[map_value & map_db->mask];

	dev_printk(KERN_INFO, &pdev->dev, "MAP [");
	for (i = 0; i < 4; i++) {
		switch (map[i]) {
		case RV:
			invalid_map = 1;
			printk(" XX");
			break;

		case NA:
			printk(" --");
			break;

		case IDE:
			WARN_ON((i & 1) || map[i + 1] != IDE);
1249
			pinfo[i / 2] = piix_port_info[ich_pata_100];
1250
			pinfo[i / 2].private_data = hpriv;
1251 1252 1253 1254 1255 1256 1257
			i++;
			printk(" IDE IDE");
			break;

		default:
			printk(" P%d", map[i]);
			if (i & 1)
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				pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1259 1260 1261 1262 1263 1264 1265 1266 1267
			break;
		}
	}
	printk(" ]\n");

	if (invalid_map)
		dev_printk(KERN_ERR, &pdev->dev,
			   "invalid MAP value %u\n", map_value);

1268
	hpriv->map = map;
1269 1270
}

1271 1272
static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
{
1273
	static const struct dmi_system_id sysids[] = {
1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
		{
			/* Clevo M570U sets IOCFG bit 18 if the cdrom
			 * isn't used to boot the system which
			 * disables the channel.
			 */
			.ident = "M570U",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
				DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
			},
		},
1285 1286

		{ }	/* terminate list */
1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305
	};
	u32 iocfg;

	if (!dmi_check_system(sysids))
		return;

	/* The datasheet says that bit 18 is NOOP but certain systems
	 * seem to use it to disable a channel.  Clear the bit on the
	 * affected systems.
	 */
	pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
	if (iocfg & (1 << 18)) {
		dev_printk(KERN_INFO, &pdev->dev,
			   "applying IOCFG bit18 quirk\n");
		iocfg &= ~(1 << 18);
		pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
	}
}

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/**
 *	piix_init_one - Register PIIX ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in piix_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.  We probe for combined mode (sigh),
 *	and then hand over control to libata, for it to do the rest.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

1321
static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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1322 1323
{
	static int printed_version;
1324
	struct device *dev = &pdev->dev;
1325
	struct ata_port_info port_info[2];
T
Tejun Heo 已提交
1326
	const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1327
	struct piix_host_priv *hpriv;
J
Jeff Garzik 已提交
1328
	unsigned long port_flags;
L
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1329 1330

	if (!printed_version++)
1331 1332
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "version " DRV_VERSION "\n");
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1333 1334 1335 1336 1337

	/* no hotplugging support (FIXME) */
	if (!in_module_init)
		return -ENODEV;

1338
	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1339 1340 1341
	if (!hpriv)
		return -ENOMEM;

1342 1343
	port_info[0] = piix_port_info[ent->driver_data];
	port_info[1] = piix_port_info[ent->driver_data];
1344 1345
	port_info[0].private_data = hpriv;
	port_info[1].private_data = hpriv;
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1346

J
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1347
	port_flags = port_info[0].flags;
1348

J
Jeff Garzik 已提交
1349
	if (port_flags & PIIX_FLAG_AHCI) {
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1350 1351 1352 1353 1354 1355 1356
		u8 tmp;
		pci_read_config_byte(pdev, PIIX_SCC, &tmp);
		if (tmp == PIIX_AHCI_DEVICE) {
			int rc = piix_disable_ahci(pdev);
			if (rc)
				return rc;
		}
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1357 1358
	}

1359
	/* Initialize SATA map */
J
Jeff Garzik 已提交
1360
	if (port_flags & ATA_FLAG_SATA) {
1361 1362
		piix_init_sata_map(pdev, port_info,
				   piix_map_db_table[ent->driver_data]);
1363 1364
		piix_init_pcs(pdev, port_info,
			      piix_map_db_table[ent->driver_data]);
1365
	}
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1367 1368 1369
	/* apply IOCFG bit18 quirk */
	piix_iocfg_bit18_quirk(pdev);

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1370 1371 1372 1373 1374 1375
	/* On ICH5, some BIOSen disable the interrupt using the
	 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
	 * On ICH6, this bit has the same effect, but only when
	 * MSI is disabled (and it is disabled, as we don't use
	 * message-signalled interrupts currently).
	 */
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1376
	if (port_flags & PIIX_FLAG_CHECKINTR)
B
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1377
		pci_intx(pdev, 1);
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1378

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1379 1380 1381 1382
	if (piix_check_450nx_errata(pdev)) {
		/* This writes into the master table but it does not
		   really matter for this errata as we will apply it to
		   all the PIIX devices on the board */
1383 1384 1385 1386
		port_info[0].mwdma_mask = 0;
		port_info[0].udma_mask = 0;
		port_info[1].mwdma_mask = 0;
		port_info[1].udma_mask = 0;
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1387
	}
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Tejun Heo 已提交
1388
	return ata_pci_init_one(pdev, ppi);
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1389 1390 1391 1392 1393 1394
}

static int __init piix_init(void)
{
	int rc;

1395 1396
	DPRINTK("pci_register_driver\n");
	rc = pci_register_driver(&piix_pci_driver);
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	if (rc)
		return rc;

	in_module_init = 0;

	DPRINTK("done\n");
	return 0;
}

static void __exit piix_exit(void)
{
	pci_unregister_driver(&piix_pci_driver);
}

module_init(piix_init);
module_exit(piix_exit);