fsl_ssi.c 39.7 KB
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/*
 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
 *
 * Author: Timur Tabi <timur@freescale.com>
 *
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 * Copyright 2007-2010 Freescale Semiconductor, Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
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 *
 *
 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
 *
 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
 * one FIFO which combines all valid receive slots. We cannot even select
 * which slots we want to receive. The WM9712 with which this driver
 * was developed with always sends GPIO status data in slot 12 which
 * we receive in our (PCM-) data stream. The only chance we have is to
 * manually skip this data in the FIQ handler. With sampling rates different
 * from 48000Hz not every frame has valid receive data, so the ratio
 * between pcm data and GPIO status data changes. Our FIQ handler is not
 * able to handle this, hence this driver only works with 48000Hz sampling
 * rate.
 * Reading and writing AC97 registers is another challenge. The core
 * provides us status bits when the read register is updated with *another*
 * value. When we read the same register two times (and the register still
 * contains the same value) these status bits are not set. We work
 * around this by not polling these bits but only wait a fixed delay.
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 */

#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/of_address.h>
#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
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#include <sound/dmaengine_pcm.h>
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#include "fsl_ssi.h"
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#include "imx-pcm.h"
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#ifdef PPC
#define read_ssi(addr)			 in_be32(addr)
#define write_ssi(val, addr)		 out_be32(addr, val)
#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
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#else
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#define read_ssi(addr)			 readl(addr)
#define write_ssi(val, addr)		 writel(val, addr)
/*
 * FIXME: Proper locking should be added at write_ssi_mask caller level
 * to ensure this register read/modify/write sequence is race free.
 */
static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
{
	u32 val = readl(addr);
	val = (val & ~clear) | set;
	writel(val, addr);
}
#endif

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/**
 * FSLSSI_I2S_RATES: sample rates supported by the I2S
 *
 * This driver currently only supports the SSI running in I2S slave mode,
 * which means the codec determines the sample rate.  Therefore, we tell
 * ALSA that we support all rates and let the codec driver decide what rates
 * are really supported.
 */
#define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
			  SNDRV_PCM_RATE_CONTINUOUS)

/**
 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
 *
 * This driver currently only supports the SSI running in I2S slave mode.
 *
 * The SSI has a limitation in that the samples must be in the same byte
 * order as the host CPU.  This is because when multiple bytes are written
 * to the STX register, the bytes and bits must be written in the same
 * order.  The STX is a shift register, so all the bits need to be aligned
 * (bit-endianness must match byte-endianness).  Processors typically write
 * the bits within a byte in the same order that the bytes of a word are
 * written in.  So if the host CPU is big-endian, then only big-endian
 * samples will be written to STX properly.
 */
#ifdef __BIG_ENDIAN
#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
	 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
	 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
#else
#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
	 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
	 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
#endif

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/* SIER bitflag of interrupts to enable */
#define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
		    CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
		    CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
		    CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
		    CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)

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#define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
		CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
		CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
#define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
		CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
		CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
#define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS)

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enum fsl_ssi_type {
	FSL_SSI_MCP8610,
	FSL_SSI_MX21,
	FSL_SSI_MX51,
};

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/**
 * fsl_ssi_private: per-SSI private data
 *
 * @ssi: pointer to the SSI's registers
 * @ssi_phys: physical address of the SSI registers
 * @irq: IRQ of this SSI
 * @playback: the number of playback streams opened
 * @capture: the number of capture streams opened
 * @cpu_dai: the CPU DAI for this device
 * @dev_attr: the sysfs device attribute structure
 * @stats: SSI statistics
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 * @name: name for this device
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 */
struct fsl_ssi_private {
	struct ccsr_ssi __iomem *ssi;
	dma_addr_t ssi_phys;
	unsigned int irq;
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	unsigned int fifo_depth;
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	struct snd_soc_dai_driver cpu_dai_drv;
	struct platform_device *pdev;
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	bool new_binding;
	bool ssi_on_imx;
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	bool imx_ac97;
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	bool use_dma;
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	bool baudclk_locked;
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	bool irq_stats;
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	u8 i2s_mode;
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	spinlock_t baudclk_lock;
	struct clk *baudclk;
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	struct clk *clk;
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	struct snd_dmaengine_dai_dma_data dma_params_tx;
	struct snd_dmaengine_dai_dma_data dma_params_rx;
	struct imx_dma_data filter_data_tx;
	struct imx_dma_data filter_data_rx;
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	struct imx_pcm_fiq_params fiq_params;
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	struct {
		unsigned int rfrc;
		unsigned int tfrc;
		unsigned int cmdau;
		unsigned int cmddu;
		unsigned int rxt;
		unsigned int rdr1;
		unsigned int rdr0;
		unsigned int tde1;
		unsigned int tde0;
		unsigned int roe1;
		unsigned int roe0;
		unsigned int tue1;
		unsigned int tue0;
		unsigned int tfs;
		unsigned int rfs;
		unsigned int tls;
		unsigned int rls;
		unsigned int rff1;
		unsigned int rff0;
		unsigned int tfe1;
		unsigned int tfe0;
	} stats;
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	struct dentry *dbg_dir;
	struct dentry *dbg_stats;
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	char name[1];
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};

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static const struct of_device_id fsl_ssi_ids[] = {
	{ .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610},
	{ .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51},
	{ .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21},
	{}
};
MODULE_DEVICE_TABLE(of, fsl_ssi_ids);

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/**
 * fsl_ssi_isr: SSI interrupt handler
 *
 * Although it's possible to use the interrupt handler to send and receive
 * data to/from the SSI, we use the DMA instead.  Programming is more
 * complicated, but the performance is much better.
 *
 * This interrupt handler is used only to gather statistics.
 *
 * @irq: IRQ of the SSI device
 * @dev_id: pointer to the ssi_private structure for this SSI device
 */
static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
{
	struct fsl_ssi_private *ssi_private = dev_id;
	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
	irqreturn_t ret = IRQ_NONE;
	__be32 sisr;
	__be32 sisr2 = 0;

	/* We got an interrupt, so read the status register to see what we
	   were interrupted for.  We mask it with the Interrupt Enable register
	   so that we only check for events that we're interested in.
	 */
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	sisr = read_ssi(&ssi->sisr) & FSLSSI_SISR_MASK;
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	if (sisr & CCSR_SSI_SISR_RFRC) {
		ssi_private->stats.rfrc++;
		sisr2 |= CCSR_SSI_SISR_RFRC;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_TFRC) {
		ssi_private->stats.tfrc++;
		sisr2 |= CCSR_SSI_SISR_TFRC;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_CMDAU) {
		ssi_private->stats.cmdau++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_CMDDU) {
		ssi_private->stats.cmddu++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_RXT) {
		ssi_private->stats.rxt++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_RDR1) {
		ssi_private->stats.rdr1++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_RDR0) {
		ssi_private->stats.rdr0++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_TDE1) {
		ssi_private->stats.tde1++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_TDE0) {
		ssi_private->stats.tde0++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_ROE1) {
		ssi_private->stats.roe1++;
		sisr2 |= CCSR_SSI_SISR_ROE1;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_ROE0) {
		ssi_private->stats.roe0++;
		sisr2 |= CCSR_SSI_SISR_ROE0;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_TUE1) {
		ssi_private->stats.tue1++;
		sisr2 |= CCSR_SSI_SISR_TUE1;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_TUE0) {
		ssi_private->stats.tue0++;
		sisr2 |= CCSR_SSI_SISR_TUE0;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_TFS) {
		ssi_private->stats.tfs++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_RFS) {
		ssi_private->stats.rfs++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_TLS) {
		ssi_private->stats.tls++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_RLS) {
		ssi_private->stats.rls++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_RFF1) {
		ssi_private->stats.rff1++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_RFF0) {
		ssi_private->stats.rff0++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_TFE1) {
		ssi_private->stats.tfe1++;
		ret = IRQ_HANDLED;
	}

	if (sisr & CCSR_SSI_SISR_TFE0) {
		ssi_private->stats.tfe0++;
		ret = IRQ_HANDLED;
	}

	/* Clear the bits that we set */
	if (sisr2)
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		write_ssi(sisr2, &ssi->sisr);
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	return ret;
}

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#if IS_ENABLED(CONFIG_DEBUG_FS)
/* Show the statistics of a flag only if its interrupt is enabled.  The
 * compiler will optimze this code to a no-op if the interrupt is not
 * enabled.
 */
#define SIER_SHOW(flag, name) \
	do { \
		if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \
			seq_printf(s, #name "=%u\n", ssi_private->stats.name); \
	} while (0)


/**
 * fsl_sysfs_ssi_show: display SSI statistics
 *
 * Display the statistics for the current SSI device.  To avoid confusion,
 * we only show those counts that are enabled.
 */
static ssize_t fsl_ssi_stats_show(struct seq_file *s, void *unused)
{
	struct fsl_ssi_private *ssi_private = s->private;

	SIER_SHOW(RFRC_EN, rfrc);
	SIER_SHOW(TFRC_EN, tfrc);
	SIER_SHOW(CMDAU_EN, cmdau);
	SIER_SHOW(CMDDU_EN, cmddu);
	SIER_SHOW(RXT_EN, rxt);
	SIER_SHOW(RDR1_EN, rdr1);
	SIER_SHOW(RDR0_EN, rdr0);
	SIER_SHOW(TDE1_EN, tde1);
	SIER_SHOW(TDE0_EN, tde0);
	SIER_SHOW(ROE1_EN, roe1);
	SIER_SHOW(ROE0_EN, roe0);
	SIER_SHOW(TUE1_EN, tue1);
	SIER_SHOW(TUE0_EN, tue0);
	SIER_SHOW(TFS_EN, tfs);
	SIER_SHOW(RFS_EN, rfs);
	SIER_SHOW(TLS_EN, tls);
	SIER_SHOW(RLS_EN, rls);
	SIER_SHOW(RFF1_EN, rff1);
	SIER_SHOW(RFF0_EN, rff0);
	SIER_SHOW(TFE1_EN, tfe1);
	SIER_SHOW(TFE0_EN, tfe0);

	return 0;
}

static int fsl_ssi_stats_open(struct inode *inode, struct file *file)
{
	return single_open(file, fsl_ssi_stats_show, inode->i_private);
}

static const struct file_operations fsl_ssi_stats_ops = {
	.open = fsl_ssi_stats_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
};

static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
		struct device *dev)
{
	ssi_private->dbg_dir = debugfs_create_dir(dev_name(dev), NULL);
	if (!ssi_private->dbg_dir)
		return -ENOMEM;

	ssi_private->dbg_stats = debugfs_create_file("stats", S_IRUGO,
			ssi_private->dbg_dir, ssi_private, &fsl_ssi_stats_ops);
	if (!ssi_private->dbg_stats) {
		debugfs_remove(ssi_private->dbg_dir);
		return -ENOMEM;
	}

	return 0;
}

static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
{
	debugfs_remove(ssi_private->dbg_stats);
	debugfs_remove(ssi_private->dbg_dir);
}

#else

static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
		struct device *dev)
{
	return 0;
}

static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
{
}

#endif /* IS_ENABLED(CONFIG_DEBUG_FS) */

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static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
{
	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;

	/*
	 * Setup the clock control register
	 */
	write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
			&ssi->stccr);
	write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
			&ssi->srccr);

	/*
	 * Enable AC97 mode and startup the SSI
	 */
	write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
			&ssi->sacnt);
	write_ssi(0xff, &ssi->saccdis);
	write_ssi(0x300, &ssi->saccen);

	/*
	 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
	 * codec before a stream is started.
	 */
	write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
			CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);

	write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
}

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static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
{
	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
	u8 wm;
	int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;

	if (ssi_private->imx_ac97)
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		ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
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	else
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		ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
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	/*
	 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
	 * to be disabled before updating the registers we set here.
	 */
	write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);

	/*
	 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
	 * enable the transmit and receive FIFO.
	 *
	 * FIXME: Little-endian samples require a different shift dir
	 */
	write_ssi_mask(&ssi->scr,
		CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
		CCSR_SSI_SCR_TFR_CLK_DIS |
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		ssi_private->i2s_mode |
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		(synchronous ? CCSR_SSI_SCR_SYN : 0));

	write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
		 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
		 CCSR_SSI_STCR_TSCKP, &ssi->stcr);

	write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
		 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
		 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
	/*
	 * The DC and PM bits are only used if the SSI is the clock master.
	 */

	/*
	 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
	 * use FIFO 1. We program the transmit water to signal a DMA transfer
	 * if there are only two (or fewer) elements left in the FIFO. Two
	 * elements equals one frame (left channel, right channel). This value,
	 * however, depends on the depth of the transmit buffer.
	 *
	 * We set the watermark on the same level as the DMA burstsize.  For
	 * fiq it is probably better to use the biggest possible watermark
	 * size.
	 */
	if (ssi_private->use_dma)
		wm = ssi_private->fifo_depth - 2;
	else
		wm = ssi_private->fifo_depth;

	write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
		CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
		&ssi->sfcsr);

	/*
	 * For ac97 interrupts are enabled with the startup of the substream
	 * because it is also running without an active substream. Normally SSI
	 * is only enabled when there is a substream.
	 */
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	if (ssi_private->imx_ac97)
		fsl_ssi_setup_ac97(ssi_private);
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	return 0;
}


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/**
 * fsl_ssi_startup: create a new substream
 *
 * This is the first function called when a stream is opened.
 *
 * If this is the first stream open, then grab the IRQ and program most of
 * the SSI registers.
 */
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static int fsl_ssi_startup(struct snd_pcm_substream *substream,
			   struct snd_soc_dai *dai)
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{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
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	struct fsl_ssi_private *ssi_private =
		snd_soc_dai_get_drvdata(rtd->cpu_dai);
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	unsigned long flags;
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	/* First, we only do fsl_ssi_setup() when SSI is going to be active.
	 * Second, fsl_ssi_setup was already called by ac97_init earlier if
	 * the driver is in ac97 mode.
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	 */
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	if (!dai->active && !ssi_private->imx_ac97) {
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		fsl_ssi_setup(ssi_private);
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		spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
		ssi_private->baudclk_locked = false;
		spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
	}
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	return 0;
}

/**
580
 * fsl_ssi_hw_params - program the sample size
581 582 583 584 585 586 587 588 589 590 591
 *
 * Most of the SSI registers have been programmed in the startup function,
 * but the word length must be programmed here.  Unfortunately, programming
 * the SxCCR.WL bits requires the SSI to be temporarily disabled.  This can
 * cause a problem with supporting simultaneous playback and capture.  If
 * the SSI is already playing a stream, then that stream may be temporarily
 * stopped when you start capture.
 *
 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
 * clock master.
 */
592 593
static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
594
{
595
	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
596
	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
597
	unsigned int channels = params_channels(hw_params);
598 599 600
	unsigned int sample_size =
		snd_pcm_format_width(params_format(hw_params));
	u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
601
	int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
602

603 604 605 606 607 608
	/*
	 * If we're in synchronous mode, and the SSI is already enabled,
	 * then STCCR is already set properly.
	 */
	if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
		return 0;
609

610 611 612 613 614 615 616 617 618
	/*
	 * FIXME: The documentation says that SxCCR[WL] should not be
	 * modified while the SSI is enabled.  The only time this can
	 * happen is if we're trying to do simultaneous playback and
	 * capture in asynchronous mode.  Unfortunately, I have been enable
	 * to get that to work at all on the P1022DS.  Therefore, we don't
	 * bother to disable/enable the SSI when setting SxCCR[WL], because
	 * the SSI will stop anyway.  Maybe one day, this will get fixed.
	 */
619

620 621 622
	/* In synchronous mode, the SSI uses STCCR for capture */
	if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
	    ssi_private->cpu_dai_drv.symmetric_rates)
623
		write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
624
	else
625
		write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
626

627 628 629 630 631
	if (!ssi_private->imx_ac97)
		write_ssi_mask(&ssi->scr,
				CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
				channels == 1 ? 0 : ssi_private->i2s_mode);

632 633 634
	return 0;
}

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/**
 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
 */
static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
	u32 strcr = 0, stcr, srcr, scr, mask;

	scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
	scr |= CCSR_SSI_SCR_NET;

	mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
		CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
		CCSR_SSI_STCR_TEFS;
	stcr = read_ssi(&ssi->stcr) & ~mask;
	srcr = read_ssi(&ssi->srcr) & ~mask;

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
		case SND_SOC_DAIFMT_CBS_CFS:
			ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_MASTER;
			break;
		case SND_SOC_DAIFMT_CBM_CFM:
			ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
			break;
		default:
			return -EINVAL;
		}
		scr |= ssi_private->i2s_mode;

		/* Data on rising edge of bclk, frame low, 1clk before data */
		strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
			CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		/* Data on rising edge of bclk, frame high */
		strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
		break;
	case SND_SOC_DAIFMT_DSP_A:
		/* Data on rising edge of bclk, frame high, 1clk before data */
		strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
			CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		/* Data on rising edge of bclk, frame high */
		strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
			CCSR_SSI_STCR_TXBIT0;
		break;
	default:
		return -EINVAL;
	}

	/* DAI clock inversion */
	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		/* Nothing to do for both normal cases */
		break;
	case SND_SOC_DAIFMT_IB_NF:
		/* Invert bit clock */
		strcr ^= CCSR_SSI_STCR_TSCKP;
		break;
	case SND_SOC_DAIFMT_NB_IF:
		/* Invert frame clock */
		strcr ^= CCSR_SSI_STCR_TFSI;
		break;
	case SND_SOC_DAIFMT_IB_IF:
		/* Invert both clocks */
		strcr ^= CCSR_SSI_STCR_TSCKP;
		strcr ^= CCSR_SSI_STCR_TFSI;
		break;
	default:
		return -EINVAL;
	}

	/* DAI clock master masks */
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
		scr |= CCSR_SSI_SCR_SYS_CLK_EN;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
		break;
	default:
		return -EINVAL;
	}

	stcr |= strcr;
	srcr |= strcr;

	if (ssi_private->cpu_dai_drv.symmetric_rates) {
		/* Need to clear RXDIR when using SYNC mode */
		srcr &= ~CCSR_SSI_SRCR_RXDIR;
		scr |= CCSR_SSI_SCR_SYN;
	}

	write_ssi(stcr, &ssi->stcr);
	write_ssi(srcr, &ssi->srcr);
	write_ssi(scr, &ssi->scr);

	return 0;
}

/**
 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
 *
 * Note: This function can be only called when using SSI as DAI master
 *
 * Quick instruction for parameters:
 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
 */
static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
	int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
	u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
	unsigned long flags, clkrate, baudrate, tmprate;
	u64 sub, savesub = 100000;

	/* Don't apply it to any non-baudclk circumstance */
	if (IS_ERR(ssi_private->baudclk))
		return -EINVAL;

	/* It should be already enough to divide clock by setting pm alone */
	psr = 0;
	div2 = 0;

	factor = (div2 + 1) * (7 * psr + 1) * 2;

	for (i = 0; i < 255; i++) {
		/* The bclk rate must be smaller than 1/5 sysclk rate */
		if (factor * (i + 1) < 5)
			continue;

		tmprate = freq * factor * (i + 2);
		clkrate = clk_round_rate(ssi_private->baudclk, tmprate);

		do_div(clkrate, factor);
		afreq = (u32)clkrate / (i + 1);

		if (freq == afreq)
			sub = 0;
		else if (freq / afreq == 1)
			sub = freq - afreq;
		else if (afreq / freq == 1)
			sub = afreq - freq;
		else
			continue;

		/* Calculate the fraction */
		sub *= 100000;
		do_div(sub, freq);

		if (sub < savesub) {
			baudrate = tmprate;
			savesub = sub;
			pm = i;
		}

		/* We are lucky */
		if (savesub == 0)
			break;
	}

	/* No proper pm found if it is still remaining the initial value */
	if (pm == 999) {
		dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
		return -EINVAL;
	}

	stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
		(psr ? CCSR_SSI_SxCCR_PSR : 0);
	mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR;

	if (dir == SND_SOC_CLOCK_OUT || synchronous)
		write_ssi_mask(&ssi->stccr, mask, stccr);
	else
		write_ssi_mask(&ssi->srccr, mask, stccr);

	spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
	if (!ssi_private->baudclk_locked) {
		ret = clk_set_rate(ssi_private->baudclk, baudrate);
		if (ret) {
			spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
			dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
			return -EINVAL;
		}
		ssi_private->baudclk_locked = true;
	}
	spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);

	return 0;
}

/**
 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
 *
 * Note: This function can be only called when using SSI as DAI master
 */
static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
				u32 rx_mask, int slots, int slot_width)
{
	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
	u32 val;

	/* The slot number should be >= 2 if using Network mode or I2S mode */
	val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
	if (val && slots < 2) {
		dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
		return -EINVAL;
	}

	write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
			CCSR_SSI_SxCCR_DC(slots));
	write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
			CCSR_SSI_SxCCR_DC(slots));

	/* The register SxMSKs needs SSI to provide essential clock due to
	 * hardware design. So we here temporarily enable SSI to set them.
	 */
	val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
	write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);

	write_ssi(tx_mask, &ssi->stmsk);
	write_ssi(rx_mask, &ssi->srmsk);

	write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);

	return 0;
}

872 873 874 875 876 877 878 879 880
/**
 * fsl_ssi_trigger: start and stop the DMA transfer.
 *
 * This function is called by ALSA to start, stop, pause, and resume the DMA
 * transfer of data.
 *
 * The DMA channel is in external master start and pause mode, which
 * means the SSI completely controls the flow of data.
 */
881 882
static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
			   struct snd_soc_dai *dai)
883 884
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
885
	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
886
	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
887
	unsigned int sier_bits;
888
	unsigned long flags;
889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908

	/*
	 *  Enable only the interrupts and DMA requests
	 *  that are needed for the channel. As the fiq
	 *  is polling for this bits, we have to ensure
	 *  that this are aligned with the preallocated
	 *  buffers
	 */

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		if (ssi_private->use_dma)
			sier_bits = SIER_FLAGS;
		else
			sier_bits = CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN;
	} else {
		if (ssi_private->use_dma)
			sier_bits = SIER_FLAGS;
		else
			sier_bits = CCSR_SSI_SIER_RIE | CCSR_SSI_SIER_RFF0_EN;
	}
909 910 911 912

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
913
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
914
			write_ssi_mask(&ssi->scr, 0,
915
				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
916
		else
917
			write_ssi_mask(&ssi->scr, 0,
918
				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
919 920 921 922 923
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
924
			write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
925
		else
926
			write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
927

928
		if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
929
					(CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
930
			write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
931 932 933 934
			spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
			ssi_private->baudclk_locked = false;
			spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
		}
935 936 937 938 939 940
		break;

	default:
		return -EINVAL;
	}

941 942
	write_ssi(sier_bits, &ssi->sier);

943 944 945
	return 0;
}

946 947 948 949
static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
{
	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);

950
	if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
951 952 953 954 955 956 957
		dai->playback_dma_data = &ssi_private->dma_params_tx;
		dai->capture_dma_data = &ssi_private->dma_params_rx;
	}

	return 0;
}

958
static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
959 960
	.startup	= fsl_ssi_startup,
	.hw_params	= fsl_ssi_hw_params,
961 962 963
	.set_fmt	= fsl_ssi_set_dai_fmt,
	.set_sysclk	= fsl_ssi_set_dai_sysclk,
	.set_tdm_slot	= fsl_ssi_set_dai_tdm_slot,
964 965 966
	.trigger	= fsl_ssi_trigger,
};

967 968
/* Template for the CPU dai driver structure */
static struct snd_soc_dai_driver fsl_ssi_dai_template = {
969
	.probe = fsl_ssi_dai_probe,
970
	.playback = {
971
		.channels_min = 1,
972 973 974 975 976
		.channels_max = 2,
		.rates = FSLSSI_I2S_RATES,
		.formats = FSLSSI_I2S_FORMATS,
	},
	.capture = {
977
		.channels_min = 1,
978 979 980 981
		.channels_max = 2,
		.rates = FSLSSI_I2S_RATES,
		.formats = FSLSSI_I2S_FORMATS,
	},
982
	.ops = &fsl_ssi_dai_ops,
983 984
};

985 986 987 988
static const struct snd_soc_component_driver fsl_ssi_component = {
	.name		= "fsl-ssi",
};

989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067
/**
 * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
 *
 * This function is called by ALSA to start, stop, pause, and resume the
 * transfer of data.
 */
static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
			   struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(
			rtd->cpu_dai);
	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE |
					CCSR_SSI_SIER_TFE0_EN);
		else
			write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE |
					CCSR_SSI_SIER_RFF0_EN);
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE |
					CCSR_SSI_SIER_TFE0_EN, 0);
		else
			write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE |
					CCSR_SSI_SIER_RFF0_EN, 0);
		break;

	default:
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
	else
		write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);

	return 0;
}

static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = {
	.startup	= fsl_ssi_startup,
	.trigger	= fsl_ssi_ac97_trigger,
};

static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
	.ac97_control = 1,
	.playback = {
		.stream_name = "AC97 Playback",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.stream_name = "AC97 Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &fsl_ssi_ac97_dai_ops,
};


static struct fsl_ssi_private *fsl_ac97_data;

static void fsl_ssi_ac97_init(void)
{
	fsl_ssi_setup(fsl_ac97_data);
}

1068
static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089
		unsigned short val)
{
	struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
	unsigned int lreg;
	unsigned int lval;

	if (reg > 0x7f)
		return;


	lreg = reg <<  12;
	write_ssi(lreg, &ssi->sacadd);

	lval = val << 4;
	write_ssi(lval , &ssi->sacdat);

	write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
			CCSR_SSI_SACNT_WR);
	udelay(100);
}

1090
static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114
		unsigned short reg)
{
	struct ccsr_ssi *ssi = fsl_ac97_data->ssi;

	unsigned short val = -1;
	unsigned int lreg;

	lreg = (reg & 0x7f) <<  12;
	write_ssi(lreg, &ssi->sacadd);
	write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
			CCSR_SSI_SACNT_RD);

	udelay(100);

	val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;

	return val;
}

static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
	.read		= fsl_ssi_ac97_read,
	.write		= fsl_ssi_ac97_write,
};

1115
/**
1116
 * Make every character in a string lower-case
1117
 */
1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129
static void make_lowercase(char *s)
{
	char *p = s;
	char c;

	while ((c = *p)) {
		if ((c >= 'A') && (c <= 'Z'))
			*p = c + ('a' - 'A');
		p++;
	}
}

1130
static int fsl_ssi_probe(struct platform_device *pdev)
1131 1132 1133
{
	struct fsl_ssi_private *ssi_private;
	int ret = 0;
1134
	struct device_attribute *dev_attr = NULL;
1135
	struct device_node *np = pdev->dev.of_node;
1136 1137
	const struct of_device_id *of_id;
	enum fsl_ssi_type hw_type;
1138
	const char *p, *sprop;
1139
	const uint32_t *iprop;
1140 1141
	struct resource res;
	char name[64];
1142
	bool shared;
1143
	bool ac97 = false;
1144

1145 1146 1147
	/* SSIs that are not connected on the board should have a
	 *      status = "disabled"
	 * property in their device tree nodes.
1148
	 */
1149
	if (!of_device_is_available(np))
1150 1151
		return -ENODEV;

1152 1153 1154 1155 1156
	of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
	if (!of_id)
		return -EINVAL;
	hw_type = (enum fsl_ssi_type) of_id->data;

1157 1158
	/* We only support the SSI in "I2S Slave" mode */
	sprop = of_get_property(np, "fsl,mode", NULL);
1159 1160 1161 1162 1163 1164 1165
	if (!sprop) {
		dev_err(&pdev->dev, "fsl,mode property is necessary\n");
		return -EINVAL;
	}
	if (!strcmp(sprop, "ac97-slave")) {
		ac97 = true;
	} else if (strcmp(sprop, "i2s-slave")) {
1166
		dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
1167 1168 1169 1170 1171
		return -ENODEV;
	}

	/* The DAI name is the last part of the full name of the node. */
	p = strrchr(np->full_name, '/') + 1;
1172
	ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
1173
			      GFP_KERNEL);
1174
	if (!ssi_private) {
1175
		dev_err(&pdev->dev, "could not allocate DAI object\n");
1176
		return -ENOMEM;
1177 1178
	}

1179
	strcpy(ssi_private->name, p);
1180

1181 1182 1183
	ssi_private->use_dma = !of_property_read_bool(np,
			"fsl,fiq-stream-filter");

1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196
	if (ac97) {
		memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
				sizeof(fsl_ssi_ac97_dai));

		fsl_ac97_data = ssi_private;
		ssi_private->imx_ac97 = true;

		snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
	} else {
		/* Initialize this copy of the CPU DAI driver structure */
		memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
		       sizeof(fsl_ssi_dai_template));
	}
1197 1198 1199 1200 1201
	ssi_private->cpu_dai_drv.name = ssi_private->name;

	/* Get the addresses and IRQ */
	ret = of_address_to_resource(np, 0, &res);
	if (ret) {
1202
		dev_err(&pdev->dev, "could not determine device resources\n");
1203
		return ret;
1204
	}
1205 1206 1207
	ssi_private->ssi = of_iomap(np, 0);
	if (!ssi_private->ssi) {
		dev_err(&pdev->dev, "could not map device resources\n");
1208
		return -ENOMEM;
1209
	}
1210
	ssi_private->ssi_phys = res.start;
1211

1212
	ssi_private->irq = irq_of_parse_and_map(np, 0);
1213
	if (!ssi_private->irq) {
1214
		dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1215
		return -ENXIO;
1216 1217
	}

1218
	/* Are the RX and the TX clocks locked? */
1219
	if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1220
		ssi_private->cpu_dai_drv.symmetric_rates = 1;
1221 1222 1223
		ssi_private->cpu_dai_drv.symmetric_channels = 1;
		ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
	}
1224

1225 1226 1227
	/* Determine the FIFO depth. */
	iprop = of_get_property(np, "fsl,fifo-depth", NULL);
	if (iprop)
1228
		ssi_private->fifo_depth = be32_to_cpup(iprop);
1229 1230 1231 1232
	else
                /* Older 8610 DTs didn't have the fifo-depth property */
		ssi_private->fifo_depth = 8;

1233 1234 1235
	ssi_private->baudclk_locked = false;
	spin_lock_init(&ssi_private->baudclk_lock);

1236 1237
	if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 ||
			hw_type == FSL_SSI_MX35) {
1238 1239
		u32 dma_events[2];
		ssi_private->ssi_on_imx = true;
1240

1241
		ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1242 1243 1244
		if (IS_ERR(ssi_private->clk)) {
			ret = PTR_ERR(ssi_private->clk);
			dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1245
			goto error_irqmap;
1246
		}
1247 1248 1249 1250 1251 1252
		ret = clk_prepare_enable(ssi_private->clk);
		if (ret) {
			dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
				ret);
			goto error_irqmap;
		}
1253

1254 1255 1256 1257 1258
		/* For those SLAVE implementations, we ingore non-baudclk cases
		 * and, instead, abandon MASTER mode that needs baud clock.
		 */
		ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
		if (IS_ERR(ssi_private->baudclk))
1259
			dev_warn(&pdev->dev, "could not get baud clock: %ld\n",
1260
				 PTR_ERR(ssi_private->baudclk));
1261 1262 1263
		else
			clk_prepare_enable(ssi_private->baudclk);

1264 1265 1266 1267
		/*
		 * We have burstsize be "fifo_depth - 2" to match the SSI
		 * watermark setting in fsl_ssi_startup().
		 */
1268
		ssi_private->dma_params_tx.maxburst =
1269
			ssi_private->fifo_depth - 2;
1270
		ssi_private->dma_params_rx.maxburst =
1271
			ssi_private->fifo_depth - 2;
1272
		ssi_private->dma_params_tx.addr =
1273
			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
1274
		ssi_private->dma_params_rx.addr =
1275
			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
1276 1277 1278 1279
		ssi_private->dma_params_tx.filter_data =
			&ssi_private->filter_data_tx;
		ssi_private->dma_params_rx.filter_data =
			&ssi_private->filter_data_rx;
1280 1281 1282 1283 1284 1285 1286 1287
		if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
				ssi_private->use_dma) {
			/*
			 * FIXME: This is a temporary solution until all
			 * necessary dma drivers support the generic dma
			 * bindings.
			 */
			ret = of_property_read_u32_array(pdev->dev.of_node,
1288
					"fsl,ssi-dma-events", dma_events, 2);
1289 1290 1291 1292
			if (ret && ssi_private->use_dma) {
				dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
				goto error_clk;
			}
1293
		}
1294 1295 1296 1297

		shared = of_device_is_compatible(of_get_parent(np),
			    "fsl,spba-bus");

1298
		imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1299
			dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1300
		imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1301
			dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1302 1303 1304 1305 1306
	} else if (ssi_private->use_dma) {
		/* The 'name' should not have any slashes in it. */
		ret = devm_request_irq(&pdev->dev, ssi_private->irq,
					fsl_ssi_isr, 0, ssi_private->name,
					ssi_private);
1307
		ssi_private->irq_stats = true;
1308 1309 1310 1311 1312
		if (ret < 0) {
			dev_err(&pdev->dev, "could not claim irq %u\n",
					ssi_private->irq);
			goto error_irqmap;
		}
1313 1314
	}

1315
	/* Register with ASoC */
1316
	dev_set_drvdata(&pdev->dev, ssi_private);
M
Mark Brown 已提交
1317

1318 1319
	ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
					 &ssi_private->cpu_dai_drv, 1);
1320
	if (ret) {
1321
		dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1322
		goto error_dev;
1323 1324
	}

1325 1326 1327 1328
	ret = fsl_ssi_debugfs_create(ssi_private, &pdev->dev);
	if (ret)
		goto error_dbgfs;

1329
	if (ssi_private->ssi_on_imx) {
1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347
		if (!ssi_private->use_dma) {

			/*
			 * Some boards use an incompatible codec. To get it
			 * working, we are using imx-fiq-pcm-audio, that
			 * can handle those codecs. DMA is not possible in this
			 * situation.
			 */

			ssi_private->fiq_params.irq = ssi_private->irq;
			ssi_private->fiq_params.base = ssi_private->ssi;
			ssi_private->fiq_params.dma_params_rx =
				&ssi_private->dma_params_rx;
			ssi_private->fiq_params.dma_params_tx =
				&ssi_private->dma_params_tx;

			ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
			if (ret)
1348
				goto error_pcm;
1349 1350 1351
		} else {
			ret = imx_pcm_dma_init(pdev);
			if (ret)
1352
				goto error_pcm;
1353
		}
1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365
	}

	/*
	 * If codec-handle property is missing from SSI node, we assume
	 * that the machine driver uses new binding which does not require
	 * SSI driver to trigger machine driver's probe.
	 */
	if (!of_get_property(np, "codec-handle", NULL)) {
		ssi_private->new_binding = true;
		goto done;
	}

1366
	/* Trigger the machine driver's probe function.  The platform driver
1367
	 * name of the machine driver is taken from /compatible property of the
1368 1369 1370
	 * device tree.  We also pass the address of the CPU DAI driver
	 * structure.
	 */
1371 1372
	sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
	/* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1373 1374 1375 1376 1377 1378 1379
	p = strrchr(sprop, ',');
	if (p)
		sprop = p + 1;
	snprintf(name, sizeof(name), "snd-soc-%s", sprop);
	make_lowercase(name);

	ssi_private->pdev =
1380
		platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1381 1382
	if (IS_ERR(ssi_private->pdev)) {
		ret = PTR_ERR(ssi_private->pdev);
1383
		dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1384
		goto error_dai;
M
Mark Brown 已提交
1385
	}
1386

1387
done:
1388 1389 1390
	if (ssi_private->imx_ac97)
		fsl_ssi_ac97_init();

1391
	return 0;
1392

1393
error_dai:
1394 1395 1396 1397
	if (ssi_private->ssi_on_imx && !ssi_private->use_dma)
		imx_pcm_fiq_exit(pdev);

error_pcm:
1398 1399 1400
	fsl_ssi_debugfs_remove(ssi_private);

error_dbgfs:
1401
	snd_soc_unregister_component(&pdev->dev);
1402 1403 1404 1405

error_dev:
	device_remove_file(&pdev->dev, dev_attr);

1406
error_clk:
1407 1408 1409
	if (ssi_private->ssi_on_imx) {
		if (!IS_ERR(ssi_private->baudclk))
			clk_disable_unprepare(ssi_private->baudclk);
1410
		clk_disable_unprepare(ssi_private->clk);
1411
	}
1412 1413

error_irqmap:
1414 1415
	if (ssi_private->irq_stats)
		irq_dispose_mapping(ssi_private->irq);
1416

1417
	return ret;
1418 1419
}

1420
static int fsl_ssi_remove(struct platform_device *pdev)
1421
{
1422
	struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1423

1424 1425
	fsl_ssi_debugfs_remove(ssi_private);

1426 1427
	if (!ssi_private->new_binding)
		platform_device_unregister(ssi_private->pdev);
1428
	snd_soc_unregister_component(&pdev->dev);
1429 1430 1431
	if (ssi_private->ssi_on_imx) {
		if (!IS_ERR(ssi_private->baudclk))
			clk_disable_unprepare(ssi_private->baudclk);
1432
		clk_disable_unprepare(ssi_private->clk);
1433
	}
1434 1435
	if (ssi_private->irq_stats)
		irq_dispose_mapping(ssi_private->irq);
1436 1437

	return 0;
1438
}
1439

1440
static struct platform_driver fsl_ssi_driver = {
1441 1442 1443 1444 1445 1446 1447 1448
	.driver = {
		.name = "fsl-ssi-dai",
		.owner = THIS_MODULE,
		.of_match_table = fsl_ssi_ids,
	},
	.probe = fsl_ssi_probe,
	.remove = fsl_ssi_remove,
};
1449

1450
module_platform_driver(fsl_ssi_driver);
1451

1452
MODULE_ALIAS("platform:fsl-ssi-dai");
1453 1454
MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1455
MODULE_LICENSE("GPL v2");