Kconfig 56.9 KB
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config ARM
	bool
	default y
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	select HAVE_AOUT
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	select HAVE_DMA_API_DEBUG
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	select HAVE_IDE
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	select HAVE_MEMBLOCK
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	select RTC_LIB
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	select SYS_SUPPORTS_APM_EMULATION
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	select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
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	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
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	select HAVE_ARCH_KGDB
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	select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
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	select HAVE_KRETPROBES if (HAVE_KPROBES)
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	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
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	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
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	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
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	select HAVE_GENERIC_DMA_COHERENT
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	select HAVE_KERNEL_GZIP
	select HAVE_KERNEL_LZO
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	select HAVE_KERNEL_LZMA
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	select HAVE_IRQ_WORK
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	select HAVE_PERF_EVENTS
	select PERF_USE_VMALLOC
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	select HAVE_REGS_AND_STACK_ACCESS_API
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	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
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	select HAVE_C_RECORDMCOUNT
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	select HAVE_GENERIC_HARDIRQS
	select HAVE_SPARSE_IRQ
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	help
	  The ARM series is a line of low-power-consumption RISC chip designs
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	  licensed by ARM Ltd and targeted at embedded applications and
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	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
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	  manufactured, but legacy ARM-based PC hardware remains popular in
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	  Europe.  There is an ARM Linux project with a web page at
	  <http://www.arm.linux.org.uk/>.

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config HAVE_PWM
	bool

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config MIGHT_HAVE_PCI
	bool

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config SYS_SUPPORTS_APM_EMULATION
	bool

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config HAVE_SCHED_CLOCK
	bool

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config GENERIC_GPIO
	bool

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config ARCH_USES_GETTIMEOFFSET
	bool
	default n
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config GENERIC_CLOCKEVENTS
	bool

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config GENERIC_CLOCKEVENTS_BROADCAST
	bool
	depends on GENERIC_CLOCKEVENTS
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	default y if SMP
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config KTIME_SCALAR
	bool
	default y

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config HAVE_TCM
	bool
	select GENERIC_ALLOCATOR

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config HAVE_PROC_CPU
	bool

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config NO_IOPORT
	bool

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config EISA
	bool
	---help---
	  The Extended Industry Standard Architecture (EISA) bus was
	  developed as an open alternative to the IBM MicroChannel bus.

	  The EISA bus provided some of the features of the IBM MicroChannel
	  bus while maintaining backward compatibility with cards made for
	  the older ISA bus.  The EISA bus saw limited use between 1988 and
	  1995 when it was made obsolete by the PCI bus.

	  Say Y here if you are building a kernel for an EISA-based machine.

	  Otherwise, say N.

config SBUS
	bool

config MCA
	bool
	help
	  MicroChannel Architecture is found in some IBM PS/2 machines and
	  laptops.  It is a bus system similar to PCI or ISA. See
	  <file:Documentation/mca.txt> (and especially the web page given
	  there) before attempting to build an MCA bus kernel.

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config STACKTRACE_SUPPORT
	bool
	default y

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config HAVE_LATENCYTOP_SUPPORT
	bool
	depends on !SMP
	default y

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config LOCKDEP_SUPPORT
	bool
	default y

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config TRACE_IRQFLAGS_SUPPORT
	bool
	default y

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config HARDIRQS_SW_RESEND
	bool
	default y

config GENERIC_IRQ_PROBE
	bool
	default y

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config GENERIC_LOCKBREAK
	bool
	default y
	depends on SMP && PREEMPT

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config RWSEM_GENERIC_SPINLOCK
	bool
	default y

config RWSEM_XCHGADD_ALGORITHM
	bool

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config ARCH_HAS_ILOG2_U32
	bool

config ARCH_HAS_ILOG2_U64
	bool

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config ARCH_HAS_CPUFREQ
	bool
	help
	  Internal node to signify that the ARCH has CPUFREQ support
	  and that the relevant menu configurations are displayed for
	  it.

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config ARCH_HAS_CPU_IDLE_WAIT
       def_bool y

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config GENERIC_HWEIGHT
	bool
	default y

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config GENERIC_CALIBRATE_DELAY
	bool
	default y

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config ARCH_MAY_HAVE_PC_FDC
	bool

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config ZONE_DMA
	bool

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config NEED_DMA_MAP_STATE
       def_bool y

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config GENERIC_ISA_DMA
	bool

config FIQ
	bool

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config ARCH_MTD_XIP
	bool

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config VECTORS_BASE
	hex
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	default 0xffff0000 if MMU || CPU_HIGH_VECTOR
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	default DRAM_BASE if REMAP_VECTORS_TO_RAM
	default 0x00000000
	help
	  The base address of exception vectors.

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config ARM_PATCH_PHYS_VIRT
	bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
	depends on EXPERIMENTAL
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	depends on !XIP_KERNEL && MMU
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	depends on !ARCH_REALVIEW || !SPARSEMEM
	help
	  Patch phys-to-virt translation functions at runtime according to
	  the position of the kernel in system memory.

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	  This can only be used with non-XIP with MMU kernels where
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	  the base of physical memory is at a 16MB boundary.

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config ARM_PATCH_PHYS_VIRT_16BIT
	def_bool y
	depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM

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source "init/Kconfig"

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source "kernel/Kconfig.freezer"

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menu "System Type"

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config MMU
	bool "MMU-based Paged Memory Management Support"
	default y
	help
	  Select if you want MMU-based virtualised addressing space
	  support by paged memory management. If unsure, say 'Y'.

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#
# The "ARM system type" choice list is ordered alphabetically by option
# text.  Please add new entries in the option alphabetic order.
#
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choice
	prompt "ARM system type"
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	default ARCH_VERSATILE
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config ARCH_INTEGRATOR
	bool "ARM Ltd. Integrator family"
	select ARM_AMBA
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	select ARCH_HAS_CPUFREQ
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	select CLKDEV_LOOKUP
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	select ICST
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	select GENERIC_CLOCKEVENTS
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	select PLAT_VERSATILE
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	help
	  Support for ARM's Integrator platform.

config ARCH_REALVIEW
	bool "ARM Ltd. RealView family"
	select ARM_AMBA
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	select CLKDEV_LOOKUP
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	select HAVE_SCHED_CLOCK
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	select ICST
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	select GENERIC_CLOCKEVENTS
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	select ARCH_WANT_OPTIONAL_GPIOLIB
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	select PLAT_VERSATILE
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	select ARM_TIMER_SP804
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	select GPIO_PL061 if GPIOLIB
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	help
	  This enables support for ARM Ltd RealView boards.

config ARCH_VERSATILE
	bool "ARM Ltd. Versatile family"
	select ARM_AMBA
	select ARM_VIC
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	select CLKDEV_LOOKUP
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	select HAVE_SCHED_CLOCK
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	select ICST
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	select GENERIC_CLOCKEVENTS
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	select ARCH_WANT_OPTIONAL_GPIOLIB
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	select PLAT_VERSATILE
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	select ARM_TIMER_SP804
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	help
	  This enables support for ARM Ltd Versatile board.

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config ARCH_VEXPRESS
	bool "ARM Ltd. Versatile Express family"
	select ARCH_WANT_OPTIONAL_GPIOLIB
	select ARM_AMBA
	select ARM_TIMER_SP804
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	select CLKDEV_LOOKUP
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	select GENERIC_CLOCKEVENTS
	select HAVE_CLK
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	select HAVE_SCHED_CLOCK
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	select ICST
	select PLAT_VERSATILE
	help
	  This enables support for the ARM Ltd Versatile Express boards.

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config ARCH_AT91
	bool "Atmel AT91"
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	select ARCH_REQUIRE_GPIOLIB
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	select HAVE_CLK
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	help
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	  This enables support for systems based on the Atmel AT91RM9200,
	  AT91SAM9 and AT91CAP9 processors.
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config ARCH_BCMRING
	bool "Broadcom BCMRING"
	depends on MMU
	select CPU_V6
	select ARM_AMBA
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	select CLKDEV_LOOKUP
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	select GENERIC_CLOCKEVENTS
	select ARCH_WANT_OPTIONAL_GPIOLIB
	help
	  Support for Broadcom's BCMRing platform.

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config ARCH_CLPS711X
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	bool "Cirrus Logic CLPS711x/EP721x-based"
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	select CPU_ARM720T
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	select ARCH_USES_GETTIMEOFFSET
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	help
	  Support for Cirrus Logic 711x/721x based boards.
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config ARCH_CNS3XXX
	bool "Cavium Networks CNS3XXX family"
	select CPU_V6
	select GENERIC_CLOCKEVENTS
	select ARM_GIC
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	select MIGHT_HAVE_PCI
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	select PCI_DOMAINS if PCI
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	help
	  Support for Cavium Networks CNS3XXX platform.

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config ARCH_GEMINI
	bool "Cortina Systems Gemini"
	select CPU_FA526
	select ARCH_REQUIRE_GPIOLIB
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	select ARCH_USES_GETTIMEOFFSET
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	help
	  Support for the Cortina Systems Gemini family SoCs

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config ARCH_EBSA110
	bool "EBSA-110"
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	select CPU_SA110
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	select ISA
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	select NO_IOPORT
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	select ARCH_USES_GETTIMEOFFSET
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	help
	  This is an evaluation board for the StrongARM processor available
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	  from Digital. It has limited hardware on-board, including an
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	  Ethernet interface, two PCMCIA sockets, two serial ports and a
	  parallel port.

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config ARCH_EP93XX
	bool "EP93xx-based"
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	select CPU_ARM920T
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	select ARM_AMBA
	select ARM_VIC
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	select CLKDEV_LOOKUP
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	select ARCH_REQUIRE_GPIOLIB
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	select ARCH_HAS_HOLES_MEMORYMODEL
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	select ARCH_USES_GETTIMEOFFSET
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	help
	  This enables support for the Cirrus EP93xx series of CPUs.

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config ARCH_FOOTBRIDGE
	bool "FootBridge"
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	select CPU_SA110
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	select FOOTBRIDGE
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	select GENERIC_CLOCKEVENTS
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	help
	  Support for systems based on the DC21285 companion chip
	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
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config ARCH_MXC
	bool "Freescale MXC/iMX-based"
	select GENERIC_CLOCKEVENTS
	select ARCH_REQUIRE_GPIOLIB
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	select CLKDEV_LOOKUP
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	select HAVE_SCHED_CLOCK
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	help
	  Support for Freescale MXC/iMX-based family of processors

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config ARCH_MXS
	bool "Freescale MXS-based"
	select GENERIC_CLOCKEVENTS
	select ARCH_REQUIRE_GPIOLIB
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	select CLKDEV_LOOKUP
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	help
	  Support for Freescale MXS-based family of processors

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config ARCH_STMP3XXX
	bool "Freescale STMP3xxx"
	select CPU_ARM926T
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	select CLKDEV_LOOKUP
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	select ARCH_REQUIRE_GPIOLIB
	select GENERIC_CLOCKEVENTS
	select USB_ARCH_HAS_EHCI
	help
	  Support for systems based on the Freescale 3xxx CPUs.

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config ARCH_NETX
	bool "Hilscher NetX based"
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	select CPU_ARM926T
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	select ARM_VIC
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	select GENERIC_CLOCKEVENTS
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	help
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	  This enables support for systems based on the Hilscher NetX Soc

config ARCH_H720X
	bool "Hynix HMS720x-based"
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	select CPU_ARM720T
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	select ISA_DMA_API
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	select ARCH_USES_GETTIMEOFFSET
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	help
	  This enables support for systems based on the Hynix HMS720x

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config ARCH_IOP13XX
	bool "IOP13xx-based"
	depends on MMU
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	select CPU_XSC3
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	select PLAT_IOP
	select PCI
	select ARCH_SUPPORTS_MSI
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	select VMSPLIT_1G
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	help
	  Support for Intel's IOP13XX (XScale) family of processors.

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config ARCH_IOP32X
	bool "IOP32x-based"
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	depends on MMU
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	select CPU_XSCALE
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	select PLAT_IOP
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	select PCI
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	select ARCH_REQUIRE_GPIOLIB
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	help
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	  Support for Intel's 80219 and IOP32X (XScale) family of
	  processors.

config ARCH_IOP33X
	bool "IOP33x-based"
	depends on MMU
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	select CPU_XSCALE
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	select PLAT_IOP
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	select PCI
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	select ARCH_REQUIRE_GPIOLIB
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	help
	  Support for Intel's IOP33X (XScale) family of processors.
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config ARCH_IXP23XX
 	bool "IXP23XX-based"
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	depends on MMU
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	select CPU_XSC3
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 	select PCI
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	select ARCH_USES_GETTIMEOFFSET
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	help
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	  Support for Intel's IXP23xx (XScale) family of processors.
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config ARCH_IXP2000
	bool "IXP2400/2800-based"
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	depends on MMU
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	select CPU_XSCALE
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	select PCI
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	select ARCH_USES_GETTIMEOFFSET
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	help
	  Support for Intel's IXP2400/2800 (XScale) family of processors.
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config ARCH_IXP4XX
	bool "IXP4xx-based"
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	depends on MMU
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	select CPU_XSCALE
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	select GENERIC_GPIO
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	select GENERIC_CLOCKEVENTS
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	select HAVE_SCHED_CLOCK
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	select MIGHT_HAVE_PCI
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	select DMABOUNCE if PCI
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	help
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	  Support for Intel's IXP4XX (XScale) family of processors.
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config ARCH_DOVE
	bool "Marvell Dove"
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	select CPU_V6K
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	select PCI
	select ARCH_REQUIRE_GPIOLIB
	select GENERIC_CLOCKEVENTS
	select PLAT_ORION
	help
	  Support for the Marvell Dove SoC 88AP510

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config ARCH_KIRKWOOD
	bool "Marvell Kirkwood"
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	select CPU_FEROCEON
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	select PCI
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	select ARCH_REQUIRE_GPIOLIB
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	select GENERIC_CLOCKEVENTS
	select PLAT_ORION
	help
	  Support for the following Marvell Kirkwood series SoCs:
	  88F6180, 88F6192 and 88F6281.

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config ARCH_LOKI
	bool "Marvell Loki (88RC8480)"
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	select CPU_FEROCEON
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	select GENERIC_CLOCKEVENTS
	select PLAT_ORION
	help
	  Support for the Marvell Loki (88RC8480) SoC.

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config ARCH_LPC32XX
	bool "NXP LPC32XX"
	select CPU_ARM926T
	select ARCH_REQUIRE_GPIOLIB
	select HAVE_IDE
	select ARM_AMBA
	select USB_ARCH_HAS_OHCI
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	select CLKDEV_LOOKUP
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	select GENERIC_TIME
	select GENERIC_CLOCKEVENTS
	help
	  Support for the NXP LPC32XX family of processors

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config ARCH_MV78XX0
	bool "Marvell MV78xx0"
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	select CPU_FEROCEON
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	select PCI
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	select ARCH_REQUIRE_GPIOLIB
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	select GENERIC_CLOCKEVENTS
	select PLAT_ORION
	help
	  Support for the following Marvell MV78xx0 series SoCs:
	  MV781x0, MV782x0.

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config ARCH_ORION5X
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	bool "Marvell Orion"
	depends on MMU
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	select CPU_FEROCEON
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	select PCI
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	select ARCH_REQUIRE_GPIOLIB
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	select GENERIC_CLOCKEVENTS
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	select PLAT_ORION
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	help
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	  Support for the following Marvell Orion 5x series SoCs:
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	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
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	  Orion-2 (5281), Orion-1-90 (6183).
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config ARCH_MMP
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	bool "Marvell PXA168/910/MMP2"
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	depends on MMU
	select ARCH_REQUIRE_GPIOLIB
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	select CLKDEV_LOOKUP
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	select GENERIC_CLOCKEVENTS
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	select HAVE_SCHED_CLOCK
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	select TICK_ONESHOT
	select PLAT_PXA
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	select SPARSE_IRQ
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	help
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	  Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
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config ARCH_KS8695
	bool "Micrel/Kendin KS8695"
	select CPU_ARM922T
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	select ARCH_REQUIRE_GPIOLIB
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	select ARCH_USES_GETTIMEOFFSET
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	help
	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
	  System-on-Chip devices.

config ARCH_NS9XXX
	bool "NetSilicon NS9xxx"
	select CPU_ARM926T
	select GENERIC_GPIO
	select GENERIC_CLOCKEVENTS
	select HAVE_CLK
	help
	  Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
	  System.

	  <http://www.digi.com/products/microprocessors/index.jsp>

config ARCH_W90X900
	bool "Nuvoton W90X900 CPU"
	select CPU_ARM926T
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	select ARCH_REQUIRE_GPIOLIB
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	select CLKDEV_LOOKUP
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	select GENERIC_CLOCKEVENTS
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	help
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	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
	  At present, the w90x900 has been renamed nuc900, regarding
	  the ARM series product line, you can login the following
	  link address to know more.

	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
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config ARCH_NUC93X
	bool "Nuvoton NUC93X CPU"
	select CPU_ARM926T
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	select CLKDEV_LOOKUP
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	help
	  Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
	  low-power and high performance MPEG-4/JPEG multimedia controller chip.

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config ARCH_TEGRA
	bool "NVIDIA Tegra"
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	select CLKDEV_LOOKUP
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	select GENERIC_TIME
	select GENERIC_CLOCKEVENTS
	select GENERIC_GPIO
	select HAVE_CLK
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	select HAVE_SCHED_CLOCK
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	select ARCH_HAS_BARRIERS if CACHE_L2X0
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	select ARCH_HAS_CPUFREQ
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	help
	  This enables support for NVIDIA Tegra based systems (Tegra APX,
	  Tegra 6xx and Tegra 2 series).

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config ARCH_PNX4008
	bool "Philips Nexperia PNX4008 Mobile"
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	select CPU_ARM926T
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	select CLKDEV_LOOKUP
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	select ARCH_USES_GETTIMEOFFSET
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	help
	  This enables support for Philips PNX4008 mobile platform.

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config ARCH_PXA
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	bool "PXA2xx/PXA3xx-based"
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	depends on MMU
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	select ARCH_MTD_XIP
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	select ARCH_HAS_CPUFREQ
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	select CLKDEV_LOOKUP
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	select ARCH_REQUIRE_GPIOLIB
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	select GENERIC_CLOCKEVENTS
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	select HAVE_SCHED_CLOCK
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	select TICK_ONESHOT
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	select PLAT_PXA
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	select SPARSE_IRQ
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	help
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	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
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config ARCH_MSM
	bool "Qualcomm MSM"
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	select HAVE_CLK
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	select GENERIC_CLOCKEVENTS
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	select ARCH_REQUIRE_GPIOLIB
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	select CLKDEV_LOOKUP
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	help
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	  Support for Qualcomm MSM/QSD based systems.  This runs on the
	  apps processor of the MSM/QSD and depends on a shared memory
	  interface to the modem processor which runs the baseband
	  stack and controls some vital subsystems
	  (clock and power control, etc).
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config ARCH_SHMOBILE
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	bool "Renesas SH-Mobile / R-Mobile"
	select HAVE_CLK
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	select CLKDEV_LOOKUP
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	select GENERIC_CLOCKEVENTS
	select NO_IOPORT
	select SPARSE_IRQ
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	select MULTI_IRQ_HANDLER
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	help
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	  Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
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config ARCH_RPC
	bool "RiscPC"
	select ARCH_ACORN
	select FIQ
	select TIMER_ACORN
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	select ARCH_MAY_HAVE_PC_FDC
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	select HAVE_PATA_PLATFORM
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	select ISA_DMA_API
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	select NO_IOPORT
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	select ARCH_SPARSEMEM_ENABLE
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	select ARCH_USES_GETTIMEOFFSET
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	help
	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
	  CD-ROM interface, serial and parallel port, and the floppy drive.

config ARCH_SA1100
	bool "SA1100-based"
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	select CPU_SA1100
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	select ISA
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	select ARCH_SPARSEMEM_ENABLE
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	select ARCH_MTD_XIP
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	select ARCH_HAS_CPUFREQ
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	select CPU_FREQ
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	select GENERIC_CLOCKEVENTS
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	select HAVE_CLK
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	select HAVE_SCHED_CLOCK
675
	select TICK_ONESHOT
676
	select ARCH_REQUIRE_GPIOLIB
677 678
	help
	  Support for StrongARM 11x0 based boards.
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config ARCH_S3C2410
681
	bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
682
	select GENERIC_GPIO
683
	select ARCH_HAS_CPUFREQ
684
	select HAVE_CLK
685
	select ARCH_USES_GETTIMEOFFSET
686
	select HAVE_S3C2410_I2C if I2C
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	help
	  Samsung S3C2410X CPU based systems, such as the Simtec Electronics
	  BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
690
	  the Samsung SMDK2410 development board (and derivatives).
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692 693 694 695
	  Note, the S3C2416 and the S3C2450 are so close that they even share
	  the same SoC ID code. This means that there is no seperate machine
	  directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.

696 697
config ARCH_S3C64XX
	bool "Samsung S3C64XX"
698
	select PLAT_SAMSUNG
699 700
	select CPU_V6
	select ARM_VIC
701
	select HAVE_CLK
702
	select NO_IOPORT
703
	select ARCH_USES_GETTIMEOFFSET
704
	select ARCH_HAS_CPUFREQ
705 706 707 708 709 710 711 712 713 714 715
	select ARCH_REQUIRE_GPIOLIB
	select SAMSUNG_CLKSRC
	select SAMSUNG_IRQ_VIC_TIMER
	select SAMSUNG_IRQ_UART
	select S3C_GPIO_TRACK
	select S3C_GPIO_PULL_UPDOWN
	select S3C_GPIO_CFG_S3C24XX
	select S3C_GPIO_CFG_S3C64XX
	select S3C_DEV_NAND
	select USB_ARCH_HAS_OHCI
	select SAMSUNG_GPIOLIB_4BIT
716
	select HAVE_S3C2410_I2C if I2C
717
	select HAVE_S3C2410_WATCHDOG if WATCHDOG
718 719 720
	help
	  Samsung S3C64XX series based systems

721 722
config ARCH_S5P64X0
	bool "Samsung S5P6440 S5P6450"
723 724 725
	select CPU_V6
	select GENERIC_GPIO
	select HAVE_CLK
726
	select HAVE_S3C2410_WATCHDOG if WATCHDOG
727 728
	select GENERIC_CLOCKEVENTS
	select HAVE_SCHED_CLOCK
729
	select HAVE_S3C2410_I2C if I2C
730
	select HAVE_S3C_RTC if RTC_CLASS
731
	help
732 733
	  Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
	  SMDK6450.
734

735 736 737 738 739
config ARCH_S5P6442
	bool "Samsung S5P6442"
	select CPU_V6
	select GENERIC_GPIO
	select HAVE_CLK
740
	select ARCH_USES_GETTIMEOFFSET
741
	select HAVE_S3C2410_WATCHDOG if WATCHDOG
742 743 744
	help
	  Samsung S5P6442 CPU based systems

745 746
config ARCH_S5PC100
	bool "Samsung S5PC100"
747 748 749
	select GENERIC_GPIO
	select HAVE_CLK
	select CPU_V7
750
	select ARM_L1_CACHE_SHIFT_6
751
	select ARCH_USES_GETTIMEOFFSET
752
	select HAVE_S3C2410_I2C if I2C
753
	select HAVE_S3C_RTC if RTC_CLASS
754
	select HAVE_S3C2410_WATCHDOG if WATCHDOG
755
	help
756
	  Samsung S5PC100 series based systems
757

758 759 760
config ARCH_S5PV210
	bool "Samsung S5PV210/S5PC110"
	select CPU_V7
761
	select ARCH_SPARSEMEM_ENABLE
762 763 764
	select GENERIC_GPIO
	select HAVE_CLK
	select ARM_L1_CACHE_SHIFT_6
765
	select ARCH_HAS_CPUFREQ
766 767
	select GENERIC_CLOCKEVENTS
	select HAVE_SCHED_CLOCK
768
	select HAVE_S3C2410_I2C if I2C
769
	select HAVE_S3C_RTC if RTC_CLASS
770
	select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 772 773
	help
	  Samsung S5PV210/S5PC110 series based systems

774 775
config ARCH_EXYNOS4
	bool "Samsung EXYNOS4"
776
	select CPU_V7
777
	select ARCH_SPARSEMEM_ENABLE
778 779
	select GENERIC_GPIO
	select HAVE_CLK
780
	select ARCH_HAS_CPUFREQ
781
	select GENERIC_CLOCKEVENTS
782
	select HAVE_S3C_RTC if RTC_CLASS
783
	select HAVE_S3C2410_I2C if I2C
784
	select HAVE_S3C2410_WATCHDOG if WATCHDOG
785
	help
786
	  Samsung EXYNOS4 series based systems
787

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config ARCH_SHARK
	bool "Shark"
790
	select CPU_SA110
791 792
	select ISA
	select ISA_DMA
793
	select ZONE_DMA
794
	select PCI
795
	select ARCH_USES_GETTIMEOFFSET
796 797 798
	help
	  Support for the StrongARM based Digital DNARD machine, also known
	  as "Shark" (<http://www.shark-linux.de/shark.html>).
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800 801 802 803
config ARCH_TCC_926
	bool "Telechips TCC ARM926-based systems"
	select CPU_ARM926T
	select HAVE_CLK
804
	select CLKDEV_LOOKUP
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	select GENERIC_CLOCKEVENTS
	help
	  Support for Telechips TCC ARM926-based systems.

809 810 811 812
config ARCH_U300
	bool "ST-Ericsson U300 Series"
	depends on MMU
	select CPU_ARM926T
813
	select HAVE_SCHED_CLOCK
814
	select HAVE_TCM
815 816 817
	select ARM_AMBA
	select ARM_VIC
	select GENERIC_CLOCKEVENTS
818
	select CLKDEV_LOOKUP
819 820 821 822
	select GENERIC_GPIO
	help
	  Support for ST-Ericsson U300 series mobile platforms.

823 824 825 826 827
config ARCH_U8500
	bool "ST-Ericsson U8500 Series"
	select CPU_V7
	select ARM_AMBA
	select GENERIC_CLOCKEVENTS
828
	select CLKDEV_LOOKUP
829
	select ARCH_REQUIRE_GPIOLIB
830
	select ARCH_HAS_CPUFREQ
831 832 833 834 835 836 837 838
	help
	  Support for ST-Ericsson's Ux500 architecture

config ARCH_NOMADIK
	bool "STMicroelectronics Nomadik"
	select ARM_AMBA
	select ARM_VIC
	select CPU_ARM926T
839
	select CLKDEV_LOOKUP
840 841 842 843 844
	select GENERIC_CLOCKEVENTS
	select ARCH_REQUIRE_GPIOLIB
	help
	  Support for the Nomadik platform by ST-Ericsson

845 846 847
config ARCH_DAVINCI
	bool "TI DaVinci"
	select GENERIC_CLOCKEVENTS
848
	select ARCH_REQUIRE_GPIOLIB
849
	select ZONE_DMA
850
	select HAVE_IDE
851
	select CLKDEV_LOOKUP
852
	select GENERIC_ALLOCATOR
853
	select ARCH_HAS_HOLES_MEMORYMODEL
854 855 856
	help
	  Support for TI's DaVinci platform.

857 858
config ARCH_OMAP
	bool "TI OMAP"
859
	select HAVE_CLK
860
	select ARCH_REQUIRE_GPIOLIB
861
	select ARCH_HAS_CPUFREQ
862
	select GENERIC_CLOCKEVENTS
863
	select HAVE_SCHED_CLOCK
864
	select ARCH_HAS_HOLES_MEMORYMODEL
865
	help
866
	  Support for TI's OMAP platform (OMAP1/2/3/4).
867

868 869 870 871
config PLAT_SPEAR
	bool "ST SPEAr"
	select ARM_AMBA
	select ARCH_REQUIRE_GPIOLIB
872
	select CLKDEV_LOOKUP
873 874 875 876 877
	select GENERIC_CLOCKEVENTS
	select HAVE_CLK
	help
	  Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).

878 879 880 881 882 883 884 885 886 887
config ARCH_VT8500
	bool "VIA/WonderMedia 85xx"
	select CPU_ARM926T
	select GENERIC_GPIO
	select ARCH_HAS_CPUFREQ
	select GENERIC_CLOCKEVENTS
	select ARCH_REQUIRE_GPIOLIB
	select HAVE_PWM
	help
	  Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
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endchoice

890 891 892 893 894
#
# This is sorted alphabetically by mach-* pathname.  However, plat-*
# Kconfigs may be included either alphabetically (according to the
# plat- suffix) or along side the corresponding mach-* source.
#
895 896 897 898
source "arch/arm/mach-at91/Kconfig"

source "arch/arm/mach-bcmring/Kconfig"

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source "arch/arm/mach-clps711x/Kconfig"

901 902
source "arch/arm/mach-cns3xxx/Kconfig"

903 904 905 906
source "arch/arm/mach-davinci/Kconfig"

source "arch/arm/mach-dove/Kconfig"

907 908
source "arch/arm/mach-ep93xx/Kconfig"

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source "arch/arm/mach-footbridge/Kconfig"

911 912
source "arch/arm/mach-gemini/Kconfig"

913 914
source "arch/arm/mach-h720x/Kconfig"

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source "arch/arm/mach-integrator/Kconfig"

917 918 919
source "arch/arm/mach-iop32x/Kconfig"

source "arch/arm/mach-iop33x/Kconfig"
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921 922
source "arch/arm/mach-iop13xx/Kconfig"

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923 924 925 926
source "arch/arm/mach-ixp4xx/Kconfig"

source "arch/arm/mach-ixp2000/Kconfig"

927 928
source "arch/arm/mach-ixp23xx/Kconfig"

929 930 931 932
source "arch/arm/mach-kirkwood/Kconfig"

source "arch/arm/mach-ks8695/Kconfig"

933 934
source "arch/arm/mach-loki/Kconfig"

935 936
source "arch/arm/mach-lpc32xx/Kconfig"

937 938
source "arch/arm/mach-msm/Kconfig"

939 940
source "arch/arm/mach-mv78xx0/Kconfig"

941
source "arch/arm/plat-mxc/Kconfig"
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943 944
source "arch/arm/mach-mxs/Kconfig"

945
source "arch/arm/mach-netx/Kconfig"
946

947 948 949 950
source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/plat-nomadik/Kconfig"

source "arch/arm/mach-ns9xxx/Kconfig"
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952
source "arch/arm/mach-nuc93x/Kconfig"
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953

954 955 956
source "arch/arm/plat-omap/Kconfig"

source "arch/arm/mach-omap1/Kconfig"
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958 959
source "arch/arm/mach-omap2/Kconfig"

960
source "arch/arm/mach-orion5x/Kconfig"
961

962 963
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"
964

965 966 967 968 969
source "arch/arm/mach-mmp/Kconfig"

source "arch/arm/mach-realview/Kconfig"

source "arch/arm/mach-sa1100/Kconfig"
970

971
source "arch/arm/plat-samsung/Kconfig"
972
source "arch/arm/plat-s3c24xx/Kconfig"
973
source "arch/arm/plat-s5p/Kconfig"
974

975
source "arch/arm/plat-spear/Kconfig"
976

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source "arch/arm/plat-tcc/Kconfig"

979 980
if ARCH_S3C2410
source "arch/arm/mach-s3c2400/Kconfig"
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source "arch/arm/mach-s3c2410/Kconfig"
982
source "arch/arm/mach-s3c2412/Kconfig"
983
source "arch/arm/mach-s3c2416/Kconfig"
984
source "arch/arm/mach-s3c2440/Kconfig"
985
source "arch/arm/mach-s3c2443/Kconfig"
986
endif
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988
if ARCH_S3C64XX
989
source "arch/arm/mach-s3c64xx/Kconfig"
990 991
endif

992
source "arch/arm/mach-s5p64x0/Kconfig"
993

994
source "arch/arm/mach-s5p6442/Kconfig"
995

996 997
source "arch/arm/mach-s5pc100/Kconfig"

998 999
source "arch/arm/mach-s5pv210/Kconfig"

1000
source "arch/arm/mach-exynos4/Kconfig"
1001

1002
source "arch/arm/mach-shmobile/Kconfig"
1003

1004
source "arch/arm/plat-stmp3xxx/Kconfig"
1005

1006 1007
source "arch/arm/mach-tegra/Kconfig"

1008
source "arch/arm/mach-u300/Kconfig"
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1010
source "arch/arm/mach-ux500/Kconfig"
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1011 1012 1013

source "arch/arm/mach-versatile/Kconfig"

1014 1015
source "arch/arm/mach-vexpress/Kconfig"

1016 1017
source "arch/arm/mach-vt8500/Kconfig"

1018 1019
source "arch/arm/mach-w90x900/Kconfig"

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1020 1021 1022 1023
# Definitions to make life easier
config ARCH_ACORN
	bool

1024 1025
config PLAT_IOP
	bool
1026
	select GENERIC_CLOCKEVENTS
1027
	select HAVE_SCHED_CLOCK
1028

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1029 1030
config PLAT_ORION
	bool
1031
	select HAVE_SCHED_CLOCK
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1032

1033 1034 1035
config PLAT_PXA
	bool

1036 1037 1038
config PLAT_VERSATILE
	bool

1039 1040 1041
config ARM_TIMER_SP804
	bool

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1042 1043
source arch/arm/mm/Kconfig

1044 1045
config IWMMXT
	bool "Enable iWMMXt support"
1046 1047
	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
	default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1048 1049 1050 1051
	help
	  Enable support for iWMMXt context switching at run time if
	  running on a CPU that supports it.

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1052 1053 1054 1055 1056 1057
#  bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
config XSCALE_PMU
	bool
	depends on CPU_XSCALE && !XSCALE_PMU_TIMER
	default y

1058
config CPU_HAS_PMU
1059
	depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1060
		   (!ARCH_OMAP3 || OMAP3_EMU)
1061 1062 1063
	default y
	bool

1064 1065 1066 1067 1068
config MULTI_IRQ_HANDLER
	bool
	help
	  Allow each machine to specify it's own IRQ handler at run time.

1069 1070 1071 1072
if !MMU
source "arch/arm/Kconfig-nommu"
endif

1073 1074
config ARM_ERRATA_411920
	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1075
	depends on CPU_V6 || CPU_V6K
1076 1077 1078 1079 1080 1081
	help
	  Invalidation of the Instruction Cache operation can
	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
	  It does not affect the MPCore. This option enables the ARM Ltd.
	  recommended workaround.

1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097
config ARM_ERRATA_430973
	bool "ARM errata: Stale prediction on replaced interworking branch"
	depends on CPU_V7
	help
	  This option enables the workaround for the 430973 Cortex-A8
	  (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
	  interworking branch is replaced with another code sequence at the
	  same virtual address, whether due to self-modifying code or virtual
	  to physical address re-mapping, Cortex-A8 does not recover from the
	  stale interworking branch prediction. This results in Cortex-A8
	  executing the new code sequence in the incorrect ARM or Thumb state.
	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
	  and also flushes the branch target cache at every context switch.
	  Note that setting specific bits in the ACTLR register may not be
	  available in non-secure mode.

1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110
config ARM_ERRATA_458693
	bool "ARM errata: Processor deadlock when a false hazard is created"
	depends on CPU_V7
	help
	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
	  erratum. For very specific sequences of memory operations, it is
	  possible for a hazard condition intended for a cache line to instead
	  be incorrectly associated with a different cache line. This false
	  hazard might then cause a processor deadlock. The workaround enables
	  the L1 caching of the NEON accesses and disables the PLD instruction
	  in the ACTLR register. Note that setting specific bits in the ACTLR
	  register may not be available in non-secure mode.

1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122
config ARM_ERRATA_460075
	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
	depends on CPU_V7
	help
	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
	  erratum. Any asynchronous access to the L2 cache may encounter a
	  situation in which recent store transactions to the L2 cache are lost
	  and overwritten with stale memory contents from external memory. The
	  workaround disables the write-allocate mode for the L2 cache via the
	  ACTLR register. Note that setting specific bits in the ACTLR register
	  may not be available in non-secure mode.

1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134
config ARM_ERRATA_742230
	bool "ARM errata: DMB operation may be faulty"
	depends on CPU_V7 && SMP
	help
	  This option enables the workaround for the 742230 Cortex-A9
	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
	  between two write operations may not ensure the correct visibility
	  ordering of the two writes. This workaround sets a specific bit in
	  the diagnostic register of the Cortex-A9 which causes the DMB
	  instruction to behave as a DSB, ensuring the correct behaviour of
	  the two writes.

1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148
config ARM_ERRATA_742231
	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
	depends on CPU_V7 && SMP
	help
	  This option enables the workaround for the 742231 Cortex-A9
	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
	  accessing some data located in the same cache line, may get corrupted
	  data due to bad handling of the address hazard when the line gets
	  replaced from one of the CPUs at the same time as another CPU is
	  accessing it. This workaround sets specific bits in the diagnostic
	  register of the Cortex-A9 which reduces the linefill issuing
	  capabilities of the processor.

1149 1150
config PL310_ERRATA_588369
	bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1151
	depends on CACHE_L2X0
1152 1153 1154 1155 1156 1157 1158 1159
	help
	   The PL310 L2 cache controller implements three types of Clean &
	   Invalidate maintenance operations: by Physical Address
	   (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
	   They are architecturally defined to behave as the execution of a
	   clean operation followed immediately by an invalidate operation,
	   both performing to the same memory location. This functionality
	   is not correctly implemented in PL310 as clean lines are not
1160
	   invalidated as a result of these operations.
1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172

config ARM_ERRATA_720789
	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
	depends on CPU_V7 && SMP
	help
	  This option enables the workaround for the 720789 Cortex-A9 (prior to
	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
	  As a consequence of this erratum, some TLB entries which should be
	  invalidated are not, resulting in an incoherency in the system page
	  tables. The workaround changes the TLB flushing routines to invalidate
	  entries regardless of the ASID.
1173

1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184
config PL310_ERRATA_727915
	bool "Background Clean & Invalidate by Way operation can cause data corruption"
	depends on CACHE_L2X0
	help
	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance
	  operation (offset 0x7FC). This operation runs in background so that
	  PL310 can handle normal accesses while it is in progress. Under very
	  rare circumstances, due to this erratum, write data can be lost when
	  PL310 treats a cacheable write transaction during a Clean &
	  Invalidate by Way operation.

1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197
config ARM_ERRATA_743622
	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
	depends on CPU_V7
	help
	  This option enables the workaround for the 743622 Cortex-A9
	  (r2p0..r2p2) erratum. Under very rare conditions, a faulty
	  optimisation in the Cortex-A9 Store Buffer may lead to data
	  corruption. This workaround sets a specific bit in the diagnostic
	  register of the Cortex-A9 which disables the Store Buffer
	  optimisation, preventing the defect from occurring. This has no
	  visible impact on the overall performance or power consumption of the
	  processor.

1198 1199 1200 1201 1202 1203 1204 1205 1206 1207
config ARM_ERRATA_751472
	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
	depends on CPU_V7 && SMP
	help
	  This option enables the workaround for the 751472 Cortex-A9 (prior
	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
	  completion of a following broadcasted operation if the second
	  operation is received by a CPU before the ICIALLUIS has completed,
	  potentially leading to corrupted entries in the cache or TLB.

1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222
config ARM_ERRATA_753970
	bool "ARM errata: cache sync operation may be faulty"
	depends on CACHE_PL310
	help
	  This option enables the workaround for the 753970 PL310 (r3p0) erratum.

	  Under some condition the effect of cache sync operation on
	  the store buffer still remains when the operation completes.
	  This means that the store buffer is always asked to drain and
	  this prevents it from merging any further writes. The workaround
	  is to replace the normal offset of cache sync operation (0x730)
	  by another offset targeting an unmapped PL310 register 0x740.
	  This has the same effect as the cache sync operation: store buffer
	  drain and waiting for all buffers empty.

1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233
config ARM_ERRATA_754322
	bool "ARM errata: possible faulty MMU translations following an ASID switch"
	depends on CPU_V7
	help
	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
	  r3p*) erratum. A speculative memory access may cause a page table walk
	  which starts prior to an ASID switch but completes afterwards. This
	  can populate the micro-TLB with a stale entry which may be hit with
	  the new ASID. This workaround places two dsb instructions in the mm
	  switching code so that no page table walks can cross the ASID switch.

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config ARM_ERRATA_754327
	bool "ARM errata: no automatic Store Buffer drain"
	depends on CPU_V7 && SMP
	help
	  This option enables the workaround for the 754327 Cortex-A9 (prior to
	  r2p0) erratum. The Store Buffer does not have any automatic draining
	  mechanism and therefore a livelock may occur if an external agent
	  continuously polls a memory location waiting to observe an update.
	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
	  written polling loops from denying visibility of updates to memory.

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endmenu

source "arch/arm/common/Kconfig"

menu "Bus support"

config ARM_AMBA
	bool

config ISA
	bool
	help
	  Find out whether you have ISA slots on your motherboard.  ISA is the
	  name of a bus system, i.e. the way the CPU talks to the other stuff
	  inside your box.  Other bus systems are PCI, EISA, MicroChannel
	  (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
	  newer boards don't support it.  If you have ISA, say Y, otherwise N.

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# Select ISA DMA controller support
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config ISA_DMA
	bool
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	select ISA_DMA_API
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# Select ISA DMA interface
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config ISA_DMA_API
	bool

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config PCI
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	bool "PCI support" if MIGHT_HAVE_PCI
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	help
	  Find out whether you have a PCI motherboard. PCI is the name of a
	  bus system, i.e. the way the CPU talks to the other stuff inside
	  your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
	  VESA. If you have PCI, say Y, otherwise N.

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config PCI_DOMAINS
	bool
	depends on PCI

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config PCI_NANOENGINE
	bool "BSE nanoEngine PCI support"
	depends on SA1100_NANOENGINE
	help
	  Enable PCI on the BSE nanoEngine board.

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config PCI_SYSCALL
	def_bool PCI

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# Select the host bridge type
config PCI_HOST_VIA82C505
	bool
	depends on PCI && ARCH_SHARK
	default y

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config PCI_HOST_ITE8152
	bool
	depends on PCI && MACH_ARMCORE
	default y
	select DMABOUNCE

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source "drivers/pci/Kconfig"

source "drivers/pcmcia/Kconfig"

endmenu

menu "Kernel Features"

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source "kernel/time/Kconfig"

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config SMP
	bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1317
	depends on EXPERIMENTAL
1318
	depends on CPU_V6K || CPU_V7
1319
	depends on GENERIC_CLOCKEVENTS
1320
	depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1321
		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1322
		 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1323
		 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1324
	select USE_GENERIC_SMP_HELPERS
1325
	select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
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	help
	  This enables support for systems with more than one CPU. If you have
	  a system with only one CPU, like most personal computers, say N. If
	  you have a system with more than one CPU, say Y.

	  If you say N here, the kernel will run on single and multiprocessor
	  machines, but will use only one CPU of a multiprocessor machine. If
	  you say Y here, the kernel will run on many, but not all, single
	  processor machines. On a single processor machine, the kernel will
	  run faster if you say N here.

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	  See also <file:Documentation/i386/IO-APIC.txt>,
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	  <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
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	  <http://tldp.org/HOWTO/SMP-HOWTO.html>.
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	  If you don't know what to do here, say N.

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config SMP_ON_UP
	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
	depends on EXPERIMENTAL
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	depends on SMP && !XIP_KERNEL
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	default y
	help
	  SMP kernels contain instructions which fail on non-SMP processors.
	  Enabling this option allows the kernel to modify itself to make
	  these instructions safe.  Disabling it allows about 1K of space
	  savings.

	  If you don't know what to do here, say Y.

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config HAVE_ARM_SCU
	bool
	depends on SMP
	help
	  This option enables support for the ARM system coherency unit

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config HAVE_ARM_TWD
	bool
	depends on SMP
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	select TICK_ONESHOT
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	help
	  This options enables support for the ARM timer and watchdog unit

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choice
	prompt "Memory split"
	default VMSPLIT_3G
	help
	  Select the desired split between kernel and user memory.

	  If you are not absolutely sure what you are doing, leave this
	  option alone!

	config VMSPLIT_3G
		bool "3G/1G user/kernel split"
	config VMSPLIT_2G
		bool "2G/2G user/kernel split"
	config VMSPLIT_1G
		bool "1G/3G user/kernel split"
endchoice

config PAGE_OFFSET
	hex
	default 0x40000000 if VMSPLIT_1G
	default 0x80000000 if VMSPLIT_2G
	default 0xC0000000

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config NR_CPUS
	int "Maximum number of CPUs (2-32)"
	range 2 32
	depends on SMP
	default "4"

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config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
	depends on SMP && HOTPLUG && EXPERIMENTAL
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	depends on !ARCH_MSM
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	help
	  Say Y here to experiment with turning CPUs off and on.  CPUs
	  can be controlled through /sys/devices/system/cpu.

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config LOCAL_TIMERS
	bool "Use local timer interrupts"
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	depends on SMP
1409
	default y
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	select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
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	help
	  Enable support for local timers on SMP platforms, rather then the
	  legacy IPI broadcast method.  Local timers allows the system
	  accounting to be spread across the timer interval, preventing a
	  "thundering herd" at every timer tick.

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source kernel/Kconfig.preempt
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config HZ
	int
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	default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
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		ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
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	default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1424
	default AT91_TIMER_HZ if ARCH_AT91
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	default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
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	default 100

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config THUMB2_KERNEL
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	bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
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	depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
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	select AEABI
	select ARM_ASM_UNIFIED
	help
	  By enabling this option, the kernel will be compiled in
	  Thumb-2 mode. A compiler/assembler that understand the unified
	  ARM-Thumb syntax is needed.

	  If unsure, say N.

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config THUMB2_AVOID_R_ARM_THM_JUMP11
	bool "Work around buggy Thumb-2 short branch relocations in gas"
	depends on THUMB2_KERNEL && MODULES
	default y
	help
	  Various binutils versions can resolve Thumb-2 branches to
	  locally-defined, preemptible global symbols as short-range "b.n"
	  branch instructions.

	  This is a problem, because there's no guarantee the final
	  destination of the symbol, or any candidate locations for a
	  trampoline, are within range of the branch.  For this reason, the
	  kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
	  relocation in modules at all, and it makes little sense to add
	  support.

	  The symptom is that the kernel fails with an "unsupported
	  relocation" error when loading some modules.

	  Until fixed tools are available, passing
	  -fno-optimize-sibling-calls to gcc should prevent gcc generating
	  code which hits this problem, at the cost of a bit of extra runtime
	  stack usage in some cases.

	  The problem is described in more detail at:
	      https://bugs.launchpad.net/binutils-linaro/+bug/725126

	  Only Thumb-2 kernels are affected.

	  Unless you are sure your tools don't have this problem, say Y.

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config ARM_ASM_UNIFIED
	bool

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config AEABI
	bool "Use the ARM EABI to compile the kernel"
	help
	  This option allows for the kernel to be compiled using the latest
	  ARM ABI (aka EABI).  This is only useful if you are using a user
	  space environment that is also compiled with EABI.

	  Since there are major incompatibilities between the legacy ABI and
	  EABI, especially with regard to structure member alignment, this
	  option also changes the kernel syscall calling convention to
	  disambiguate both ABIs and allow for backward compatibility support
	  (selected with CONFIG_OABI_COMPAT).

	  To use this you need GCC version 4.0.0 or later.

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config OABI_COMPAT
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	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
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	depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
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	default y
	help
	  This option preserves the old syscall interface along with the
	  new (ARM EABI) one. It also provides a compatibility layer to
	  intercept syscalls that have structure arguments which layout
	  in memory differs between the legacy ABI and the new ARM EABI
	  (only for non "thumb" binaries). This option adds a tiny
	  overhead to all syscalls and produces a slightly larger kernel.
	  If you know you'll be using only pure EABI user space then you
	  can say N here. If this option is not selected and you attempt
	  to execute a legacy ABI binary then the result will be
	  UNPREDICTABLE (in fact it can be predicted that it won't work
	  at all). If in doubt say Y.

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config ARCH_HAS_HOLES_MEMORYMODEL
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	bool

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config ARCH_SPARSEMEM_ENABLE
	bool

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config ARCH_SPARSEMEM_DEFAULT
	def_bool ARCH_SPARSEMEM_ENABLE

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config ARCH_SELECT_MEMORY_MODEL
1516
	def_bool ARCH_SPARSEMEM_ENABLE
1517

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config HIGHMEM
	bool "High Memory Support (EXPERIMENTAL)"
	depends on MMU && EXPERIMENTAL
	help
	  The address space of ARM processors is only 4 Gigabytes large
	  and it has to accommodate user address space, kernel address
	  space as well as some memory mapped IO. That means that, if you
	  have a large amount of physical memory and/or IO, not all of the
	  memory can be "permanently mapped" by the kernel. The physical
	  memory that is not permanently mapped is called "high memory".

	  Depending on the selected kernel/user memory split, minimum
	  vmalloc space and actual amount of RAM, you may not need this
	  option which should result in a slightly faster kernel.

	  If unsure, say n.

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config HIGHPTE
	bool "Allocate 2nd-level pagetables from highmem"
	depends on HIGHMEM
	depends on !OUTER_CACHE

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config HW_PERF_EVENTS
	bool "Enable hardware performance counter support for perf events"
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	depends on PERF_EVENTS && CPU_HAS_PMU
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	default y
	help
	  Enable hardware performance counter support for perf events. If
	  disabled, perf events will use software events only.

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source "mm/Kconfig"

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config FORCE_MAX_ZONEORDER
	int "Maximum zone order" if ARCH_SHMOBILE
	range 11 64 if ARCH_SHMOBILE
	default "9" if SA1111
	default "11"
	help
	  The kernel memory allocator divides physically contiguous memory
	  blocks into "zones", where each zone is a power of two number of
	  pages.  This option selects the largest power of two that the kernel
	  keeps in the memory allocator.  If you need to allocate very large
	  blocks of physically contiguous memory, then you may need to
	  increase this value.

	  This config option is actually maximum order plus one. For example,
	  a value of 11 means that the largest free memory block is 2^10 pages.

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config LEDS
	bool "Timer and CPU usage LEDs"
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	depends on ARCH_CDB89712 || ARCH_EBSA110 || \
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		   ARCH_EBSA285 || ARCH_INTEGRATOR || \
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		   ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
		   ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
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		   ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
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		   ARCH_AT91 || ARCH_DAVINCI || \
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		   ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
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	help
	  If you say Y here, the LEDs on your machine will be used
	  to provide useful information about your current system status.

	  If you are compiling a kernel for a NetWinder or EBSA-285, you will
	  be able to select which LEDs are active using the options below. If
	  you are compiling a kernel for the EBSA-110 or the LART however, the
	  red LED will simply flash regularly to indicate that the system is
	  still functional. It is safe to say Y here if you have a CATS
	  system, but the driver will do nothing.

config LEDS_TIMER
	bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
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			    OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
			    || MACH_OMAP_PERSEUS2
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	depends on LEDS
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	depends on !GENERIC_CLOCKEVENTS
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	default y if ARCH_EBSA110
	help
	  If you say Y here, one of the system LEDs (the green one on the
	  NetWinder, the amber one on the EBSA285, or the red one on the LART)
	  will flash regularly to indicate that the system is still
	  operational. This is mainly useful to kernel hackers who are
	  debugging unstable kernels.

	  The LART uses the same LED for both Timer LED and CPU usage LED
	  functions. You may choose to use both, but the Timer LED function
	  will overrule the CPU usage LED.

config LEDS_CPU
	bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
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			!ARCH_OMAP) \
			|| OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
			|| MACH_OMAP_PERSEUS2
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	depends on LEDS
	help
	  If you say Y here, the red LED will be used to give a good real
	  time indication of CPU usage, by lighting whenever the idle task
	  is not currently executing.

	  The LART uses the same LED for both Timer LED and CPU usage LED
	  functions. You may choose to use both, but the Timer LED function
	  will overrule the CPU usage LED.

config ALIGNMENT_TRAP
	bool
1621
	depends on CPU_CP15_MMU
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	default y if !ARCH_EBSA110
1623
	select HAVE_PROC_CPU if PROC_FS
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	help
1625
	  ARM processors cannot fetch/store information which is not
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	  naturally aligned on the bus, i.e., a 4 byte fetch must start at an
	  address divisible by 4. On 32-bit ARM processors, these non-aligned
	  fetch/store instructions will be emulated in software if you say
	  here, which has a severe performance impact. This is necessary for
	  correct operation of some network protocols. With an IP-only
	  configuration it is safe to say N, otherwise say Y.

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config UACCESS_WITH_MEMCPY
	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
	depends on MMU && EXPERIMENTAL
	default y if CPU_FEROCEON
	help
	  Implement faster copy_to_user and clear_user methods for CPU
	  cores where a 8-word STM instruction give significantly higher
	  memory write throughput than a sequence of individual 32bit stores.

	  A possible side effect is a slight increase in scheduling latency
	  between threads sharing the same address space if they invoke
	  such copy operations with large buffers.

	  However, if the CPU data cache is using a write-allocate mode,
	  this option is unlikely to provide any performance gain.

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config SECCOMP
	bool
	prompt "Enable seccomp to safely compute untrusted bytecode"
	---help---
	  This kernel feature is useful for number crunching applications
	  that may need to compute untrusted bytecode during their
	  execution. By using pipes or other transports made available to
	  the process as file descriptors supporting the read/write
	  syscalls, it's possible to isolate those applications in
	  their own address space using seccomp. Once seccomp is
	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
	  and the task is only allowed to execute a few safe syscalls
	  defined by each seccomp mode.

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config CC_STACKPROTECTOR
	bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1665
	depends on EXPERIMENTAL
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	help
	  This option turns on the -fstack-protector GCC feature. This
	  feature puts, at the beginning of functions, a canary value on
	  the stack just before the return address, and validates
	  the value just before actually returning.  Stack based buffer
	  overflows (that need to overwrite this return address) now also
	  overwrite the canary, which gets detected and the attack is then
	  neutralized via a kernel panic.
	  This feature requires gcc version 4.2 or above.

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config DEPRECATED_PARAM_STRUCT
	bool "Provide old way to pass kernel parameters"
	help
	  This was deprecated in 2001 and announced to live on for 5 years.
	  Some old boot loaders still use this way.

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endmenu

menu "Boot options"

# Compressed boot loader in ROM.  Yes, we really want to ask about
# TEXT and BSS so we preserve their values in the config files.
config ZBOOT_ROM_TEXT
	hex "Compressed ROM boot loader base address"
	default "0"
	help
	  The physical address at which the ROM-able zImage is to be
	  placed in the target.  Platforms which normally make use of
	  ROM-able zImage formats normally set this to a suitable
	  value in their defconfig file.

	  If ZBOOT_ROM is not enabled, this has no effect.

config ZBOOT_ROM_BSS
	hex "Compressed ROM boot loader BSS address"
	default "0"
	help
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	  The base address of an area of read/write memory in the target
	  for the ROM-able zImage which must be available while the
	  decompressor is running. It must be large enough to hold the
	  entire decompressed kernel plus an additional 128 KiB.
	  Platforms which normally make use of ROM-able zImage formats
	  normally set this to a suitable value in their defconfig file.
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	  If ZBOOT_ROM is not enabled, this has no effect.

config ZBOOT_ROM
	bool "Compressed boot loader in ROM/flash"
	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
	help
	  Say Y here if you intend to execute your compressed kernel image
	  (zImage) directly from ROM or flash.  If unsure, say N.

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config ZBOOT_ROM_MMCIF
	bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
	depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
	help
	  Say Y here to include experimental MMCIF loading code in the
	  ROM-able zImage. With this enabled it is possible to write the
	  the ROM-able zImage kernel image to an MMC card and boot the
	  kernel straight from the reset vector. At reset the processor
	  Mask ROM will load the first part of the the ROM-able zImage
	  which in turn loads the rest the kernel image to RAM using the
	  MMCIF hardware block.

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config CMDLINE
	string "Default kernel command string"
	default ""
	help
	  On some architectures (EBSA110 and CATS), there is currently no way
	  for the boot loader to pass arguments to the kernel. For these
	  architectures, you should supply some command-line options at build
	  time by entering them here. As a minimum, you should specify the
	  memory size and the root device (e.g., mem=64M root=/dev/nfs).

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config CMDLINE_FORCE
	bool "Always use the default kernel command string"
	depends on CMDLINE != ""
	help
	  Always use the default kernel command string, even if the boot
	  loader passes other arguments to the kernel.
	  This is useful if you cannot or don't want to change the
	  command-line options your boot loader passes to the kernel.

	  If unsure, say N.

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config XIP_KERNEL
	bool "Kernel Execute-In-Place from ROM"
	depends on !ZBOOT_ROM
	help
	  Execute-In-Place allows the kernel to run from non-volatile storage
	  directly addressable by the CPU, such as NOR flash. This saves RAM
	  space since the text section of the kernel is not loaded from flash
	  to RAM.  Read-write sections, such as the data section and stack,
	  are still copied to RAM.  The XIP kernel is not compressed since
	  it has to run directly from flash, so it will take more space to
	  store it.  The flash address used to link the kernel object files,
	  and for storing it, is configuration dependent. Therefore, if you
	  say Y here, you must know the proper physical address where to
	  store the kernel image depending on your own flash memory usage.

	  Also note that the make target becomes "make xipImage" rather than
	  "make zImage" or "make Image".  The final kernel binary to put in
	  ROM memory will be arch/arm/boot/xipImage.

	  If unsure, say N.

config XIP_PHYS_ADDR
	hex "XIP Kernel Physical Location"
	depends on XIP_KERNEL
	default "0x00080000"
	help
	  This is the physical address in your flash memory the kernel will
	  be linked for and stored to.  This address is dependent on your
	  own flash usage.

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config KEXEC
	bool "Kexec system call (EXPERIMENTAL)"
	depends on EXPERIMENTAL
	help
	  kexec is a system call that implements the ability to shutdown your
	  current kernel, and to start another kernel.  It is like a reboot
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	  but it is independent of the system firmware.   And like a reboot
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	  you can start any kernel with it, not just Linux.

	  It is an ongoing process to be certain the hardware in a machine
	  is properly shutdown, so do not be surprised if this code does not
	  initially work for you.  It may help to enable device hotplugging
	  support.

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config ATAGS_PROC
	bool "Export atags in procfs"
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	depends on KEXEC
	default y
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	help
	  Should the atags used to boot the kernel be exported in an "atags"
	  file in procfs. Useful with kexec.

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config CRASH_DUMP
	bool "Build kdump crash kernel (EXPERIMENTAL)"
	depends on EXPERIMENTAL
	help
	  Generate crash dump after being started by kexec. This should
	  be normally only set in special crash dump kernels which are
	  loaded in the main kernel with kexec-tools into a specially
	  reserved region and then later executed after a crash by
	  kdump/kexec. The crash dump kernel must be compiled to a
	  memory address not used by the main kernel

	  For more details see Documentation/kdump/kdump.txt

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config AUTO_ZRELADDR
	bool "Auto calculation of the decompressed kernel image address"
	depends on !ZBOOT_ROM && !ARCH_U300
	help
	  ZRELADDR is the physical address where the decompressed kernel
	  image will be placed. If AUTO_ZRELADDR is selected, the address
	  will be determined at run-time by masking the current IP with
	  0xf8000000. This assumes the zImage being placed in the first 128MB
	  from start of memory.

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endmenu

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menu "CPU Power Management"
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if ARCH_HAS_CPUFREQ
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source "drivers/cpufreq/Kconfig"

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config CPU_FREQ_IMX
	tristate "CPUfreq driver for i.MX CPUs"
	depends on ARCH_MXC && CPU_FREQ
	help
	  This enables the CPUfreq driver for i.MX CPUs.

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config CPU_FREQ_SA1100
	bool

config CPU_FREQ_SA1110
	bool

config CPU_FREQ_INTEGRATOR
	tristate "CPUfreq driver for ARM Integrator CPUs"
	depends on ARCH_INTEGRATOR && CPU_FREQ
	default y
	help
	  This enables the CPUfreq driver for ARM Integrator CPUs.

	  For details, take a look at <file:Documentation/cpu-freq>.

	  If in doubt, say Y.

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config CPU_FREQ_PXA
	bool
	depends on CPU_FREQ && ARCH_PXA && PXA25x
	default y
	select CPU_FREQ_DEFAULT_GOV_USERSPACE

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config CPU_FREQ_S3C64XX
	bool "CPUfreq support for Samsung S3C64XX CPUs"
	depends on CPU_FREQ && CPU_S3C6410

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config CPU_FREQ_S3C
	bool
	help
	  Internal configuration node for common cpufreq on Samsung SoC

config CPU_FREQ_S3C24XX
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	bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
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	depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
	select CPU_FREQ_S3C
	help
	  This enables the CPUfreq driver for the Samsung S3C24XX family
	  of CPUs.

	  For details, take a look at <file:Documentation/cpu-freq>.

	  If in doubt, say N.

config CPU_FREQ_S3C24XX_PLL
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	bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
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	depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
	help
	  Compile in support for changing the PLL frequency from the
	  S3C24XX series CPUfreq driver. The PLL takes time to settle
	  after a frequency change, so by default it is not enabled.

	  This also means that the PLL tables for the selected CPU(s) will
	  be built which may increase the size of the kernel image.

config CPU_FREQ_S3C24XX_DEBUG
	bool "Debug CPUfreq Samsung driver core"
	depends on CPU_FREQ_S3C24XX
	help
	  Enable s3c_freq_dbg for the Samsung S3C CPUfreq core

config CPU_FREQ_S3C24XX_IODEBUG
	bool "Debug CPUfreq Samsung driver IO timing"
	depends on CPU_FREQ_S3C24XX
	help
	  Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core

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config CPU_FREQ_S3C24XX_DEBUGFS
	bool "Export debugfs for CPUFreq"
	depends on CPU_FREQ_S3C24XX && DEBUG_FS
	help
	  Export status information via debugfs.

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endif

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source "drivers/cpuidle/Kconfig"

endmenu

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menu "Floating point emulation"

comment "At least one emulation must be selected"

config FPE_NWFPE
	bool "NWFPE math emulation"
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	depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
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	---help---
	  Say Y to include the NWFPE floating point emulator in the kernel.
	  This is necessary to run most binaries. Linux does not currently
	  support floating point hardware so you need to say Y here even if
	  your machine has an FPA or floating point co-processor podule.

	  You may say N here if you are going to load the Acorn FPEmulator
	  early in the bootup.

config FPE_NWFPE_XP
	bool "Support extended precision"
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	depends on FPE_NWFPE
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	help
	  Say Y to include 80-bit support in the kernel floating-point
	  emulator.  Otherwise, only 32 and 64-bit support is compiled in.
	  Note that gcc does not generate 80-bit operations by default,
	  so in most cases this option only enlarges the size of the
	  floating point emulator without any good reason.

	  You almost surely want to say N here.

config FPE_FASTFPE
	bool "FastFPE math emulation (EXPERIMENTAL)"
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	depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
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	---help---
	  Say Y here to include the FAST floating point emulator in the kernel.
	  This is an experimental much faster emulator which now also has full
	  precision for the mantissa.  It does not support any exceptions.
	  It is very simple, and approximately 3-6 times faster than NWFPE.

	  It should be sufficient for most programs.  It may be not suitable
	  for scientific calculations, but you have to check this for yourself.
	  If you do not feel you need a faster FP emulation you should better
	  choose NWFPE.

config VFP
	bool "VFP-format floating point maths"
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	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
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	help
	  Say Y to include VFP support code in the kernel. This is needed
	  if your hardware includes a VFP unit.

	  Please see <file:Documentation/arm/VFP/release-notes.txt> for
	  release notes and additional status information.

	  Say N if your target does not have VFP hardware.

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config VFPv3
	bool
	depends on VFP
	default y if CPU_V7

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config NEON
	bool "Advanced SIMD (NEON) Extension support"
	depends on VFPv3 && CPU_V7
	help
	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
	  Extension.

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endmenu

menu "Userspace binary formats"

source "fs/Kconfig.binfmt"

config ARTHUR
	tristate "RISC OS personality"
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	depends on !AEABI
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	help
	  Say Y here to include the kernel code necessary if you want to run
	  Acorn RISC OS/Arthur binaries under Linux. This code is still very
	  experimental; if this sounds frightening, say N and sleep in peace.
	  You can also say M here to compile this support as a module (which
	  will be called arthur).

endmenu

menu "Power management options"

2006
source "kernel/power/Kconfig"
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config ARCH_SUSPEND_POSSIBLE
	def_bool y

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endmenu

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source "net/Kconfig"

2015
source "drivers/Kconfig"
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source "fs/Kconfig"

source "arch/arm/Kconfig.debug"

source "security/Kconfig"

source "crypto/Kconfig"

source "lib/Kconfig"
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