ioat_dma.c 47.3 KB
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/*
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 * Intel I/OAT DMA Linux driver
 * Copyright(c) 2004 - 2007 Intel Corporation.
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 *
 * This program is free software; you can redistribute it and/or modify it
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 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
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 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
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 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 * The full GNU General Public License is included in this distribution in
 * the file called "COPYING".
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 *
 */

/*
 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
 * copy operations.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/dmaengine.h>
#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/workqueue.h>
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#include <linux/i7300_idle.h>
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#include "ioatdma.h"
#include "ioatdma_registers.h"
#include "ioatdma_hw.h"

#define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common)
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#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
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#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
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#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx)
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#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
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static int ioat_pending_level = 4;
module_param(ioat_pending_level, int, 0644);
MODULE_PARM_DESC(ioat_pending_level,
		 "high-water mark for pushing ioat descriptors (default: 4)");

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#define RESET_DELAY  msecs_to_jiffies(100)
#define WATCHDOG_DELAY  round_jiffies(msecs_to_jiffies(2000))
static void ioat_dma_chan_reset_part2(struct work_struct *work);
static void ioat_dma_chan_watchdog(struct work_struct *work);

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/*
 * workaround for IOAT ver.3.0 null descriptor issue
 * (channel returns error when size is 0)
 */
#define NULL_DESC_BUFFER_SIZE 1

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/* internal functions */
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static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan);
static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan);
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static struct ioat_desc_sw *
ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
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static struct ioat_desc_sw *
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ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
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static inline struct ioat_dma_chan *ioat_lookup_chan_by_index(
						struct ioatdma_device *device,
						int index)
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{
	return device->idx[index];
}

/**
 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
 * @irq: interrupt id
 * @data: interrupt data
 */
static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
{
	struct ioatdma_device *instance = data;
	struct ioat_dma_chan *ioat_chan;
	unsigned long attnstatus;
	int bit;
	u8 intrctrl;

	intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);

	if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
		return IRQ_NONE;

	if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
		writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
		return IRQ_NONE;
	}

	attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
	for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
		ioat_chan = ioat_lookup_chan_by_index(instance, bit);
		tasklet_schedule(&ioat_chan->cleanup_task);
	}

	writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
	return IRQ_HANDLED;
}

/**
 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
 * @irq: interrupt id
 * @data: interrupt data
 */
static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
{
	struct ioat_dma_chan *ioat_chan = data;

	tasklet_schedule(&ioat_chan->cleanup_task);

	return IRQ_HANDLED;
}

static void ioat_dma_cleanup_tasklet(unsigned long data);

/**
 * ioat_dma_enumerate_channels - find and initialize the device's channels
 * @device: the device to be enumerated
 */
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static int ioat_dma_enumerate_channels(struct ioatdma_device *device)
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{
	u8 xfercap_scale;
	u32 xfercap;
	int i;
	struct ioat_dma_chan *ioat_chan;

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	/*
	 * IOAT ver.3 workarounds
	 */
	if (device->version == IOAT_VER_3_0) {
		u32 chan_err_mask;
		u16 dev_id;
		u32 dmauncerrsts;

		/*
		 * Write CHANERRMSK_INT with 3E07h to mask out the errors
		 * that can cause stability issues for IOAT ver.3
		 */
		chan_err_mask = 0x3E07;
		pci_write_config_dword(device->pdev,
			IOAT_PCI_CHANERRMASK_INT_OFFSET,
			chan_err_mask);

		/*
		 * Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
		 * (workaround for spurious config parity error after restart)
		 */
		pci_read_config_word(device->pdev,
			IOAT_PCI_DEVICE_ID_OFFSET,
			&dev_id);
		if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {
			dmauncerrsts = 0x10;
			pci_write_config_dword(device->pdev,
				IOAT_PCI_DMAUNCERRSTS_OFFSET,
				dmauncerrsts);
		}
	}

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	device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
	xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
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	xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));

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#ifdef  CONFIG_I7300_IDLE_IOAT_CHANNEL
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	if (i7300_idle_platform_probe(NULL, NULL) == 0) {
		device->common.chancnt--;
	}
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#endif
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	for (i = 0; i < device->common.chancnt; i++) {
		ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL);
		if (!ioat_chan) {
			device->common.chancnt = i;
			break;
		}

		ioat_chan->device = device;
		ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1));
		ioat_chan->xfercap = xfercap;
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		ioat_chan->desccount = 0;
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		INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2);
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		if (ioat_chan->device->version != IOAT_VER_1_2) {
			writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE
					| IOAT_DMA_DCA_ANY_CPU,
				ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
		}
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		spin_lock_init(&ioat_chan->cleanup_lock);
		spin_lock_init(&ioat_chan->desc_lock);
		INIT_LIST_HEAD(&ioat_chan->free_desc);
		INIT_LIST_HEAD(&ioat_chan->used_desc);
		/* This should be made common somewhere in dmaengine.c */
		ioat_chan->common.device = &device->common;
		list_add_tail(&ioat_chan->common.device_node,
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			      &device->common.channels);
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		device->idx[i] = ioat_chan;
		tasklet_init(&ioat_chan->cleanup_task,
			     ioat_dma_cleanup_tasklet,
			     (unsigned long) ioat_chan);
		tasklet_disable(&ioat_chan->cleanup_task);
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	}
	return device->common.chancnt;
}

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/**
 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
 *                                 descriptors to hw
 * @chan: DMA channel handle
 */
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static inline void __ioat1_dma_memcpy_issue_pending(
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						struct ioat_dma_chan *ioat_chan)
{
	ioat_chan->pending = 0;
	writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET);
}

static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
{
	struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);

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	if (ioat_chan->pending > 0) {
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		spin_lock_bh(&ioat_chan->desc_lock);
		__ioat1_dma_memcpy_issue_pending(ioat_chan);
		spin_unlock_bh(&ioat_chan->desc_lock);
	}
}

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static inline void __ioat2_dma_memcpy_issue_pending(
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						struct ioat_dma_chan *ioat_chan)
{
	ioat_chan->pending = 0;
	writew(ioat_chan->dmacount,
	       ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
}

static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan)
{
	struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);

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	if (ioat_chan->pending > 0) {
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		spin_lock_bh(&ioat_chan->desc_lock);
		__ioat2_dma_memcpy_issue_pending(ioat_chan);
		spin_unlock_bh(&ioat_chan->desc_lock);
	}
}
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/**
 * ioat_dma_chan_reset_part2 - reinit the channel after a reset
 */
static void ioat_dma_chan_reset_part2(struct work_struct *work)
{
	struct ioat_dma_chan *ioat_chan =
		container_of(work, struct ioat_dma_chan, work.work);
	struct ioat_desc_sw *desc;

	spin_lock_bh(&ioat_chan->cleanup_lock);
	spin_lock_bh(&ioat_chan->desc_lock);

	ioat_chan->completion_virt->low = 0;
	ioat_chan->completion_virt->high = 0;
	ioat_chan->pending = 0;

	/*
	 * count the descriptors waiting, and be sure to do it
	 * right for both the CB1 line and the CB2 ring
	 */
	ioat_chan->dmacount = 0;
	if (ioat_chan->used_desc.prev) {
		desc = to_ioat_desc(ioat_chan->used_desc.prev);
		do {
			ioat_chan->dmacount++;
			desc = to_ioat_desc(desc->node.next);
		} while (&desc->node != ioat_chan->used_desc.next);
	}

	/*
	 * write the new starting descriptor address
	 * this puts channel engine into ARMED state
	 */
	desc = to_ioat_desc(ioat_chan->used_desc.prev);
	switch (ioat_chan->device->version) {
	case IOAT_VER_1_2:
		writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
		       ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
		writel(((u64) desc->async_tx.phys) >> 32,
		       ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);

		writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
			+ IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
		break;
	case IOAT_VER_2_0:
		writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
		       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
		writel(((u64) desc->async_tx.phys) >> 32,
		       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);

		/* tell the engine to go with what's left to be done */
		writew(ioat_chan->dmacount,
		       ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);

		break;
	}
	dev_err(&ioat_chan->device->pdev->dev,
		"chan%d reset - %d descs waiting, %d total desc\n",
		chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);

	spin_unlock_bh(&ioat_chan->desc_lock);
	spin_unlock_bh(&ioat_chan->cleanup_lock);
}

/**
 * ioat_dma_reset_channel - restart a channel
 * @ioat_chan: IOAT DMA channel handle
 */
static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan)
{
	u32 chansts, chanerr;

	if (!ioat_chan->used_desc.prev)
		return;

	chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
	chansts = (ioat_chan->completion_virt->low
					& IOAT_CHANSTS_DMA_TRANSFER_STATUS);
	if (chanerr) {
		dev_err(&ioat_chan->device->pdev->dev,
			"chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
			chan_num(ioat_chan), chansts, chanerr);
		writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
	}

	/*
	 * whack it upside the head with a reset
	 * and wait for things to settle out.
	 * force the pending count to a really big negative
	 * to make sure no one forces an issue_pending
	 * while we're waiting.
	 */

	spin_lock_bh(&ioat_chan->desc_lock);
	ioat_chan->pending = INT_MIN;
	writeb(IOAT_CHANCMD_RESET,
	       ioat_chan->reg_base
	       + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
	spin_unlock_bh(&ioat_chan->desc_lock);

	/* schedule the 2nd half instead of sleeping a long time */
	schedule_delayed_work(&ioat_chan->work, RESET_DELAY);
}

/**
 * ioat_dma_chan_watchdog - watch for stuck channels
 */
static void ioat_dma_chan_watchdog(struct work_struct *work)
{
	struct ioatdma_device *device =
		container_of(work, struct ioatdma_device, work.work);
	struct ioat_dma_chan *ioat_chan;
	int i;

	union {
		u64 full;
		struct {
			u32 low;
			u32 high;
		};
	} completion_hw;
	unsigned long compl_desc_addr_hw;

	for (i = 0; i < device->common.chancnt; i++) {
		ioat_chan = ioat_lookup_chan_by_index(device, i);

		if (ioat_chan->device->version == IOAT_VER_1_2
			/* have we started processing anything yet */
		    && ioat_chan->last_completion
			/* have we completed any since last watchdog cycle? */
		    && (ioat_chan->last_completion ==
				ioat_chan->watchdog_completion)
			/* has TCP stuck on one cookie since last watchdog? */
		    && (ioat_chan->watchdog_tcp_cookie ==
				ioat_chan->watchdog_last_tcp_cookie)
		    && (ioat_chan->watchdog_tcp_cookie !=
				ioat_chan->completed_cookie)
			/* is there something in the chain to be processed? */
			/* CB1 chain always has at least the last one processed */
		    && (ioat_chan->used_desc.prev != ioat_chan->used_desc.next)
		    && ioat_chan->pending == 0) {

			/*
			 * check CHANSTS register for completed
			 * descriptor address.
			 * if it is different than completion writeback,
			 * it is not zero
			 * and it has changed since the last watchdog
			 *     we can assume that channel
			 *     is still working correctly
			 *     and the problem is in completion writeback.
			 *     update completion writeback
			 *     with actual CHANSTS value
			 * else
			 *     try resetting the channel
			 */

			completion_hw.low = readl(ioat_chan->reg_base +
				IOAT_CHANSTS_OFFSET_LOW(ioat_chan->device->version));
			completion_hw.high = readl(ioat_chan->reg_base +
				IOAT_CHANSTS_OFFSET_HIGH(ioat_chan->device->version));
#if (BITS_PER_LONG == 64)
			compl_desc_addr_hw =
				completion_hw.full
				& IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
#else
			compl_desc_addr_hw =
				completion_hw.low & IOAT_LOW_COMPLETION_MASK;
#endif

			if ((compl_desc_addr_hw != 0)
			   && (compl_desc_addr_hw != ioat_chan->watchdog_completion)
			   && (compl_desc_addr_hw != ioat_chan->last_compl_desc_addr_hw)) {
				ioat_chan->last_compl_desc_addr_hw = compl_desc_addr_hw;
				ioat_chan->completion_virt->low = completion_hw.low;
				ioat_chan->completion_virt->high = completion_hw.high;
			} else {
				ioat_dma_reset_channel(ioat_chan);
				ioat_chan->watchdog_completion = 0;
				ioat_chan->last_compl_desc_addr_hw = 0;
			}

		/*
		 * for version 2.0 if there are descriptors yet to be processed
		 * and the last completed hasn't changed since the last watchdog
		 *      if they haven't hit the pending level
		 *          issue the pending to push them through
		 *      else
		 *          try resetting the channel
		 */
		} else if (ioat_chan->device->version == IOAT_VER_2_0
		    && ioat_chan->used_desc.prev
		    && ioat_chan->last_completion
		    && ioat_chan->last_completion == ioat_chan->watchdog_completion) {

			if (ioat_chan->pending < ioat_pending_level)
				ioat2_dma_memcpy_issue_pending(&ioat_chan->common);
			else {
				ioat_dma_reset_channel(ioat_chan);
				ioat_chan->watchdog_completion = 0;
			}
		} else {
			ioat_chan->last_compl_desc_addr_hw = 0;
			ioat_chan->watchdog_completion
					= ioat_chan->last_completion;
		}

		ioat_chan->watchdog_last_tcp_cookie =
			ioat_chan->watchdog_tcp_cookie;
	}

	schedule_delayed_work(&device->work, WATCHDOG_DELAY);
}

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static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
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{
	struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
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	struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
	struct ioat_desc_sw *prev, *new;
	struct ioat_dma_descriptor *hw;
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	dma_cookie_t cookie;
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	LIST_HEAD(new_chain);
	u32 copy;
	size_t len;
	dma_addr_t src, dst;
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	unsigned long orig_flags;
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	unsigned int desc_count = 0;

	/* src and dest and len are stored in the initial descriptor */
	len = first->len;
	src = first->src;
	dst = first->dst;
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	orig_flags = first->async_tx.flags;
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	new = first;
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	spin_lock_bh(&ioat_chan->desc_lock);
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	prev = to_ioat_desc(ioat_chan->used_desc.prev);
	prefetch(prev->hw);
	do {
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		copy = min_t(size_t, len, ioat_chan->xfercap);
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		async_tx_ack(&new->async_tx);
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		hw = new->hw;
		hw->size = copy;
		hw->ctl = 0;
		hw->src_addr = src;
		hw->dst_addr = dst;
		hw->next = 0;

		/* chain together the physical address list for the HW */
		wmb();
		prev->hw->next = (u64) new->async_tx.phys;

		len -= copy;
		dst += copy;
		src += copy;

		list_add_tail(&new->node, &new_chain);
		desc_count++;
		prev = new;
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	} while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan)));
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	if (!new) {
		dev_err(&ioat_chan->device->pdev->dev,
			"tx submit failed\n");
		spin_unlock_bh(&ioat_chan->desc_lock);
		return -ENOMEM;
	}

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	hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
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	if (first->async_tx.callback) {
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		hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
		if (first != new) {
			/* move callback into to last desc */
			new->async_tx.callback = first->async_tx.callback;
			new->async_tx.callback_param
					= first->async_tx.callback_param;
			first->async_tx.callback = NULL;
			first->async_tx.callback_param = NULL;
		}
	}

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	new->tx_cnt = desc_count;
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	new->async_tx.flags = orig_flags; /* client is in control of this ack */
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	/* store the original values for use in later cleanup */
	if (new != first) {
		new->src = first->src;
		new->dst = first->dst;
		new->len = first->len;
	}

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	/* cookie incr and addition to used_list must be atomic */
	cookie = ioat_chan->common.cookie;
	cookie++;
	if (cookie < 0)
		cookie = 1;
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	ioat_chan->common.cookie = new->async_tx.cookie = cookie;
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	/* write address into NextDescriptor field of last desc in chain */
	to_ioat_desc(ioat_chan->used_desc.prev)->hw->next =
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							first->async_tx.phys;
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	list_splice_tail(&new_chain, &ioat_chan->used_desc);
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	ioat_chan->dmacount += desc_count;
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	ioat_chan->pending += desc_count;
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	if (ioat_chan->pending >= ioat_pending_level)
		__ioat1_dma_memcpy_issue_pending(ioat_chan);
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	spin_unlock_bh(&ioat_chan->desc_lock);

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	return cookie;
}

static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
{
	struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
	struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
	struct ioat_desc_sw *new;
	struct ioat_dma_descriptor *hw;
	dma_cookie_t cookie;
	u32 copy;
	size_t len;
	dma_addr_t src, dst;
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	unsigned long orig_flags;
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	unsigned int desc_count = 0;

	/* src and dest and len are stored in the initial descriptor */
	len = first->len;
	src = first->src;
	dst = first->dst;
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	orig_flags = first->async_tx.flags;
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	new = first;

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	/*
	 * ioat_chan->desc_lock is still in force in version 2 path
	 * it gets unlocked at end of this function
	 */
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	do {
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		copy = min_t(size_t, len, ioat_chan->xfercap);
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		async_tx_ack(&new->async_tx);
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		hw = new->hw;
		hw->size = copy;
		hw->ctl = 0;
		hw->src_addr = src;
		hw->dst_addr = dst;

		len -= copy;
		dst += copy;
		src += copy;
		desc_count++;
	} while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan)));

612 613 614 615 616 617 618 619
	if (!new) {
		dev_err(&ioat_chan->device->pdev->dev,
			"tx submit failed\n");
		spin_unlock_bh(&ioat_chan->desc_lock);
		return -ENOMEM;
	}

	hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
620
	if (first->async_tx.callback) {
621 622 623 624 625 626 627 628 629 630 631 632
		hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
		if (first != new) {
			/* move callback into to last desc */
			new->async_tx.callback = first->async_tx.callback;
			new->async_tx.callback_param
					= first->async_tx.callback_param;
			first->async_tx.callback = NULL;
			first->async_tx.callback_param = NULL;
		}
	}

	new->tx_cnt = desc_count;
633
	new->async_tx.flags = orig_flags; /* client is in control of this ack */
634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653

	/* store the original values for use in later cleanup */
	if (new != first) {
		new->src = first->src;
		new->dst = first->dst;
		new->len = first->len;
	}

	/* cookie incr and addition to used_list must be atomic */
	cookie = ioat_chan->common.cookie;
	cookie++;
	if (cookie < 0)
		cookie = 1;
	ioat_chan->common.cookie = new->async_tx.cookie = cookie;

	ioat_chan->dmacount += desc_count;
	ioat_chan->pending += desc_count;
	if (ioat_chan->pending >= ioat_pending_level)
		__ioat2_dma_memcpy_issue_pending(ioat_chan);
	spin_unlock_bh(&ioat_chan->desc_lock);
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655 656 657
	return cookie;
}

658 659 660 661 662
/**
 * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
 * @ioat_chan: the channel supplying the memory pool for the descriptors
 * @flags: allocation flags
 */
663
static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
664 665
					struct ioat_dma_chan *ioat_chan,
					gfp_t flags)
666 667 668
{
	struct ioat_dma_descriptor *desc;
	struct ioat_desc_sw *desc_sw;
669
	struct ioatdma_device *ioatdma_device;
670 671
	dma_addr_t phys;

672 673
	ioatdma_device = to_ioatdma_device(ioat_chan->common.device);
	desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
674 675 676 677 678
	if (unlikely(!desc))
		return NULL;

	desc_sw = kzalloc(sizeof(*desc_sw), flags);
	if (unlikely(!desc_sw)) {
679
		pci_pool_free(ioatdma_device->dma_pool, desc, phys);
680 681 682 683
		return NULL;
	}

	memset(desc, 0, sizeof(*desc));
684
	dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common);
685 686 687 688 689
	switch (ioat_chan->device->version) {
	case IOAT_VER_1_2:
		desc_sw->async_tx.tx_submit = ioat1_tx_submit;
		break;
	case IOAT_VER_2_0:
690
	case IOAT_VER_3_0:
691 692 693
		desc_sw->async_tx.tx_submit = ioat2_tx_submit;
		break;
	}
694
	INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
695

696
	desc_sw->hw = desc;
697
	desc_sw->async_tx.phys = phys;
698 699 700 701

	return desc_sw;
}

702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736
static int ioat_initial_desc_count = 256;
module_param(ioat_initial_desc_count, int, 0644);
MODULE_PARM_DESC(ioat_initial_desc_count,
		 "initial descriptors per channel (default: 256)");

/**
 * ioat2_dma_massage_chan_desc - link the descriptors into a circle
 * @ioat_chan: the channel to be massaged
 */
static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan)
{
	struct ioat_desc_sw *desc, *_desc;

	/* setup used_desc */
	ioat_chan->used_desc.next = ioat_chan->free_desc.next;
	ioat_chan->used_desc.prev = NULL;

	/* pull free_desc out of the circle so that every node is a hw
	 * descriptor, but leave it pointing to the list
	 */
	ioat_chan->free_desc.prev->next = ioat_chan->free_desc.next;
	ioat_chan->free_desc.next->prev = ioat_chan->free_desc.prev;

	/* circle link the hw descriptors */
	desc = to_ioat_desc(ioat_chan->free_desc.next);
	desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
	list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) {
		desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
	}
}

/**
 * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors
 * @chan: the channel to be filled out
 */
737
static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
738 739
{
	struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
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	struct ioat_desc_sw *desc;
741 742 743 744 745
	u16 chanctrl;
	u32 chanerr;
	int i;
	LIST_HEAD(tmp_list);

746 747
	/* have we already been set up? */
	if (!list_empty(&ioat_chan->free_desc))
748
		return ioat_chan->desccount;
749

750
	/* Setup register to interrupt and write completion status on error */
751
	chanctrl = IOAT_CHANCTRL_ERR_INT_EN |
752 753
		IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
		IOAT_CHANCTRL_ERR_COMPLETION_EN;
754
	writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
755

756
	chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
757
	if (chanerr) {
758
		dev_err(&ioat_chan->device->pdev->dev,
759
			"CHANERR = %x, clearing\n", chanerr);
760
		writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
761 762 763
	}

	/* Allocate descriptors */
764
	for (i = 0; i < ioat_initial_desc_count; i++) {
765 766
		desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
		if (!desc) {
767
			dev_err(&ioat_chan->device->pdev->dev,
768
				"Only %d initial descriptors\n", i);
769 770 771 772 773
			break;
		}
		list_add_tail(&desc->node, &tmp_list);
	}
	spin_lock_bh(&ioat_chan->desc_lock);
774
	ioat_chan->desccount = i;
775
	list_splice(&tmp_list, &ioat_chan->free_desc);
776 777
	if (ioat_chan->device->version != IOAT_VER_1_2)
		ioat2_dma_massage_chan_desc(ioat_chan);
778 779 780 781 782 783
	spin_unlock_bh(&ioat_chan->desc_lock);

	/* allocate a completion writeback area */
	/* doing 2 32bit writes to mmio since 1 64b write doesn't work */
	ioat_chan->completion_virt =
		pci_pool_alloc(ioat_chan->device->completion_pool,
784 785
			       GFP_KERNEL,
			       &ioat_chan->completion_addr);
786 787
	memset(ioat_chan->completion_virt, 0,
	       sizeof(*ioat_chan->completion_virt));
788 789 790 791
	writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF,
	       ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
	writel(((u64) ioat_chan->completion_addr) >> 32,
	       ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
792

793
	tasklet_enable(&ioat_chan->cleanup_task);
794 795
	ioat_dma_start_null_desc(ioat_chan);  /* give chain to dma device */
	return ioat_chan->desccount;
796 797
}

798 799 800 801
/**
 * ioat_dma_free_chan_resources - release all the descriptors
 * @chan: the channel to be cleaned
 */
802 803 804
static void ioat_dma_free_chan_resources(struct dma_chan *chan)
{
	struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
805
	struct ioatdma_device *ioatdma_device = to_ioatdma_device(chan->device);
806 807 808
	struct ioat_desc_sw *desc, *_desc;
	int in_use_descs = 0;

809 810 811 812 813 814
	/* Before freeing channel resources first check
	 * if they have been previously allocated for this channel.
	 */
	if (ioat_chan->desccount == 0)
		return;

815
	tasklet_disable(&ioat_chan->cleanup_task);
816 817
	ioat_dma_memcpy_cleanup(ioat_chan);

818 819 820
	/* Delay 100ms after reset to allow internal DMA logic to quiesce
	 * before removing DMA descriptor resources.
	 */
821 822 823
	writeb(IOAT_CHANCMD_RESET,
	       ioat_chan->reg_base
			+ IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
824
	mdelay(100);
825 826

	spin_lock_bh(&ioat_chan->desc_lock);
827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845
	switch (ioat_chan->device->version) {
	case IOAT_VER_1_2:
		list_for_each_entry_safe(desc, _desc,
					 &ioat_chan->used_desc, node) {
			in_use_descs++;
			list_del(&desc->node);
			pci_pool_free(ioatdma_device->dma_pool, desc->hw,
				      desc->async_tx.phys);
			kfree(desc);
		}
		list_for_each_entry_safe(desc, _desc,
					 &ioat_chan->free_desc, node) {
			list_del(&desc->node);
			pci_pool_free(ioatdma_device->dma_pool, desc->hw,
				      desc->async_tx.phys);
			kfree(desc);
		}
		break;
	case IOAT_VER_2_0:
846
	case IOAT_VER_3_0:
847 848 849 850 851 852 853 854
		list_for_each_entry_safe(desc, _desc,
					 ioat_chan->free_desc.next, node) {
			list_del(&desc->node);
			pci_pool_free(ioatdma_device->dma_pool, desc->hw,
				      desc->async_tx.phys);
			kfree(desc);
		}
		desc = to_ioat_desc(ioat_chan->free_desc.next);
855
		pci_pool_free(ioatdma_device->dma_pool, desc->hw,
856
			      desc->async_tx.phys);
857
		kfree(desc);
858 859 860
		INIT_LIST_HEAD(&ioat_chan->free_desc);
		INIT_LIST_HEAD(&ioat_chan->used_desc);
		break;
861 862 863
	}
	spin_unlock_bh(&ioat_chan->desc_lock);

864
	pci_pool_free(ioatdma_device->completion_pool,
865 866
		      ioat_chan->completion_virt,
		      ioat_chan->completion_addr);
867 868 869

	/* one is ok since we left it on there on purpose */
	if (in_use_descs > 1)
870
		dev_err(&ioat_chan->device->pdev->dev,
871
			"Freeing %d in use descriptors!\n",
872 873 874
			in_use_descs - 1);

	ioat_chan->last_completion = ioat_chan->completion_addr = 0;
875
	ioat_chan->pending = 0;
876
	ioat_chan->dmacount = 0;
877
	ioat_chan->desccount = 0;
878 879 880 881
	ioat_chan->watchdog_completion = 0;
	ioat_chan->last_compl_desc_addr_hw = 0;
	ioat_chan->watchdog_tcp_cookie =
		ioat_chan->watchdog_last_tcp_cookie = 0;
882
}
883

884 885 886 887 888 889 890 891
/**
 * ioat_dma_get_next_descriptor - return the next available descriptor
 * @ioat_chan: IOAT DMA channel handle
 *
 * Gets the next descriptor from the chain, and must be called with the
 * channel's desc_lock held.  Allocates more descriptors if the channel
 * has run out.
 */
892
static struct ioat_desc_sw *
893
ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
894
{
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	struct ioat_desc_sw *new;
896 897 898 899 900 901 902

	if (!list_empty(&ioat_chan->free_desc)) {
		new = to_ioat_desc(ioat_chan->free_desc.next);
		list_del(&new->node);
	} else {
		/* try to get another desc */
		new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
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		if (!new) {
			dev_err(&ioat_chan->device->pdev->dev,
				"alloc failed\n");
			return NULL;
		}
908 909 910 911
	}

	prefetch(new->hw);
	return new;
912 913
}

914 915 916
static struct ioat_desc_sw *
ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
{
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	struct ioat_desc_sw *new;
918 919 920 921 922 923 924 925 926 927 928 929 930

	/*
	 * used.prev points to where to start processing
	 * used.next points to next free descriptor
	 * if used.prev == NULL, there are none waiting to be processed
	 * if used.next == used.prev.prev, there is only one free descriptor,
	 *      and we need to use it to as a noop descriptor before
	 *      linking in a new set of descriptors, since the device
	 *      has probably already read the pointer to it
	 */
	if (ioat_chan->used_desc.prev &&
	    ioat_chan->used_desc.next == ioat_chan->used_desc.prev->prev) {

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		struct ioat_desc_sw *desc;
		struct ioat_desc_sw *noop_desc;
933 934 935 936
		int i;

		/* set up the noop descriptor */
		noop_desc = to_ioat_desc(ioat_chan->used_desc.next);
937 938
		/* set size to non-zero value (channel returns error when size is 0) */
		noop_desc->hw->size = NULL_DESC_BUFFER_SIZE;
939 940 941 942 943 944 945 946
		noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL;
		noop_desc->hw->src_addr = 0;
		noop_desc->hw->dst_addr = 0;

		ioat_chan->used_desc.next = ioat_chan->used_desc.next->next;
		ioat_chan->pending++;
		ioat_chan->dmacount++;

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		/* try to get a few more descriptors */
948 949
		for (i = 16; i; i--) {
			desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
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950 951 952 953 954
			if (!desc) {
				dev_err(&ioat_chan->device->pdev->dev,
					"alloc failed\n");
				break;
			}
955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986
			list_add_tail(&desc->node, ioat_chan->used_desc.next);

			desc->hw->next
				= to_ioat_desc(desc->node.next)->async_tx.phys;
			to_ioat_desc(desc->node.prev)->hw->next
				= desc->async_tx.phys;
			ioat_chan->desccount++;
		}

		ioat_chan->used_desc.next = noop_desc->node.next;
	}
	new = to_ioat_desc(ioat_chan->used_desc.next);
	prefetch(new);
	ioat_chan->used_desc.next = new->node.next;

	if (ioat_chan->used_desc.prev == NULL)
		ioat_chan->used_desc.prev = &new->node;

	prefetch(new->hw);
	return new;
}

static struct ioat_desc_sw *ioat_dma_get_next_descriptor(
						struct ioat_dma_chan *ioat_chan)
{
	if (!ioat_chan)
		return NULL;

	switch (ioat_chan->device->version) {
	case IOAT_VER_1_2:
		return ioat1_dma_get_next_descriptor(ioat_chan);
	case IOAT_VER_2_0:
987
	case IOAT_VER_3_0:
988 989 990 991 992 993
		return ioat2_dma_get_next_descriptor(ioat_chan);
	}
	return NULL;
}

static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy(
994
						struct dma_chan *chan,
995 996
						dma_addr_t dma_dest,
						dma_addr_t dma_src,
997
						size_t len,
998
						unsigned long flags)
999
{
1000
	struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1001
	struct ioat_desc_sw *new;
1002 1003

	spin_lock_bh(&ioat_chan->desc_lock);
1004
	new = ioat_dma_get_next_descriptor(ioat_chan);
1005 1006
	spin_unlock_bh(&ioat_chan->desc_lock);

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1007 1008
	if (new) {
		new->len = len;
1009 1010
		new->dst = dma_dest;
		new->src = dma_src;
1011
		new->async_tx.flags = flags;
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		return &new->async_tx;
1013 1014 1015 1016
	} else {
		dev_err(&ioat_chan->device->pdev->dev,
			"chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
			chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
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		return NULL;
1018
	}
1019 1020
}

1021 1022
static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy(
						struct dma_chan *chan,
1023 1024
						dma_addr_t dma_dest,
						dma_addr_t dma_src,
1025
						size_t len,
1026
						unsigned long flags)
1027 1028 1029 1030 1031 1032 1033
{
	struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
	struct ioat_desc_sw *new;

	spin_lock_bh(&ioat_chan->desc_lock);
	new = ioat2_dma_get_next_descriptor(ioat_chan);

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1034 1035 1036 1037
	/*
	 * leave ioat_chan->desc_lock set in ioat 2 path
	 * it will get unlocked at end of tx_submit
	 */
1038

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1039 1040
	if (new) {
		new->len = len;
1041 1042
		new->dst = dma_dest;
		new->src = dma_src;
1043
		new->async_tx.flags = flags;
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		return &new->async_tx;
1045 1046 1047 1048 1049
	} else {
		spin_unlock_bh(&ioat_chan->desc_lock);
		dev_err(&ioat_chan->device->pdev->dev,
			"chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
			chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
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		return NULL;
1051
	}
1052 1053
}

1054 1055 1056 1057 1058 1059 1060 1061
static void ioat_dma_cleanup_tasklet(unsigned long data)
{
	struct ioat_dma_chan *chan = (void *)data;
	ioat_dma_memcpy_cleanup(chan);
	writew(IOAT_CHANCTRL_INT_DISABLE,
	       chan->reg_base + IOAT_CHANCTRL_OFFSET);
}

1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082
static void
ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc)
{
	/*
	 * yes we are unmapping both _page and _single
	 * alloc'd regions with unmap_page. Is this
	 * *really* that bad?
	 */
	if (!(desc->async_tx.flags & DMA_COMPL_SKIP_DEST_UNMAP))
		pci_unmap_page(ioat_chan->device->pdev,
				pci_unmap_addr(desc, dst),
				pci_unmap_len(desc, len),
				PCI_DMA_FROMDEVICE);

	if (!(desc->async_tx.flags & DMA_COMPL_SKIP_SRC_UNMAP))
		pci_unmap_page(ioat_chan->device->pdev,
				pci_unmap_addr(desc, src),
				pci_unmap_len(desc, len),
				PCI_DMA_TODEVICE);
}

1083 1084 1085 1086
/**
 * ioat_dma_memcpy_cleanup - cleanup up finished descriptors
 * @chan: ioat channel to be cleaned up
 */
1087
static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
1088 1089 1090 1091
{
	unsigned long phys_complete;
	struct ioat_desc_sw *desc, *_desc;
	dma_cookie_t cookie = 0;
1092 1093
	unsigned long desc_phys;
	struct ioat_desc_sw *latest_desc;
1094

1095
	prefetch(ioat_chan->completion_virt);
1096

1097
	if (!spin_trylock_bh(&ioat_chan->cleanup_lock))
1098 1099 1100 1101 1102 1103 1104 1105 1106
		return;

	/* The completion writeback can happen at any time,
	   so reads by the driver need to be atomic operations
	   The descriptor physical addresses are limited to 32-bits
	   when the CPU can only do a 32-bit mov */

#if (BITS_PER_LONG == 64)
	phys_complete =
1107 1108
		ioat_chan->completion_virt->full
		& IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
1109
#else
1110 1111
	phys_complete =
		ioat_chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
1112 1113
#endif

1114 1115
	if ((ioat_chan->completion_virt->full
		& IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
1116 1117
				IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
		dev_err(&ioat_chan->device->pdev->dev,
1118
			"Channel halted, chanerr = %x\n",
1119
			readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET));
1120 1121 1122 1123

		/* TODO do something to salvage the situation */
	}

1124
	if (phys_complete == ioat_chan->last_completion) {
1125
		spin_unlock_bh(&ioat_chan->cleanup_lock);
1126 1127 1128 1129
		/*
		 * perhaps we're stuck so hard that the watchdog can't go off?
		 * try to catch it after 2 seconds
		 */
1130 1131 1132 1133 1134 1135
		if (ioat_chan->device->version != IOAT_VER_3_0) {
			if (time_after(jiffies,
				       ioat_chan->last_completion_time + HZ*WATCHDOG_DELAY)) {
				ioat_dma_chan_watchdog(&(ioat_chan->device->work.work));
				ioat_chan->last_completion_time = jiffies;
			}
1136
		}
1137 1138
		return;
	}
1139
	ioat_chan->last_completion_time = jiffies;
1140

1141
	cookie = 0;
1142 1143 1144 1145 1146
	if (!spin_trylock_bh(&ioat_chan->desc_lock)) {
		spin_unlock_bh(&ioat_chan->cleanup_lock);
		return;
	}

1147 1148 1149 1150
	switch (ioat_chan->device->version) {
	case IOAT_VER_1_2:
		list_for_each_entry_safe(desc, _desc,
					 &ioat_chan->used_desc, node) {
1151

1152
			/*
1153 1154 1155
			 * Incoming DMA requests may use multiple descriptors,
			 * due to exceeding xfercap, perhaps. If so, only the
			 * last one will have a cookie, and require unmapping.
1156
			 */
1157 1158
			if (desc->async_tx.cookie) {
				cookie = desc->async_tx.cookie;
1159
				ioat_dma_unmap(ioat_chan, desc);
1160 1161 1162 1163
				if (desc->async_tx.callback) {
					desc->async_tx.callback(desc->async_tx.callback_param);
					desc->async_tx.callback = NULL;
				}
1164
			}
1165

1166 1167 1168 1169 1170
			if (desc->async_tx.phys != phys_complete) {
				/*
				 * a completed entry, but not the last, so clean
				 * up if the client is done with the descriptor
				 */
1171
				if (async_tx_test_ack(&desc->async_tx)) {
1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182
					list_del(&desc->node);
					list_add_tail(&desc->node,
						      &ioat_chan->free_desc);
				} else
					desc->async_tx.cookie = 0;
			} else {
				/*
				 * last used desc. Do not remove, so we can
				 * append from it, but don't look at it next
				 * time, either
				 */
1183
				desc->async_tx.cookie = 0;
1184

1185 1186 1187 1188 1189 1190
				/* TODO check status bits? */
				break;
			}
		}
		break;
	case IOAT_VER_2_0:
1191
	case IOAT_VER_3_0:
1192 1193
		/* has some other thread has already cleaned up? */
		if (ioat_chan->used_desc.prev == NULL)
1194
			break;
1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218

		/* work backwards to find latest finished desc */
		desc = to_ioat_desc(ioat_chan->used_desc.next);
		latest_desc = NULL;
		do {
			desc = to_ioat_desc(desc->node.prev);
			desc_phys = (unsigned long)desc->async_tx.phys
				       & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
			if (desc_phys == phys_complete) {
				latest_desc = desc;
				break;
			}
		} while (&desc->node != ioat_chan->used_desc.prev);

		if (latest_desc != NULL) {

			/* work forwards to clear finished descriptors */
			for (desc = to_ioat_desc(ioat_chan->used_desc.prev);
			     &desc->node != latest_desc->node.next &&
			     &desc->node != ioat_chan->used_desc.next;
			     desc = to_ioat_desc(desc->node.next)) {
				if (desc->async_tx.cookie) {
					cookie = desc->async_tx.cookie;
					desc->async_tx.cookie = 0;
1219
					ioat_dma_unmap(ioat_chan, desc);
1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231
					if (desc->async_tx.callback) {
						desc->async_tx.callback(desc->async_tx.callback_param);
						desc->async_tx.callback = NULL;
					}
				}
			}

			/* move used.prev up beyond those that are finished */
			if (&desc->node == ioat_chan->used_desc.next)
				ioat_chan->used_desc.prev = NULL;
			else
				ioat_chan->used_desc.prev = &desc->node;
1232
		}
1233
		break;
1234 1235
	}

1236
	spin_unlock_bh(&ioat_chan->desc_lock);
1237

1238
	ioat_chan->last_completion = phys_complete;
1239
	if (cookie != 0)
1240
		ioat_chan->completed_cookie = cookie;
1241

1242
	spin_unlock_bh(&ioat_chan->cleanup_lock);
1243 1244 1245 1246 1247 1248
}

/**
 * ioat_dma_is_complete - poll the status of a IOAT DMA transaction
 * @chan: IOAT DMA channel handle
 * @cookie: DMA transaction identifier
1249 1250
 * @done: if not %NULL, updated with last completed transaction
 * @used: if not %NULL, updated with last used transaction
1251 1252
 */
static enum dma_status ioat_dma_is_complete(struct dma_chan *chan,
1253 1254 1255
					    dma_cookie_t cookie,
					    dma_cookie_t *done,
					    dma_cookie_t *used)
1256 1257 1258 1259 1260 1261 1262 1263
{
	struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
	dma_cookie_t last_used;
	dma_cookie_t last_complete;
	enum dma_status ret;

	last_used = chan->cookie;
	last_complete = ioat_chan->completed_cookie;
1264
	ioat_chan->watchdog_tcp_cookie = cookie;
1265 1266

	if (done)
1267
		*done = last_complete;
1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280
	if (used)
		*used = last_used;

	ret = dma_async_is_complete(cookie, last_complete, last_used);
	if (ret == DMA_SUCCESS)
		return ret;

	ioat_dma_memcpy_cleanup(ioat_chan);

	last_used = chan->cookie;
	last_complete = ioat_chan->completed_cookie;

	if (done)
1281
		*done = last_complete;
1282 1283 1284 1285 1286 1287
	if (used)
		*used = last_used;

	return dma_async_is_complete(cookie, last_complete, last_used);
}

1288
static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
1289 1290 1291 1292 1293
{
	struct ioat_desc_sw *desc;

	spin_lock_bh(&ioat_chan->desc_lock);

1294
	desc = ioat_dma_get_next_descriptor(ioat_chan);
1295 1296 1297 1298 1299 1300 1301 1302

	if (!desc) {
		dev_err(&ioat_chan->device->pdev->dev,
			"Unable to start null desc - get next desc failed\n");
		spin_unlock_bh(&ioat_chan->desc_lock);
		return;
	}

1303 1304 1305
	desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL
				| IOAT_DMA_DESCRIPTOR_CTL_INT_GN
				| IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
1306 1307
	/* set size to non-zero value (channel returns error when size is 0) */
	desc->hw->size = NULL_DESC_BUFFER_SIZE;
1308 1309
	desc->hw->src_addr = 0;
	desc->hw->dst_addr = 0;
1310
	async_tx_ack(&desc->async_tx);
1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324
	switch (ioat_chan->device->version) {
	case IOAT_VER_1_2:
		desc->hw->next = 0;
		list_add_tail(&desc->node, &ioat_chan->used_desc);

		writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
		       ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
		writel(((u64) desc->async_tx.phys) >> 32,
		       ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);

		writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
			+ IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
		break;
	case IOAT_VER_2_0:
1325
	case IOAT_VER_3_0:
1326 1327 1328 1329 1330 1331 1332 1333 1334
		writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
		       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
		writel(((u64) desc->async_tx.phys) >> 32,
		       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);

		ioat_chan->dmacount++;
		__ioat2_dma_memcpy_issue_pending(ioat_chan);
		break;
	}
1335 1336 1337 1338 1339 1340 1341 1342
	spin_unlock_bh(&ioat_chan->desc_lock);
}

/*
 * Perform a IOAT transaction to verify the HW works.
 */
#define IOAT_TEST_SIZE 2000

1343 1344
static void ioat_dma_test_callback(void *dma_async_param)
{
1345 1346 1347
	struct completion *cmp = dma_async_param;

	complete(cmp);
1348 1349
}

1350 1351 1352 1353 1354
/**
 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
 * @device: device to be tested
 */
static int ioat_dma_self_test(struct ioatdma_device *device)
1355 1356 1357 1358 1359
{
	int i;
	u8 *src;
	u8 *dest;
	struct dma_chan *dma_chan;
S
Shannon Nelson 已提交
1360
	struct dma_async_tx_descriptor *tx;
1361
	dma_addr_t dma_dest, dma_src;
1362 1363
	dma_cookie_t cookie;
	int err = 0;
1364
	struct completion cmp;
1365

1366
	src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1367 1368
	if (!src)
		return -ENOMEM;
1369
	dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380
	if (!dest) {
		kfree(src);
		return -ENOMEM;
	}

	/* Fill in src buffer */
	for (i = 0; i < IOAT_TEST_SIZE; i++)
		src[i] = (u8)i;

	/* Start copy, using first DMA channel */
	dma_chan = container_of(device->common.channels.next,
1381 1382
				struct dma_chan,
				device_node);
1383
	if (device->common.device_alloc_chan_resources(dma_chan) < 1) {
1384 1385
		dev_err(&device->pdev->dev,
			"selftest cannot allocate chan resource\n");
1386 1387 1388 1389
		err = -ENODEV;
		goto out;
	}

1390 1391 1392 1393 1394 1395
	dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE,
				 DMA_TO_DEVICE);
	dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE,
				  DMA_FROM_DEVICE);
	tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
						   IOAT_TEST_SIZE, 0);
1396 1397 1398 1399 1400 1401 1402
	if (!tx) {
		dev_err(&device->pdev->dev,
			"Self-test prep failed, disabling\n");
		err = -ENODEV;
		goto free_resources;
	}

1403
	async_tx_ack(tx);
1404
	init_completion(&cmp);
1405
	tx->callback = ioat_dma_test_callback;
1406
	tx->callback_param = &cmp;
1407
	cookie = tx->tx_submit(tx);
1408 1409 1410 1411 1412 1413
	if (cookie < 0) {
		dev_err(&device->pdev->dev,
			"Self-test setup failed, disabling\n");
		err = -ENODEV;
		goto free_resources;
	}
1414
	device->common.device_issue_pending(dma_chan);
D
Dan Williams 已提交
1415

1416
	wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1417

1418 1419
	if (device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL)
					!= DMA_SUCCESS) {
1420
		dev_err(&device->pdev->dev,
1421
			"Self-test copy timed out, disabling\n");
1422 1423 1424 1425
		err = -ENODEV;
		goto free_resources;
	}
	if (memcmp(src, dest, IOAT_TEST_SIZE)) {
1426
		dev_err(&device->pdev->dev,
1427
			"Self-test copy failed compare, disabling\n");
1428 1429 1430 1431 1432
		err = -ENODEV;
		goto free_resources;
	}

free_resources:
1433
	device->common.device_free_chan_resources(dma_chan);
1434 1435 1436 1437 1438 1439
out:
	kfree(src);
	kfree(dest);
	return err;
}

1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464
static char ioat_interrupt_style[32] = "msix";
module_param_string(ioat_interrupt_style, ioat_interrupt_style,
		    sizeof(ioat_interrupt_style), 0644);
MODULE_PARM_DESC(ioat_interrupt_style,
		 "set ioat interrupt style: msix (default), "
		 "msix-single-vector, msi, intx)");

/**
 * ioat_dma_setup_interrupts - setup interrupt handler
 * @device: ioat device
 */
static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
{
	struct ioat_dma_chan *ioat_chan;
	int err, i, j, msixcnt;
	u8 intrctrl = 0;

	if (!strcmp(ioat_interrupt_style, "msix"))
		goto msix;
	if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
		goto msix_single_vector;
	if (!strcmp(ioat_interrupt_style, "msi"))
		goto msi;
	if (!strcmp(ioat_interrupt_style, "intx"))
		goto intx;
1465 1466 1467
	dev_err(&device->pdev->dev, "invalid ioat_interrupt_style %s\n",
		ioat_interrupt_style);
	goto err_no_irq;
1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597

msix:
	/* The number of MSI-X vectors should equal the number of channels */
	msixcnt = device->common.chancnt;
	for (i = 0; i < msixcnt; i++)
		device->msix_entries[i].entry = i;

	err = pci_enable_msix(device->pdev, device->msix_entries, msixcnt);
	if (err < 0)
		goto msi;
	if (err > 0)
		goto msix_single_vector;

	for (i = 0; i < msixcnt; i++) {
		ioat_chan = ioat_lookup_chan_by_index(device, i);
		err = request_irq(device->msix_entries[i].vector,
				  ioat_dma_do_interrupt_msix,
				  0, "ioat-msix", ioat_chan);
		if (err) {
			for (j = 0; j < i; j++) {
				ioat_chan =
					ioat_lookup_chan_by_index(device, j);
				free_irq(device->msix_entries[j].vector,
					 ioat_chan);
			}
			goto msix_single_vector;
		}
	}
	intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
	device->irq_mode = msix_multi_vector;
	goto done;

msix_single_vector:
	device->msix_entries[0].entry = 0;
	err = pci_enable_msix(device->pdev, device->msix_entries, 1);
	if (err)
		goto msi;

	err = request_irq(device->msix_entries[0].vector, ioat_dma_do_interrupt,
			  0, "ioat-msix", device);
	if (err) {
		pci_disable_msix(device->pdev);
		goto msi;
	}
	device->irq_mode = msix_single_vector;
	goto done;

msi:
	err = pci_enable_msi(device->pdev);
	if (err)
		goto intx;

	err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
			  0, "ioat-msi", device);
	if (err) {
		pci_disable_msi(device->pdev);
		goto intx;
	}
	/*
	 * CB 1.2 devices need a bit set in configuration space to enable MSI
	 */
	if (device->version == IOAT_VER_1_2) {
		u32 dmactrl;
		pci_read_config_dword(device->pdev,
				      IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
		dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
		pci_write_config_dword(device->pdev,
				       IOAT_PCI_DMACTRL_OFFSET, dmactrl);
	}
	device->irq_mode = msi;
	goto done;

intx:
	err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
			  IRQF_SHARED, "ioat-intx", device);
	if (err)
		goto err_no_irq;
	device->irq_mode = intx;

done:
	intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
	writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
	return 0;

err_no_irq:
	/* Disable all interrupt generation */
	writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
	dev_err(&device->pdev->dev, "no usable interrupts\n");
	device->irq_mode = none;
	return -1;
}

/**
 * ioat_dma_remove_interrupts - remove whatever interrupts were set
 * @device: ioat device
 */
static void ioat_dma_remove_interrupts(struct ioatdma_device *device)
{
	struct ioat_dma_chan *ioat_chan;
	int i;

	/* Disable all interrupt generation */
	writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);

	switch (device->irq_mode) {
	case msix_multi_vector:
		for (i = 0; i < device->common.chancnt; i++) {
			ioat_chan = ioat_lookup_chan_by_index(device, i);
			free_irq(device->msix_entries[i].vector, ioat_chan);
		}
		pci_disable_msix(device->pdev);
		break;
	case msix_single_vector:
		free_irq(device->msix_entries[0].vector, device);
		pci_disable_msix(device->pdev);
		break;
	case msi:
		free_irq(device->pdev->irq, device);
		pci_disable_msi(device->pdev);
		break;
	case intx:
		free_irq(device->pdev->irq, device);
		break;
	case none:
		dev_warn(&device->pdev->dev,
			 "call to %s without interrupts setup\n", __func__);
	}
	device->irq_mode = none;
}

1598 1599
struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
				      void __iomem *iobase)
1600 1601
{
	int err;
1602
	struct ioatdma_device *device;
1603 1604 1605 1606 1607 1608

	device = kzalloc(sizeof(*device), GFP_KERNEL);
	if (!device) {
		err = -ENOMEM;
		goto err_kzalloc;
	}
1609 1610 1611
	device->pdev = pdev;
	device->reg_base = iobase;
	device->version = readb(device->reg_base + IOAT_VER_OFFSET);
1612 1613 1614

	/* DMA coherent memory pool for DMA descriptor allocations */
	device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1615 1616
					   sizeof(struct ioat_dma_descriptor),
					   64, 0);
1617 1618 1619 1620 1621
	if (!device->dma_pool) {
		err = -ENOMEM;
		goto err_dma_pool;
	}

1622 1623 1624
	device->completion_pool = pci_pool_create("completion_pool", pdev,
						  sizeof(u64), SMP_CACHE_BYTES,
						  SMP_CACHE_BYTES);
1625 1626 1627 1628 1629 1630
	if (!device->completion_pool) {
		err = -ENOMEM;
		goto err_completion_pool;
	}

	INIT_LIST_HEAD(&device->common.channels);
1631
	ioat_dma_enumerate_channels(device);
1632

1633 1634 1635 1636
	device->common.device_alloc_chan_resources =
						ioat_dma_alloc_chan_resources;
	device->common.device_free_chan_resources =
						ioat_dma_free_chan_resources;
1637 1638 1639
	device->common.dev = &pdev->dev;

	dma_cap_set(DMA_MEMCPY, device->common.cap_mask);
1640
	device->common.device_is_tx_complete = ioat_dma_is_complete;
1641 1642 1643 1644 1645 1646 1647
	switch (device->version) {
	case IOAT_VER_1_2:
		device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
		device->common.device_issue_pending =
						ioat1_dma_memcpy_issue_pending;
		break;
	case IOAT_VER_2_0:
1648
	case IOAT_VER_3_0:
1649 1650 1651 1652 1653 1654
		device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy;
		device->common.device_issue_pending =
						ioat2_dma_memcpy_issue_pending;
		break;
	}

1655
	dev_err(&device->pdev->dev,
1656 1657 1658
		"Intel(R) I/OAT DMA Engine found,"
		" %d channels, device version 0x%02x, driver version %s\n",
		device->common.chancnt, device->version, IOAT_DMA_VERSION);
1659

1660
	err = ioat_dma_setup_interrupts(device);
1661
	if (err)
1662
		goto err_setup_interrupts;
1663

1664
	err = ioat_dma_self_test(device);
1665 1666 1667
	if (err)
		goto err_self_test;

1668 1669
	ioat_set_tcp_copy_break(device);

1670 1671
	dma_async_device_register(&device->common);

1672 1673 1674 1675 1676
	if (device->version != IOAT_VER_3_0) {
		INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog);
		schedule_delayed_work(&device->work,
				      WATCHDOG_DELAY);
	}
1677

1678
	return device;
1679 1680

err_self_test:
1681 1682
	ioat_dma_remove_interrupts(device);
err_setup_interrupts:
1683 1684 1685 1686 1687 1688
	pci_pool_destroy(device->completion_pool);
err_completion_pool:
	pci_pool_destroy(device->dma_pool);
err_dma_pool:
	kfree(device);
err_kzalloc:
1689
	dev_err(&pdev->dev,
1690
		"Intel(R) I/OAT DMA Engine initialization failed\n");
1691
	return NULL;
D
Dan Aloni 已提交
1692 1693
}

1694
void ioat_dma_remove(struct ioatdma_device *device)
1695 1696 1697 1698
{
	struct dma_chan *chan, *_chan;
	struct ioat_dma_chan *ioat_chan;

1699
	ioat_dma_remove_interrupts(device);
1700

1701 1702
	dma_async_device_unregister(&device->common);

1703 1704
	pci_pool_destroy(device->dma_pool);
	pci_pool_destroy(device->completion_pool);
1705

S
Shannon Nelson 已提交
1706 1707 1708 1709
	iounmap(device->reg_base);
	pci_release_regions(device->pdev);
	pci_disable_device(device->pdev);

1710 1711 1712
	if (device->version != IOAT_VER_3_0) {
		cancel_delayed_work(&device->work);
	}
1713

1714 1715
	list_for_each_entry_safe(chan, _chan,
				 &device->common.channels, device_node) {
1716 1717 1718 1719 1720 1721 1722
		ioat_chan = to_ioat_chan(chan);
		list_del(&chan->device_node);
		kfree(ioat_chan);
	}
	kfree(device);
}