sysfs.c 23.6 KB
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#include <linux/device.h>
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#include <linux/cpu.h>
#include <linux/smp.h>
#include <linux/percpu.h>
#include <linux/init.h>
#include <linux/sched.h>
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#include <linux/export.h>
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#include <linux/nodemask.h>
#include <linux/cpumask.h>
#include <linux/notifier.h>

#include <asm/current.h>
#include <asm/processor.h>
#include <asm/cputable.h>
#include <asm/hvcall.h>
#include <asm/prom.h>
#include <asm/machdep.h>
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#include <asm/smp.h>
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#include <asm/pmc.h>
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#include <asm/firmware.h>
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#include "cacheinfo.h"

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#ifdef CONFIG_PPC64
#include <asm/paca.h>
#include <asm/lppaca.h>
#endif

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static DEFINE_PER_CPU(struct cpu, cpu_devices);

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/*
 * SMT snooze delay stuff, 64-bit only for now
 */

#ifdef CONFIG_PPC64
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/* Time in microseconds we delay before sleeping in the idle loop */
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DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
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static ssize_t store_smt_snooze_delay(struct device *dev,
				      struct device_attribute *attr,
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				      const char *buf,
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				      size_t count)
{
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	struct cpu *cpu = container_of(dev, struct cpu, dev);
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	ssize_t ret;
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	long snooze;
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	ret = sscanf(buf, "%ld", &snooze);
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	if (ret != 1)
		return -EINVAL;

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	per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
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	return count;
}

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static ssize_t show_smt_snooze_delay(struct device *dev,
				     struct device_attribute *attr,
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				     char *buf)
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{
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	struct cpu *cpu = container_of(dev, struct cpu, dev);
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	return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
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}

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static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
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		   store_smt_snooze_delay);

static int __init setup_smt_snooze_delay(char *str)
{
	unsigned int cpu;
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	long snooze;
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	if (!cpu_has_feature(CPU_FTR_SMT))
		return 1;

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	snooze = simple_strtol(str, NULL, 10);
	for_each_possible_cpu(cpu)
		per_cpu(smt_snooze_delay, cpu) = snooze;
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	return 1;
}
__setup("smt-snooze-delay=", setup_smt_snooze_delay);

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#endif /* CONFIG_PPC64 */
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#ifdef CONFIG_PPC_FSL_BOOK3E
#define MAX_BIT				63

static u64 pw20_wt;
static u64 altivec_idle_wt;

static unsigned int get_idle_ticks_bit(u64 ns)
{
	u64 cycle;

	if (ns >= 10000)
		cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
	else
		cycle = div_u64(ns * tb_ticks_per_usec, 1000);

	if (!cycle)
		return 0;

	return ilog2(cycle);
}

static void do_show_pwrmgtcr0(void *val)
{
	u32 *value = val;

	*value = mfspr(SPRN_PWRMGTCR0);
}

static ssize_t show_pw20_state(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	u32 value;
	unsigned int cpu = dev->id;

	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);

	value &= PWRMGTCR0_PW20_WAIT;

	return sprintf(buf, "%u\n", value ? 1 : 0);
}

static void do_store_pw20_state(void *val)
{
	u32 *value = val;
	u32 pw20_state;

	pw20_state = mfspr(SPRN_PWRMGTCR0);

	if (*value)
		pw20_state |= PWRMGTCR0_PW20_WAIT;
	else
		pw20_state &= ~PWRMGTCR0_PW20_WAIT;

	mtspr(SPRN_PWRMGTCR0, pw20_state);
}

static ssize_t store_pw20_state(struct device *dev,
				struct device_attribute *attr,
				const char *buf, size_t count)
{
	u32 value;
	unsigned int cpu = dev->id;

	if (kstrtou32(buf, 0, &value))
		return -EINVAL;

	if (value > 1)
		return -EINVAL;

	smp_call_function_single(cpu, do_store_pw20_state, &value, 1);

	return count;
}

static ssize_t show_pw20_wait_time(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	u32 value;
	u64 tb_cycle = 1;
	u64 time;

	unsigned int cpu = dev->id;

	if (!pw20_wt) {
		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
		value = (value & PWRMGTCR0_PW20_ENT) >>
					PWRMGTCR0_PW20_ENT_SHIFT;

		tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
		/* convert ms to ns */
		if (tb_ticks_per_usec > 1000) {
			time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
		} else {
			u32 rem_us;

			time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
						&rem_us);
			time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
		}
	} else {
		time = pw20_wt;
	}

	return sprintf(buf, "%llu\n", time > 0 ? time : 0);
}

static void set_pw20_wait_entry_bit(void *val)
{
	u32 *value = val;
	u32 pw20_idle;

	pw20_idle = mfspr(SPRN_PWRMGTCR0);

	/* Set Automatic PW20 Core Idle Count */
	/* clear count */
	pw20_idle &= ~PWRMGTCR0_PW20_ENT;

	/* set count */
	pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);

	mtspr(SPRN_PWRMGTCR0, pw20_idle);
}

static ssize_t store_pw20_wait_time(struct device *dev,
				struct device_attribute *attr,
				const char *buf, size_t count)
{
	u32 entry_bit;
	u64 value;

	unsigned int cpu = dev->id;

	if (kstrtou64(buf, 0, &value))
		return -EINVAL;

	if (!value)
		return -EINVAL;

	entry_bit = get_idle_ticks_bit(value);
	if (entry_bit > MAX_BIT)
		return -EINVAL;

	pw20_wt = value;

	smp_call_function_single(cpu, set_pw20_wait_entry_bit,
				&entry_bit, 1);

	return count;
}

static ssize_t show_altivec_idle(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	u32 value;
	unsigned int cpu = dev->id;

	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);

	value &= PWRMGTCR0_AV_IDLE_PD_EN;

	return sprintf(buf, "%u\n", value ? 1 : 0);
}

static void do_store_altivec_idle(void *val)
{
	u32 *value = val;
	u32 altivec_idle;

	altivec_idle = mfspr(SPRN_PWRMGTCR0);

	if (*value)
		altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
	else
		altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;

	mtspr(SPRN_PWRMGTCR0, altivec_idle);
}

static ssize_t store_altivec_idle(struct device *dev,
				struct device_attribute *attr,
				const char *buf, size_t count)
{
	u32 value;
	unsigned int cpu = dev->id;

	if (kstrtou32(buf, 0, &value))
		return -EINVAL;

	if (value > 1)
		return -EINVAL;

	smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);

	return count;
}

static ssize_t show_altivec_idle_wait_time(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	u32 value;
	u64 tb_cycle = 1;
	u64 time;

	unsigned int cpu = dev->id;

	if (!altivec_idle_wt) {
		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
		value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
					PWRMGTCR0_AV_IDLE_CNT_SHIFT;

		tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
		/* convert ms to ns */
		if (tb_ticks_per_usec > 1000) {
			time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
		} else {
			u32 rem_us;

			time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
						&rem_us);
			time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
		}
	} else {
		time = altivec_idle_wt;
	}

	return sprintf(buf, "%llu\n", time > 0 ? time : 0);
}

static void set_altivec_idle_wait_entry_bit(void *val)
{
	u32 *value = val;
	u32 altivec_idle;

	altivec_idle = mfspr(SPRN_PWRMGTCR0);

	/* Set Automatic AltiVec Idle Count */
	/* clear count */
	altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;

	/* set count */
	altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);

	mtspr(SPRN_PWRMGTCR0, altivec_idle);
}

static ssize_t store_altivec_idle_wait_time(struct device *dev,
				struct device_attribute *attr,
				const char *buf, size_t count)
{
	u32 entry_bit;
	u64 value;

	unsigned int cpu = dev->id;

	if (kstrtou64(buf, 0, &value))
		return -EINVAL;

	if (!value)
		return -EINVAL;

	entry_bit = get_idle_ticks_bit(value);
	if (entry_bit > MAX_BIT)
		return -EINVAL;

	altivec_idle_wt = value;

	smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
				&entry_bit, 1);

	return count;
}

/*
 * Enable/Disable interface:
 * 0, disable. 1, enable.
 */
static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);

/*
 * Set wait time interface:(Nanosecond)
 * Example: Base on TBfreq is 41MHZ.
 * 1~48(ns): TB[63]
 * 49~97(ns): TB[62]
 * 98~195(ns): TB[61]
 * 196~390(ns): TB[60]
 * 391~780(ns): TB[59]
 * 781~1560(ns): TB[58]
 * ...
 */
static DEVICE_ATTR(pw20_wait_time, 0600,
			show_pw20_wait_time,
			store_pw20_wait_time);
static DEVICE_ATTR(altivec_idle_wait_time, 0600,
			show_altivec_idle_wait_time,
			store_altivec_idle_wait_time);
#endif

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/*
 * Enabling PMCs will slow partition context switch times so we only do
 * it the first time we write to the PMCs.
 */

static DEFINE_PER_CPU(char, pmcs_enabled);

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void ppc_enable_pmcs(void)
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{
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	ppc_set_pmu_inuse(1);

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	/* Only need to enable them once */
	if (__get_cpu_var(pmcs_enabled))
		return;

	__get_cpu_var(pmcs_enabled) = 1;

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	if (ppc_md.enable_pmcs)
		ppc_md.enable_pmcs();
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}
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EXPORT_SYMBOL(ppc_enable_pmcs);
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#define __SYSFS_SPRSETUP(NAME, ADDRESS, EXTRA) \
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static void read_##NAME(void *val) \
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{ \
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	*(unsigned long *)val = mfspr(ADDRESS);	\
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} \
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static void write_##NAME(void *val) \
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{ \
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	EXTRA; \
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	mtspr(ADDRESS, *(unsigned long *)val);	\
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} \
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static ssize_t show_##NAME(struct device *dev, \
			struct device_attribute *attr, \
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			char *buf) \
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{ \
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	struct cpu *cpu = container_of(dev, struct cpu, dev); \
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	unsigned long val; \
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	smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);	\
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	return sprintf(buf, "%lx\n", val); \
} \
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static ssize_t __used \
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	store_##NAME(struct device *dev, struct device_attribute *attr, \
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			const char *buf, size_t count) \
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{ \
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	struct cpu *cpu = container_of(dev, struct cpu, dev); \
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	unsigned long val; \
	int ret = sscanf(buf, "%lx", &val); \
	if (ret != 1) \
		return -EINVAL; \
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	smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
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	return count; \
}

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#define SYSFS_PMCSETUP(NAME, ADDRESS)	\
	__SYSFS_SPRSETUP(NAME, ADDRESS, ppc_enable_pmcs())
#define SYSFS_SPRSETUP(NAME, ADDRESS)	\
	__SYSFS_SPRSETUP(NAME, ADDRESS, )
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/* Let's define all possible registers, we'll only hook up the ones
 * that are implemented on the current processor
 */

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#if defined(CONFIG_PPC64)
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#define HAS_PPC_PMC_CLASSIC	1
#define HAS_PPC_PMC_IBM		1
#define HAS_PPC_PMC_PA6T	1
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#elif defined(CONFIG_6xx)
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#define HAS_PPC_PMC_CLASSIC	1
#define HAS_PPC_PMC_IBM		1
#define HAS_PPC_PMC_G4		1
#endif


#ifdef HAS_PPC_PMC_CLASSIC
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SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
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#ifdef HAS_PPC_PMC_G4
SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
#endif

#ifdef CONFIG_PPC64
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SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
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SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
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SYSFS_SPRSETUP(purr, SPRN_PURR);
SYSFS_SPRSETUP(spurr, SPRN_SPURR);
SYSFS_SPRSETUP(dscr, SPRN_DSCR);
SYSFS_SPRSETUP(pir, SPRN_PIR);
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/*
  Lets only enable read for phyp resources and
  enable write when needed with a separate function.
  Lets be conservative and default to pseries.
*/
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static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
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static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
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static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
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static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
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static DEVICE_ATTR(pir, 0400, show_pir, NULL);
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unsigned long dscr_default = 0;
EXPORT_SYMBOL(dscr_default);

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static void add_write_permission_dev_attr(struct device_attribute *attr)
{
	attr->attr.mode |= 0200;
}

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static ssize_t show_dscr_default(struct device *dev,
		struct device_attribute *attr, char *buf)
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{
	return sprintf(buf, "%lx\n", dscr_default);
}

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static void update_dscr(void *dummy)
{
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	if (!current->thread.dscr_inherit) {
		current->thread.dscr = dscr_default;
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		mtspr(SPRN_DSCR, dscr_default);
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	}
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}

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static ssize_t __used store_dscr_default(struct device *dev,
		struct device_attribute *attr, const char *buf,
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		size_t count)
{
	unsigned long val;
	int ret = 0;
	
	ret = sscanf(buf, "%lx", &val);
	if (ret != 1)
		return -EINVAL;
	dscr_default = val;

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	on_each_cpu(update_dscr, NULL, 1);

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	return count;
}

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static DEVICE_ATTR(dscr_default, 0600,
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		show_dscr_default, store_dscr_default);

static void sysfs_create_dscr_default(void)
{
	int err = 0;
	if (cpu_has_feature(CPU_FTR_DSCR))
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		err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
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}
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#endif /* CONFIG_PPC64 */

#ifdef HAS_PPC_PMC_PA6T
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SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
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#ifdef CONFIG_DEBUG_KERNEL
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SYSFS_SPRSETUP(hid0, SPRN_HID0);
SYSFS_SPRSETUP(hid1, SPRN_HID1);
SYSFS_SPRSETUP(hid4, SPRN_HID4);
SYSFS_SPRSETUP(hid5, SPRN_HID5);
SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
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#endif /* CONFIG_DEBUG_KERNEL */
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#endif /* HAS_PPC_PMC_PA6T */
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#ifdef HAS_PPC_PMC_IBM
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static struct device_attribute ibm_common_attrs[] = {
	__ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
	__ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
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};
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#endif /* HAS_PPC_PMC_G4 */

#ifdef HAS_PPC_PMC_G4
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static struct device_attribute g4_common_attrs[] = {
	__ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
	__ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
	__ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
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};
#endif /* HAS_PPC_PMC_G4 */
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static struct device_attribute classic_pmc_attrs[] = {
	__ATTR(pmc1, 0600, show_pmc1, store_pmc1),
	__ATTR(pmc2, 0600, show_pmc2, store_pmc2),
	__ATTR(pmc3, 0600, show_pmc3, store_pmc3),
	__ATTR(pmc4, 0600, show_pmc4, store_pmc4),
	__ATTR(pmc5, 0600, show_pmc5, store_pmc5),
	__ATTR(pmc6, 0600, show_pmc6, store_pmc6),
605
#ifdef CONFIG_PPC64
606 607
	__ATTR(pmc7, 0600, show_pmc7, store_pmc7),
	__ATTR(pmc8, 0600, show_pmc8, store_pmc8),
608
#endif
609 610
};

611
#ifdef HAS_PPC_PMC_PA6T
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static struct device_attribute pa6t_attrs[] = {
	__ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
	__ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
	__ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
	__ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
	__ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
	__ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
	__ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
	__ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
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#ifdef CONFIG_DEBUG_KERNEL
622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649
	__ATTR(hid0, 0600, show_hid0, store_hid0),
	__ATTR(hid1, 0600, show_hid1, store_hid1),
	__ATTR(hid4, 0600, show_hid4, store_hid4),
	__ATTR(hid5, 0600, show_hid5, store_hid5),
	__ATTR(ima0, 0600, show_ima0, store_ima0),
	__ATTR(ima1, 0600, show_ima1, store_ima1),
	__ATTR(ima2, 0600, show_ima2, store_ima2),
	__ATTR(ima3, 0600, show_ima3, store_ima3),
	__ATTR(ima4, 0600, show_ima4, store_ima4),
	__ATTR(ima5, 0600, show_ima5, store_ima5),
	__ATTR(ima6, 0600, show_ima6, store_ima6),
	__ATTR(ima7, 0600, show_ima7, store_ima7),
	__ATTR(ima8, 0600, show_ima8, store_ima8),
	__ATTR(ima9, 0600, show_ima9, store_ima9),
	__ATTR(imaat, 0600, show_imaat, store_imaat),
	__ATTR(btcr, 0600, show_btcr, store_btcr),
	__ATTR(pccr, 0600, show_pccr, store_pccr),
	__ATTR(rpccr, 0600, show_rpccr, store_rpccr),
	__ATTR(der, 0600, show_der, store_der),
	__ATTR(mer, 0600, show_mer, store_mer),
	__ATTR(ber, 0600, show_ber, store_ber),
	__ATTR(ier, 0600, show_ier, store_ier),
	__ATTR(sier, 0600, show_sier, store_sier),
	__ATTR(siar, 0600, show_siar, store_siar),
	__ATTR(tsr0, 0600, show_tsr0, store_tsr0),
	__ATTR(tsr1, 0600, show_tsr1, store_tsr1),
	__ATTR(tsr2, 0600, show_tsr2, store_tsr2),
	__ATTR(tsr3, 0600, show_tsr3, store_tsr3),
650
#endif /* CONFIG_DEBUG_KERNEL */
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};
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#endif /* HAS_PPC_PMC_PA6T */
#endif /* HAS_PPC_PMC_CLASSIC */
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655
static void register_cpu_online(unsigned int cpu)
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{
	struct cpu *c = &per_cpu(cpu_devices, cpu);
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	struct device *s = &c->dev;
	struct device_attribute *attrs, *pmc_attrs;
660
	int i, nattrs;
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662
#ifdef CONFIG_PPC64
663
	if (cpu_has_feature(CPU_FTR_SMT))
664
		device_create_file(s, &dev_attr_smt_snooze_delay);
665
#endif
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	/* PMC stuff */
668
	switch (cur_cpu_spec->pmc_type) {
669
#ifdef HAS_PPC_PMC_IBM
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	case PPC_PMC_IBM:
		attrs = ibm_common_attrs;
672
		nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
673
		pmc_attrs = classic_pmc_attrs;
674
		break;
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#endif /* HAS_PPC_PMC_IBM */
#ifdef HAS_PPC_PMC_G4
	case PPC_PMC_G4:
		attrs = g4_common_attrs;
679
		nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
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		pmc_attrs = classic_pmc_attrs;
		break;
#endif /* HAS_PPC_PMC_G4 */
#ifdef HAS_PPC_PMC_PA6T
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	case PPC_PMC_PA6T:
		/* PA Semi starts counting at PMC0 */
		attrs = pa6t_attrs;
687
		nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
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		pmc_attrs = NULL;
		break;
690
#endif /* HAS_PPC_PMC_PA6T */
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	default:
		attrs = NULL;
		nattrs = 0;
		pmc_attrs = NULL;
	}

	for (i = 0; i < nattrs; i++)
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		device_create_file(s, &attrs[i]);
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	if (pmc_attrs)
		for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
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			device_create_file(s, &pmc_attrs[i]);
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704
#ifdef CONFIG_PPC64
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	if (cpu_has_feature(CPU_FTR_MMCRA))
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		device_create_file(s, &dev_attr_mmcra);
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708 709 710
	if (cpu_has_feature(CPU_FTR_PURR)) {
		if (!firmware_has_feature(FW_FEATURE_LPAR))
			add_write_permission_dev_attr(&dev_attr_purr);
711
		device_create_file(s, &dev_attr_purr);
712
	}
713

714
	if (cpu_has_feature(CPU_FTR_SPURR))
715
		device_create_file(s, &dev_attr_spurr);
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717
	if (cpu_has_feature(CPU_FTR_DSCR))
718
		device_create_file(s, &dev_attr_dscr);
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	if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
721
		device_create_file(s, &dev_attr_pir);
722
#endif /* CONFIG_PPC64 */
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724 725 726 727 728 729 730 731 732
#ifdef CONFIG_PPC_FSL_BOOK3E
	if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
		device_create_file(s, &dev_attr_pw20_state);
		device_create_file(s, &dev_attr_pw20_wait_time);

		device_create_file(s, &dev_attr_altivec_idle);
		device_create_file(s, &dev_attr_altivec_idle_wait_time);
	}
#endif
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	cacheinfo_cpu_online(cpu);
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}

#ifdef CONFIG_HOTPLUG_CPU
static void unregister_cpu_online(unsigned int cpu)
{
	struct cpu *c = &per_cpu(cpu_devices, cpu);
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	struct device *s = &c->dev;
	struct device_attribute *attrs, *pmc_attrs;
742
	int i, nattrs;
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744
	BUG_ON(!c->hotpluggable);
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746
#ifdef CONFIG_PPC64
747
	if (cpu_has_feature(CPU_FTR_SMT))
748
		device_remove_file(s, &dev_attr_smt_snooze_delay);
749
#endif
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	/* PMC stuff */
752
	switch (cur_cpu_spec->pmc_type) {
753
#ifdef HAS_PPC_PMC_IBM
754 755
	case PPC_PMC_IBM:
		attrs = ibm_common_attrs;
756
		nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
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		pmc_attrs = classic_pmc_attrs;
		break;
#endif /* HAS_PPC_PMC_IBM */
#ifdef HAS_PPC_PMC_G4
	case PPC_PMC_G4:
		attrs = g4_common_attrs;
763
		nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
764
		pmc_attrs = classic_pmc_attrs;
765
		break;
766 767
#endif /* HAS_PPC_PMC_G4 */
#ifdef HAS_PPC_PMC_PA6T
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	case PPC_PMC_PA6T:
		/* PA Semi starts counting at PMC0 */
		attrs = pa6t_attrs;
771
		nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
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		pmc_attrs = NULL;
		break;
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#endif /* HAS_PPC_PMC_PA6T */
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	default:
		attrs = NULL;
		nattrs = 0;
		pmc_attrs = NULL;
	}
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781
	for (i = 0; i < nattrs; i++)
782
		device_remove_file(s, &attrs[i]);
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	if (pmc_attrs)
		for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
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			device_remove_file(s, &pmc_attrs[i]);
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788
#ifdef CONFIG_PPC64
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	if (cpu_has_feature(CPU_FTR_MMCRA))
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		device_remove_file(s, &dev_attr_mmcra);
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792
	if (cpu_has_feature(CPU_FTR_PURR))
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		device_remove_file(s, &dev_attr_purr);
794

795
	if (cpu_has_feature(CPU_FTR_SPURR))
796
		device_remove_file(s, &dev_attr_spurr);
797

798
	if (cpu_has_feature(CPU_FTR_DSCR))
799
		device_remove_file(s, &dev_attr_dscr);
800 801

	if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
802
		device_remove_file(s, &dev_attr_pir);
803
#endif /* CONFIG_PPC64 */
804

805 806 807 808 809 810 811 812 813
#ifdef CONFIG_PPC_FSL_BOOK3E
	if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
		device_remove_file(s, &dev_attr_pw20_state);
		device_remove_file(s, &dev_attr_pw20_wait_time);

		device_remove_file(s, &dev_attr_altivec_idle);
		device_remove_file(s, &dev_attr_altivec_idle_wait_time);
	}
#endif
814
	cacheinfo_cpu_offline(cpu);
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}
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#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
ssize_t arch_cpu_probe(const char *buf, size_t count)
{
	if (ppc_md.cpu_probe)
		return ppc_md.cpu_probe(buf, count);

	return -EINVAL;
}

ssize_t arch_cpu_release(const char *buf, size_t count)
{
	if (ppc_md.cpu_release)
		return ppc_md.cpu_release(buf, count);

	return -EINVAL;
}
#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */

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#endif /* CONFIG_HOTPLUG_CPU */

837
static int sysfs_cpu_notify(struct notifier_block *self,
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				      unsigned long action, void *hcpu)
{
	unsigned int cpu = (unsigned int)(long)hcpu;

	switch (action) {
	case CPU_ONLINE:
844
	case CPU_ONLINE_FROZEN:
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		register_cpu_online(cpu);
		break;
#ifdef CONFIG_HOTPLUG_CPU
	case CPU_DEAD:
849
	case CPU_DEAD_FROZEN:
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		unregister_cpu_online(cpu);
		break;
#endif
	}
	return NOTIFY_OK;
}

857
static struct notifier_block sysfs_cpu_nb = {
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	.notifier_call	= sysfs_cpu_notify,
};

861 862
static DEFINE_MUTEX(cpu_mutex);

863
int cpu_add_dev_attr(struct device_attribute *attr)
864 865 866 867 868 869
{
	int cpu;

	mutex_lock(&cpu_mutex);

	for_each_possible_cpu(cpu) {
870
		device_create_file(get_cpu_device(cpu), attr);
871 872 873 874 875
	}

	mutex_unlock(&cpu_mutex);
	return 0;
}
876
EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
877

878
int cpu_add_dev_attr_group(struct attribute_group *attrs)
879 880
{
	int cpu;
881
	struct device *dev;
882
	int ret;
883 884 885 886

	mutex_lock(&cpu_mutex);

	for_each_possible_cpu(cpu) {
887 888
		dev = get_cpu_device(cpu);
		ret = sysfs_create_group(&dev->kobj, attrs);
889
		WARN_ON(ret != 0);
890 891 892 893 894
	}

	mutex_unlock(&cpu_mutex);
	return 0;
}
895
EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
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898
void cpu_remove_dev_attr(struct device_attribute *attr)
899 900 901 902 903 904
{
	int cpu;

	mutex_lock(&cpu_mutex);

	for_each_possible_cpu(cpu) {
905
		device_remove_file(get_cpu_device(cpu), attr);
906 907 908 909
	}

	mutex_unlock(&cpu_mutex);
}
910
EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
911

912
void cpu_remove_dev_attr_group(struct attribute_group *attrs)
913 914
{
	int cpu;
915
	struct device *dev;
916 917 918 919

	mutex_lock(&cpu_mutex);

	for_each_possible_cpu(cpu) {
920 921
		dev = get_cpu_device(cpu);
		sysfs_remove_group(&dev->kobj, attrs);
922 923 924 925
	}

	mutex_unlock(&cpu_mutex);
}
926
EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
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/* NUMA stuff */

#ifdef CONFIG_NUMA
static void register_nodes(void)
{
	int i;

936 937
	for (i = 0; i < MAX_NUMNODES; i++)
		register_one_node(i);
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}
939

940
int sysfs_add_device_to_node(struct device *dev, int nid)
941
{
942
	struct node *node = node_devices[nid];
943
	return sysfs_create_link(&node->dev.kobj, &dev->kobj,
944 945
			kobject_name(&dev->kobj));
}
946
EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
947

948
void sysfs_remove_device_from_node(struct device *dev, int nid)
949
{
950
	struct node *node = node_devices[nid];
951
	sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
952
}
953
EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
954

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#else
static void register_nodes(void)
{
	return;
}
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#endif

/* Only valid if CPU is present. */
964 965
static ssize_t show_physical_id(struct device *dev,
				struct device_attribute *attr, char *buf)
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{
967
	struct cpu *cpu = container_of(dev, struct cpu, dev);
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969
	return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
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}
971
static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
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static int __init topology_init(void)
{
	int cpu;

	register_nodes();
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	cpu_notifier_register_begin();
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981
	for_each_possible_cpu(cpu) {
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		struct cpu *c = &per_cpu(cpu_devices, cpu);

		/*
		 * For now, we just see if the system supports making
		 * the RTAS calls for CPU hotplug.  But, there may be a
		 * more comprehensive way to do this for an individual
		 * CPU.  For instance, the boot cpu might never be valid
		 * for hotplugging.
		 */
991 992
		if (ppc_md.cpu_die)
			c->hotpluggable = 1;
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994
		if (cpu_online(cpu) || c->hotpluggable) {
995
			register_cpu(c, cpu);
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997
			device_create_file(&c->dev, &dev_attr_physical_id);
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		}

		if (cpu_online(cpu))
			register_cpu_online(cpu);
	}
1003 1004 1005 1006 1007

	__register_cpu_notifier(&sysfs_cpu_nb);

	cpu_notifier_register_done();

1008 1009 1010
#ifdef CONFIG_PPC64
	sysfs_create_dscr_default();
#endif /* CONFIG_PPC64 */
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	return 0;
}
1014
subsys_initcall(topology_init);
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