nvc0_fence.c 6.8 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_dma.h"
28 29
#include <engine/fifo.h>
#include <core/ramht.h>
30
#include "nouveau_fence.h"
31
#include "nv50_display.h"
32 33 34 35

struct nvc0_fence_priv {
	struct nouveau_fence_priv base;
	struct nouveau_bo *bo;
36
	u32 *suspend;
37 38 39 40 41
};

struct nvc0_fence_chan {
	struct nouveau_fence_chan base;
	struct nouveau_vma vma;
42
	struct nouveau_vma dispc_vma[4];
43 44
};

45 46 47 48 49 50 51
u64
nvc0_fence_crtc(struct nouveau_channel *chan, int crtc)
{
	struct nvc0_fence_chan *fctx = chan->fence;
	return fctx->dispc_vma[crtc].offset;
}

52 53 54 55
static int
nvc0_fence_emit(struct nouveau_fence *fence)
{
	struct nouveau_channel *chan = fence->channel;
56
	struct nvc0_fence_chan *fctx = chan->fence;
57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
	u64 addr = fctx->vma.offset + chan->id * 16;
	int ret;

	ret = RING_SPACE(chan, 5);
	if (ret == 0) {
		BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
		OUT_RING  (chan, upper_32_bits(addr));
		OUT_RING  (chan, lower_32_bits(addr));
		OUT_RING  (chan, fence->sequence);
		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
		FIRE_RING (chan);
	}

	return ret;
}

static int
74 75
nvc0_fence_sync(struct nouveau_fence *fence,
		struct nouveau_channel *prev, struct nouveau_channel *chan)
76
{
77
	struct nvc0_fence_chan *fctx = chan->fence;
78
	u64 addr = fctx->vma.offset + prev->id * 16;
79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97
	int ret;

	ret = RING_SPACE(chan, 5);
	if (ret == 0) {
		BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
		OUT_RING  (chan, upper_32_bits(addr));
		OUT_RING  (chan, lower_32_bits(addr));
		OUT_RING  (chan, fence->sequence);
		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
				 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
		FIRE_RING (chan);
	}

	return ret;
}

static u32
nvc0_fence_read(struct nouveau_channel *chan)
{
98 99
	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	struct nvc0_fence_priv *priv = dev_priv->fence.func;
100 101 102 103
	return nouveau_bo_rd32(priv->bo, chan->id * 16/4);
}

static void
104
nvc0_fence_context_del(struct nouveau_channel *chan)
105
{
106 107
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
108 109
	struct nvc0_fence_priv *priv = dev_priv->fence.func;
	struct nvc0_fence_chan *fctx = chan->fence;
110 111 112 113 114 115 116 117 118 119 120 121 122 123 124
	int i;

	if (dev_priv->card_type >= NV_D0) {
		for (i = 0; i < dev->mode_config.num_crtc; i++) {
			struct nouveau_bo *bo = nvd0_display_crtc_sema(dev, i);
			nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
		}
	} else
	if (dev_priv->card_type >= NV_50) {
		struct nv50_display *disp = nv50_display(dev);
		for (i = 0; i < dev->mode_config.num_crtc; i++) {
			struct nv50_display_crtc *dispc = &disp->crtc[i];
			nouveau_bo_vma_del(dispc->sem.bo, &fctx->dispc_vma[i]);
		}
	}
125 126 127

	nouveau_bo_vma_del(priv->bo, &fctx->vma);
	nouveau_fence_context_del(&fctx->base);
128
	chan->fence = NULL;
129 130 131 132
	kfree(fctx);
}

static int
133
nvc0_fence_context_new(struct nouveau_channel *chan)
134
{
135 136
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
137
	struct nvc0_fence_priv *priv = dev_priv->fence.func;
138
	struct nvc0_fence_chan *fctx;
139
	int ret, i;
140

141
	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
142 143 144 145 146 147 148
	if (!fctx)
		return -ENOMEM;

	nouveau_fence_context_new(&fctx->base);

	ret = nouveau_bo_vma_add(priv->bo, chan->vm, &fctx->vma);
	if (ret)
149
		nvc0_fence_context_del(chan);
150

151 152 153 154 155 156 157 158 159 160 161
	/* map display semaphore buffers into channel's vm */
	for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
		struct nouveau_bo *bo;
		if (dev_priv->card_type >= NV_D0)
			bo = nvd0_display_crtc_sema(dev, i);
		else
			bo = nv50_display(dev)->crtc[i].sem.bo;

		ret = nouveau_bo_vma_add(bo, chan->vm, &fctx->dispc_vma[i]);
	}

162 163 164 165
	nouveau_bo_wr32(priv->bo, chan->id * 16/4, 0x00000000);
	return ret;
}

166 167
static bool
nvc0_fence_suspend(struct drm_device *dev)
168
{
169
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
170 171
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nvc0_fence_priv *priv = dev_priv->fence.func;
172 173
	int i;

174 175
	priv->suspend = vmalloc(pfifo->channels * sizeof(u32));
	if (priv->suspend) {
176 177 178 179
		for (i = 0; i < pfifo->channels; i++)
			priv->suspend[i] = nouveau_bo_rd32(priv->bo, i);
	}

180
	return priv->suspend != NULL;
181 182
}

183 184
static void
nvc0_fence_resume(struct drm_device *dev)
185
{
186
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
187 188
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nvc0_fence_priv *priv = dev_priv->fence.func;
189 190 191 192 193 194 195 196
	int i;

	if (priv->suspend) {
		for (i = 0; i < pfifo->channels; i++)
			nouveau_bo_wr32(priv->bo, i, priv->suspend[i]);
		vfree(priv->suspend);
		priv->suspend = NULL;
	}
197 198 199
}

static void
200
nvc0_fence_destroy(struct drm_device *dev)
201 202
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
203
	struct nvc0_fence_priv *priv = dev_priv->fence.func;
204 205 206

	nouveau_bo_unmap(priv->bo);
	nouveau_bo_ref(NULL, &priv->bo);
207
	dev_priv->fence.func = NULL;
208 209 210 211 212 213
	kfree(priv);
}

int
nvc0_fence_create(struct drm_device *dev)
{
214
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
215 216 217 218 219 220 221 222
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nvc0_fence_priv *priv;
	int ret;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

223 224 225 226 227
	priv->base.dtor = nvc0_fence_destroy;
	priv->base.suspend = nvc0_fence_suspend;
	priv->base.resume = nvc0_fence_resume;
	priv->base.context_new = nvc0_fence_context_new;
	priv->base.context_del = nvc0_fence_context_del;
228 229 230
	priv->base.emit = nvc0_fence_emit;
	priv->base.sync = nvc0_fence_sync;
	priv->base.read = nvc0_fence_read;
231
	dev_priv->fence.func = priv;
232 233 234 235 236 237 238 239 240 241 242 243

	ret = nouveau_bo_new(dev, 16 * pfifo->channels, 0, TTM_PL_FLAG_VRAM,
			     0, 0, NULL, &priv->bo);
	if (ret == 0) {
		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
		if (ret == 0)
			ret = nouveau_bo_map(priv->bo);
		if (ret)
			nouveau_bo_ref(NULL, &priv->bo);
	}

	if (ret)
244
		nvc0_fence_destroy(dev);
245 246
	return ret;
}