- reg: Base address and length of each register bank used by the external IRQ pins driven by the interrupt controller hardware module. The base addresses, length and number of required register banks varies with soctype.
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in interrupts.txt in this directoryOptional properties:- any properties, listed in interrupts.txt, and any standard resource allocation properties- sense-bitfield-width: width of a single sense bitfield in the SENSE register, if different from the default 4 bits