smp_64.c 35.5 KB
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/* smp.c: Sparc64 SMP support.
 *
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 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
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 */

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#include <linux/export.h>
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#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/pagemap.h>
#include <linux/threads.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
#include <linux/cache.h>
#include <linux/jiffies.h>
#include <linux/profile.h>
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#include <linux/bootmem.h>
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#include <linux/vmalloc.h>
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#include <linux/ftrace.h>
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#include <linux/cpu.h>
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#include <linux/slab.h>
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#include <linux/kgdb.h>
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#include <asm/head.h>
#include <asm/ptrace.h>
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#include <linux/atomic.h>
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#include <asm/tlbflush.h>
#include <asm/mmu_context.h>
#include <asm/cpudata.h>
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#include <asm/hvtramp.h>
#include <asm/io.h>
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#include <asm/timer.h>
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#include <asm/setup.h>
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#include <asm/irq.h>
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#include <asm/irq_regs.h>
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#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/oplib.h>
#include <asm/uaccess.h>
#include <asm/starfire.h>
#include <asm/tlb.h>
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#include <asm/sections.h>
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#include <asm/prom.h>
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#include <asm/mdesc.h>
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#include <asm/ldc.h>
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#include <asm/hypervisor.h>
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#include <asm/pcr.h>
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#include "cpumap.h"
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#include "kernel.h"
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DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
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cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
	{ [0 ... NR_CPUS-1] = CPU_MASK_NONE };
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EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
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EXPORT_SYMBOL(cpu_core_map);

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static cpumask_t smp_commenced_mask;

void smp_info(struct seq_file *m)
{
	int i;
	
	seq_printf(m, "State:\n");
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	for_each_online_cpu(i)
		seq_printf(m, "CPU%d:\t\tonline\n", i);
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}

void smp_bogo(struct seq_file *m)
{
	int i;
	
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	for_each_online_cpu(i)
		seq_printf(m,
			   "Cpu%dClkTck\t: %016lx\n",
			   i, cpu_data(i).clock_tick);
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}

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extern void setup_sparc64_timer(void);
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static volatile unsigned long callin_flag = 0;

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void smp_callin(void)
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{
	int cpuid = hard_smp_processor_id();

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	__local_per_cpu_offset = __per_cpu_offset(cpuid);
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	if (tlb_type == hypervisor)
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		sun4v_ktsb_register();
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	__flush_tlb_all();
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	setup_sparc64_timer();
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	if (cheetah_pcache_forced_on)
		cheetah_enable_pcache();

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	callin_flag = 1;
	__asm__ __volatile__("membar #Sync\n\t"
			     "flush  %%g6" : : : "memory");

	/* Clear this or we will die instantly when we
	 * schedule back to this idler...
	 */
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	current_thread_info()->new_child = 0;
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	/* Attach to the address space of init_task. */
	atomic_inc(&init_mm.mm_count);
	current->active_mm = &init_mm;

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	/* inform the notifiers about the new cpu */
	notify_cpu_starting(cpuid);

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	while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
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		rmb();
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	set_cpu_online(cpuid, true);
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	/* idle thread is expected to have preempt disabled */
	preempt_disable();
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	local_irq_enable();

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	cpu_startup_entry(CPUHP_ONLINE);
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}

void cpu_panic(void)
{
	printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
	panic("SMP bolixed\n");
}

/* This tick register synchronization scheme is taken entirely from
 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 *
 * The only change I've made is to rework it so that the master
 * initiates the synchonization instead of the slave. -DaveM
 */

#define MASTER	0
#define SLAVE	(SMP_CACHE_BYTES/sizeof(unsigned long))

#define NUM_ROUNDS	64	/* magic value */
#define NUM_ITERS	5	/* likewise */

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static DEFINE_RAW_SPINLOCK(itc_sync_lock);
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static unsigned long go[SLAVE + 1];

#define DEBUG_TICK_SYNC	0

static inline long get_delta (long *rt, long *master)
{
	unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
	unsigned long tcenter, t0, t1, tm;
	unsigned long i;

	for (i = 0; i < NUM_ITERS; i++) {
		t0 = tick_ops->get_tick();
		go[MASTER] = 1;
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		membar_safe("#StoreLoad");
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		while (!(tm = go[SLAVE]))
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			rmb();
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		go[SLAVE] = 0;
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		wmb();
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		t1 = tick_ops->get_tick();

		if (t1 - t0 < best_t1 - best_t0)
			best_t0 = t0, best_t1 = t1, best_tm = tm;
	}

	*rt = best_t1 - best_t0;
	*master = best_tm - best_t0;

	/* average best_t0 and best_t1 without overflow: */
	tcenter = (best_t0/2 + best_t1/2);
	if (best_t0 % 2 + best_t1 % 2 == 2)
		tcenter++;
	return tcenter - best_tm;
}

void smp_synchronize_tick_client(void)
{
	long i, delta, adj, adjust_latency = 0, done = 0;
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	unsigned long flags, rt, master_time_stamp;
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#if DEBUG_TICK_SYNC
	struct {
		long rt;	/* roundtrip time */
		long master;	/* master's timestamp */
		long diff;	/* difference between midpoint and master's timestamp */
		long lat;	/* estimate of itc adjustment latency */
	} t[NUM_ROUNDS];
#endif

	go[MASTER] = 1;

	while (go[MASTER])
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		rmb();
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	local_irq_save(flags);
	{
		for (i = 0; i < NUM_ROUNDS; i++) {
			delta = get_delta(&rt, &master_time_stamp);
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			if (delta == 0)
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				done = 1;	/* let's lock on to this... */

			if (!done) {
				if (i > 0) {
					adjust_latency += -delta;
					adj = -delta + adjust_latency/4;
				} else
					adj = -delta;

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				tick_ops->add_tick(adj);
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			}
#if DEBUG_TICK_SYNC
			t[i].rt = rt;
			t[i].master = master_time_stamp;
			t[i].diff = delta;
			t[i].lat = adjust_latency/4;
#endif
		}
	}
	local_irq_restore(flags);

#if DEBUG_TICK_SYNC
	for (i = 0; i < NUM_ROUNDS; i++)
		printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
		       t[i].rt, t[i].master, t[i].diff, t[i].lat);
#endif

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	printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
	       "(last diff %ld cycles, maxerr %lu cycles)\n",
	       smp_processor_id(), delta, rt);
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}

static void smp_start_sync_tick_client(int cpu);

static void smp_synchronize_one_tick(int cpu)
{
	unsigned long flags, i;

	go[MASTER] = 0;

	smp_start_sync_tick_client(cpu);

	/* wait for client to be ready */
	while (!go[MASTER])
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		rmb();
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	/* now let the client proceed into his loop */
	go[MASTER] = 0;
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	membar_safe("#StoreLoad");
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	raw_spin_lock_irqsave(&itc_sync_lock, flags);
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	{
		for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
			while (!go[MASTER])
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				rmb();
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			go[MASTER] = 0;
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			wmb();
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			go[SLAVE] = tick_ops->get_tick();
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			membar_safe("#StoreLoad");
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		}
	}
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	raw_spin_unlock_irqrestore(&itc_sync_lock, flags);
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}

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#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
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static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg,
				void **descrp)
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{
	extern unsigned long sparc64_ttable_tl0;
	extern unsigned long kern_locked_tte_data;
	struct hvtramp_descr *hdesc;
	unsigned long trampoline_ra;
	struct trap_per_cpu *tb;
	u64 tte_vaddr, tte_data;
	unsigned long hv_err;
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	int i;
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	hdesc = kzalloc(sizeof(*hdesc) +
			(sizeof(struct hvtramp_mapping) *
			 num_kernel_image_mappings - 1),
			GFP_KERNEL);
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	if (!hdesc) {
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		printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
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		       "hvtramp_descr.\n");
		return;
	}
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	*descrp = hdesc;
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	hdesc->cpu = cpu;
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	hdesc->num_mappings = num_kernel_image_mappings;
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	tb = &trap_block[cpu];

	hdesc->fault_info_va = (unsigned long) &tb->fault_info;
	hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);

	hdesc->thread_reg = thread_reg;

	tte_vaddr = (unsigned long) KERNBASE;
	tte_data = kern_locked_tte_data;

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	for (i = 0; i < hdesc->num_mappings; i++) {
		hdesc->maps[i].vaddr = tte_vaddr;
		hdesc->maps[i].tte   = tte_data;
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		tte_vaddr += 0x400000;
		tte_data  += 0x400000;
	}

	trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);

	hv_err = sun4v_cpu_start(cpu, trampoline_ra,
				 kimage_addr_to_ra(&sparc64_ttable_tl0),
				 __pa(hdesc));
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	if (hv_err)
		printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
		       "gives error %lu\n", hv_err);
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}
#endif

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extern unsigned long sparc64_cpu_startup;

/* The OBP cpu startup callback truncates the 3rd arg cookie to
 * 32-bits (I think) so to be safe we have it read the pointer
 * contained here so we work on >4GB machines. -DaveM
 */
static struct thread_info *cpu_new_thread = NULL;

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static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle)
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{
	unsigned long entry =
		(unsigned long)(&sparc64_cpu_startup);
	unsigned long cookie =
		(unsigned long)(&cpu_new_thread);
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	void *descr = NULL;
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	int timeout, ret;
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	callin_flag = 0;
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	cpu_new_thread = task_thread_info(idle);
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	if (tlb_type == hypervisor) {
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#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
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		if (ldom_domaining_enabled)
			ldom_startcpu_cpuid(cpu,
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					    (unsigned long) cpu_new_thread,
					    &descr);
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		else
#endif
			prom_startcpu_cpuid(cpu, entry, cookie);
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	} else {
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		struct device_node *dp = of_find_node_by_cpuid(cpu);
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		prom_startcpu(dp->phandle, entry, cookie);
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	}
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	for (timeout = 0; timeout < 50000; timeout++) {
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		if (callin_flag)
			break;
		udelay(100);
	}
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	if (callin_flag) {
		ret = 0;
	} else {
		printk("Processor %d is stuck.\n", cpu);
		ret = -ENODEV;
	}
	cpu_new_thread = NULL;

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	kfree(descr);
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	return ret;
}

static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
{
	u64 result, target;
	int stuck, tmp;

	if (this_is_starfire) {
		/* map to real upaid */
		cpu = (((cpu & 0x3c) << 1) |
			((cpu & 0x40) >> 4) |
			(cpu & 0x3));
	}

	target = (cpu << 14) | 0x70;
again:
	/* Ok, this is the real Spitfire Errata #54.
	 * One must read back from a UDB internal register
	 * after writes to the UDB interrupt dispatch, but
	 * before the membar Sync for that write.
	 * So we use the high UDB control register (ASI 0x7f,
	 * ADDR 0x20) for the dummy read. -DaveM
	 */
	tmp = 0x40;
	__asm__ __volatile__(
	"wrpr	%1, %2, %%pstate\n\t"
	"stxa	%4, [%0] %3\n\t"
	"stxa	%5, [%0+%8] %3\n\t"
	"add	%0, %8, %0\n\t"
	"stxa	%6, [%0+%8] %3\n\t"
	"membar	#Sync\n\t"
	"stxa	%%g0, [%7] %3\n\t"
	"membar	#Sync\n\t"
	"mov	0x20, %%g1\n\t"
	"ldxa	[%%g1] 0x7f, %%g0\n\t"
	"membar	#Sync"
	: "=r" (tmp)
	: "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
	  "r" (data0), "r" (data1), "r" (data2), "r" (target),
	  "r" (0x10), "0" (tmp)
        : "g1");

	/* NOTE: PSTATE_IE is still clear. */
	stuck = 100000;
	do {
		__asm__ __volatile__("ldxa [%%g0] %1, %0"
			: "=r" (result)
			: "i" (ASI_INTR_DISPATCH_STAT));
		if (result == 0) {
			__asm__ __volatile__("wrpr %0, 0x0, %%pstate"
					     : : "r" (pstate));
			return;
		}
		stuck -= 1;
		if (stuck == 0)
			break;
	} while (result & 0x1);
	__asm__ __volatile__("wrpr %0, 0x0, %%pstate"
			     : : "r" (pstate));
	if (stuck == 0) {
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		printk("CPU[%d]: mondo stuckage result[%016llx]\n",
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		       smp_processor_id(), result);
	} else {
		udelay(2);
		goto again;
	}
}

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static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
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{
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	u64 *mondo, data0, data1, data2;
	u16 *cpu_list;
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	u64 pstate;
	int i;

	__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
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	cpu_list = __va(tb->cpu_list_pa);
	mondo = __va(tb->cpu_mondo_block_pa);
	data0 = mondo[0];
	data1 = mondo[1];
	data2 = mondo[2];
	for (i = 0; i < cnt; i++)
		spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
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}

/* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 * packet, but we have no use for that.  However we do take advantage of
 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 */
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static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
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{
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	int nack_busy_id, is_jbus, need_more;
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	u64 *mondo, pstate, ver, busy_mask;
	u16 *cpu_list;
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	cpu_list = __va(tb->cpu_list_pa);
	mondo = __va(tb->cpu_mondo_block_pa);
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	/* Unfortunately, someone at Sun had the brilliant idea to make the
	 * busy/nack fields hard-coded by ITID number for this Ultra-III
	 * derivative processor.
	 */
	__asm__ ("rdpr %%ver, %0" : "=r" (ver));
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	is_jbus = ((ver >> 32) == __JALAPENO_ID ||
		   (ver >> 32) == __SERRANO_ID);
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	__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));

retry:
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	need_more = 0;
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	__asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
			     : : "r" (pstate), "i" (PSTATE_IE));

	/* Setup the dispatch data registers. */
	__asm__ __volatile__("stxa	%0, [%3] %6\n\t"
			     "stxa	%1, [%4] %6\n\t"
			     "stxa	%2, [%5] %6\n\t"
			     "membar	#Sync\n\t"
			     : /* no outputs */
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			     : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
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			       "r" (0x40), "r" (0x50), "r" (0x60),
			       "i" (ASI_INTR_W));

	nack_busy_id = 0;
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	busy_mask = 0;
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	{
		int i;

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		for (i = 0; i < cnt; i++) {
			u64 target, nr;

			nr = cpu_list[i];
			if (nr == 0xffff)
				continue;
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			target = (nr << 14) | 0x70;
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			if (is_jbus) {
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				busy_mask |= (0x1UL << (nr * 2));
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			} else {
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				target |= (nack_busy_id << 24);
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				busy_mask |= (0x1UL <<
					      (nack_busy_id * 2));
			}
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			__asm__ __volatile__(
				"stxa	%%g0, [%0] %1\n\t"
				"membar	#Sync\n\t"
				: /* no outputs */
				: "r" (target), "i" (ASI_INTR_W));
			nack_busy_id++;
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			if (nack_busy_id == 32) {
				need_more = 1;
				break;
			}
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		}
	}

	/* Now, poll for completion. */
	{
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		u64 dispatch_stat, nack_mask;
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		long stuck;

		stuck = 100000 * nack_busy_id;
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		nack_mask = busy_mask << 1;
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		do {
			__asm__ __volatile__("ldxa	[%%g0] %1, %0"
					     : "=r" (dispatch_stat)
					     : "i" (ASI_INTR_DISPATCH_STAT));
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			if (!(dispatch_stat & (busy_mask | nack_mask))) {
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				__asm__ __volatile__("wrpr %0, 0x0, %%pstate"
						     : : "r" (pstate));
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				if (unlikely(need_more)) {
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					int i, this_cnt = 0;
					for (i = 0; i < cnt; i++) {
						if (cpu_list[i] == 0xffff)
							continue;
						cpu_list[i] = 0xffff;
						this_cnt++;
						if (this_cnt == 32)
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							break;
					}
					goto retry;
				}
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				return;
			}
			if (!--stuck)
				break;
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		} while (dispatch_stat & busy_mask);
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		__asm__ __volatile__("wrpr %0, 0x0, %%pstate"
				     : : "r" (pstate));

575
		if (dispatch_stat & busy_mask) {
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			/* Busy bits will not clear, continue instead
			 * of freezing up on this cpu.
			 */
579
			printk("CPU[%d]: mondo stuckage result[%016llx]\n",
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			       smp_processor_id(), dispatch_stat);
		} else {
			int i, this_busy_nack = 0;

			/* Delay some random time with interrupts enabled
			 * to prevent deadlock.
			 */
			udelay(2 * nack_busy_id);

			/* Clear out the mask bits for cpus which did not
			 * NACK us.
			 */
592 593 594 595 596 597
			for (i = 0; i < cnt; i++) {
				u64 check_mask, nr;

				nr = cpu_list[i];
				if (nr == 0xffff)
					continue;
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599
				if (is_jbus)
600
					check_mask = (0x2UL << (2*nr));
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				else
					check_mask = (0x2UL <<
						      this_busy_nack);
				if ((dispatch_stat & check_mask) == 0)
605
					cpu_list[i] = 0xffff;
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				this_busy_nack += 2;
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				if (this_busy_nack == 64)
					break;
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			}

			goto retry;
		}
	}
}

616
/* Multi-cpu list version.  */
617
static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
618
{
619
	int retries, this_cpu, prev_sent, i, saw_cpu_error;
620
	unsigned long status;
621
	u16 *cpu_list;
622

623
	this_cpu = smp_processor_id();
624

625 626
	cpu_list = __va(tb->cpu_list_pa);

627
	saw_cpu_error = 0;
628
	retries = 0;
629
	prev_sent = 0;
630
	do {
631
		int forward_progress, n_sent;
632

633 634 635 636 637 638
		status = sun4v_cpu_mondo_send(cnt,
					      tb->cpu_list_pa,
					      tb->cpu_mondo_block_pa);

		/* HV_EOK means all cpus received the xcall, we're done.  */
		if (likely(status == HV_EOK))
639
			break;
640

641 642 643 644
		/* First, see if we made any forward progress.
		 *
		 * The hypervisor indicates successful sends by setting
		 * cpu list entries to the value 0xffff.
645
		 */
646
		n_sent = 0;
647
		for (i = 0; i < cnt; i++) {
648 649
			if (likely(cpu_list[i] == 0xffff))
				n_sent++;
650 651
		}

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		forward_progress = 0;
		if (n_sent > prev_sent)
			forward_progress = 1;

		prev_sent = n_sent;

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		/* If we get a HV_ECPUERROR, then one or more of the cpus
		 * in the list are in error state.  Use the cpu_state()
		 * hypervisor call to find out which cpus are in error state.
		 */
		if (unlikely(status == HV_ECPUERROR)) {
			for (i = 0; i < cnt; i++) {
				long err;
				u16 cpu;

				cpu = cpu_list[i];
				if (cpu == 0xffff)
					continue;

				err = sun4v_cpu_state(cpu);
672 673
				if (err == HV_CPU_STATE_ERROR) {
					saw_cpu_error = (cpu + 1);
674
					cpu_list[i] = 0xffff;
675 676 677 678 679
				}
			}
		} else if (unlikely(status != HV_EWOULDBLOCK))
			goto fatal_mondo_error;

680 681 682 683 684 685 686
		/* Don't bother rewriting the CPU list, just leave the
		 * 0xffff and non-0xffff entries in there and the
		 * hypervisor will do the right thing.
		 *
		 * Only advance timeout state if we didn't make any
		 * forward progress.
		 */
687 688 689 690 691 692 693 694 695
		if (unlikely(!forward_progress)) {
			if (unlikely(++retries > 10000))
				goto fatal_mondo_timeout;

			/* Delay a little bit to let other cpus catch up
			 * on their cpu mondo queue work.
			 */
			udelay(2 * cnt);
		}
696 697
	} while (1);

698
	if (unlikely(saw_cpu_error))
699 700 701 702 703 704
		goto fatal_mondo_cpu_error;

	return;

fatal_mondo_cpu_error:
	printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
705 706
	       "(including %d) were in error state\n",
	       this_cpu, saw_cpu_error - 1);
707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726
	return;

fatal_mondo_timeout:
	printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
	       " progress after %d retries.\n",
	       this_cpu, retries);
	goto dump_cpu_list_and_out;

fatal_mondo_error:
	printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
	       this_cpu, status);
	printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
	       "mondo_block_pa(%lx)\n",
	       this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);

dump_cpu_list_and_out:
	printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
	for (i = 0; i < cnt; i++)
		printk("%u ", cpu_list[i]);
	printk("]\n");
727
}
728

729
static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
730 731 732

static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
{
733 734
	struct trap_per_cpu *tb;
	int this_cpu, i, cnt;
735
	unsigned long flags;
736 737
	u16 *cpu_list;
	u64 *mondo;
738 739 740 741 742 743 744 745 746 747 748 749

	/* We have to do this whole thing with interrupts fully disabled.
	 * Otherwise if we send an xcall from interrupt context it will
	 * corrupt both our mondo block and cpu list state.
	 *
	 * One consequence of this is that we cannot use timeout mechanisms
	 * that depend upon interrupts being delivered locally.  So, for
	 * example, we cannot sample jiffies and expect it to advance.
	 *
	 * Fortunately, udelay() uses %stick/%tick so we can use that.
	 */
	local_irq_save(flags);
750 751 752 753 754 755 756 757 758 759 760 761 762 763

	this_cpu = smp_processor_id();
	tb = &trap_block[this_cpu];

	mondo = __va(tb->cpu_mondo_block_pa);
	mondo[0] = data0;
	mondo[1] = data1;
	mondo[2] = data2;
	wmb();

	cpu_list = __va(tb->cpu_list_pa);

	/* Setup the initial cpu list.  */
	cnt = 0;
764
	for_each_cpu(i, mask) {
765 766 767 768 769 770 771 772
		if (i == this_cpu || !cpu_online(i))
			continue;
		cpu_list[cnt++] = i;
	}

	if (cnt)
		xcall_deliver_impl(tb, cnt);

773
	local_irq_restore(flags);
774
}
775

776 777
/* Send cross call to all processors mentioned in MASK_P
 * except self.  Really, there are only two cases currently,
778
 * "cpu_online_mask" and "mm_cpumask(mm)".
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 */
780
static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
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{
	u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));

784 785
	xcall_deliver(data0, data1, data2, mask);
}
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787 788 789
/* Send cross call to all processors except self. */
static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
{
790
	smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
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}

extern unsigned long xcall_sync_tick;

static void smp_start_sync_tick_client(int cpu)
{
797
	xcall_deliver((u64) &xcall_sync_tick, 0, 0,
798
		      cpumask_of(cpu));
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}

extern unsigned long xcall_call_function;

803
void arch_send_call_function_ipi_mask(const struct cpumask *mask)
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{
805
	xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
806
}
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808
extern unsigned long xcall_call_function_single;
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810 811
void arch_send_call_function_single_ipi(int cpu)
{
812
	xcall_deliver((u64) &xcall_call_function_single, 0, 0,
813
		      cpumask_of(cpu));
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}

816
void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs)
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{
818 819 820
	clear_softint(1 << irq);
	generic_smp_call_function_interrupt();
}
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822
void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs)
823
{
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	clear_softint(1 << irq);
825
	generic_smp_call_function_single_interrupt();
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}

828 829
static void tsb_sync(void *info)
{
830
	struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
831 832
	struct mm_struct *mm = info;

833
	/* It is not valid to test "current->active_mm == mm" here.
834 835 836 837 838 839
	 *
	 * The value of "current" is not changed atomically with
	 * switch_mm().  But that's OK, we just need to check the
	 * current cpu's trap block PGD physical address.
	 */
	if (tp->pgd_paddr == __pa(mm->pgd))
840 841 842 843 844
		tsb_context_switch(mm);
}

void smp_tsb_sync(struct mm_struct *mm)
{
845
	smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
846 847
}

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extern unsigned long xcall_flush_tlb_mm;
849
extern unsigned long xcall_flush_tlb_page;
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extern unsigned long xcall_flush_tlb_kernel_range;
851
extern unsigned long xcall_fetch_glob_regs;
852 853
extern unsigned long xcall_fetch_glob_pmu;
extern unsigned long xcall_fetch_glob_pmu_n4;
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extern unsigned long xcall_receive_signal;
855
extern unsigned long xcall_new_mmu_context_version;
856 857 858
#ifdef CONFIG_KGDB
extern unsigned long xcall_kgdb_capture;
#endif
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#ifdef DCACHE_ALIASING_POSSIBLE
extern unsigned long xcall_flush_dcache_page_cheetah;
#endif
extern unsigned long xcall_flush_dcache_page_spitfire;

865
static inline void __local_flush_dcache_page(struct page *page)
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{
#ifdef DCACHE_ALIASING_POSSIBLE
	__flush_dcache_page(page_address(page),
			    ((tlb_type == spitfire) &&
			     page_mapping(page) != NULL));
#else
	if (page_mapping(page) != NULL &&
	    tlb_type == spitfire)
		__flush_icache_page(__pa(page_address(page)));
#endif
}

void smp_flush_dcache_page_impl(struct page *page, int cpu)
{
880 881 882 883
	int this_cpu;

	if (tlb_type == hypervisor)
		return;
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#ifdef CONFIG_DEBUG_DCFLUSH
	atomic_inc(&dcpage_flushes);
#endif
888 889 890

	this_cpu = get_cpu();

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	if (cpu == this_cpu) {
		__local_flush_dcache_page(page);
	} else if (cpu_online(cpu)) {
		void *pg_addr = page_address(page);
895
		u64 data0 = 0;
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		if (tlb_type == spitfire) {
898
			data0 = ((u64)&xcall_flush_dcache_page_spitfire);
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			if (page_mapping(page) != NULL)
				data0 |= ((u64)1 << 32);
901
		} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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#ifdef DCACHE_ALIASING_POSSIBLE
903
			data0 =	((u64)&xcall_flush_dcache_page_cheetah);
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#endif
		}
906 907
		if (data0) {
			xcall_deliver(data0, __pa(pg_addr),
908
				      (u64) pg_addr, cpumask_of(cpu));
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#ifdef CONFIG_DEBUG_DCFLUSH
910
			atomic_inc(&dcpage_flushes_xcall);
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#endif
912
		}
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	}

	put_cpu();
}

void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
{
920 921
	void *pg_addr;
	u64 data0;
922 923 924 925

	if (tlb_type == hypervisor)
		return;

926
	preempt_disable();
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#ifdef CONFIG_DEBUG_DCFLUSH
	atomic_inc(&dcpage_flushes);
#endif
931 932
	data0 = 0;
	pg_addr = page_address(page);
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	if (tlb_type == spitfire) {
		data0 = ((u64)&xcall_flush_dcache_page_spitfire);
		if (page_mapping(page) != NULL)
			data0 |= ((u64)1 << 32);
937
	} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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#ifdef DCACHE_ALIASING_POSSIBLE
		data0 = ((u64)&xcall_flush_dcache_page_cheetah);
#endif
	}
942 943
	if (data0) {
		xcall_deliver(data0, __pa(pg_addr),
944
			      (u64) pg_addr, cpu_online_mask);
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#ifdef CONFIG_DEBUG_DCFLUSH
946
		atomic_inc(&dcpage_flushes_xcall);
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947
#endif
948
	}
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	__local_flush_dcache_page(page);

951
	preempt_enable();
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}

954
void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
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{
956
	struct mm_struct *mm;
957
	unsigned long flags;
958

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	clear_softint(1 << irq);
960 961 962 963 964

	/* See if we need to allocate a new TLB context because
	 * the version of the one we are using is now out of date.
	 */
	mm = current->active_mm;
965 966
	if (unlikely(!mm || (mm == &init_mm)))
		return;
967

968
	spin_lock_irqsave(&mm->context.lock, flags);
969

970 971
	if (unlikely(!CTX_VALID(mm->context)))
		get_new_mmu_context(mm);
972

973
	spin_unlock_irqrestore(&mm->context.lock, flags);
974

975 976 977
	load_secondary_context(mm);
	__flush_tlb_mm(CTX_HWBITS(mm->context),
		       SECONDARY_CONTEXT);
978 979 980 981
}

void smp_new_mmu_context_version(void)
{
982
	smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
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}

985 986 987 988 989 990 991
#ifdef CONFIG_KGDB
void kgdb_roundup_cpus(unsigned long flags)
{
	smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
}
#endif

992 993 994 995 996
void smp_fetch_global_regs(void)
{
	smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
}

997 998 999 1000 1001 1002 1003 1004 1005
void smp_fetch_global_pmu(void)
{
	if (tlb_type == hypervisor &&
	    sun4v_chip_type >= SUN4V_CHIP_NIAGARA4)
		smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0);
	else
		smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0);
}

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/* We know that the window frames of the user have been flushed
 * to the stack before we get here because all callers of us
 * are flush_tlb_*() routines, and these run after flush_cache_*()
 * which performs the flushw.
 *
 * The SMP TLB coherency scheme we use works as follows:
 *
 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
 *    space has (potentially) executed on, this is the heuristic
 *    we use to avoid doing cross calls.
 *
 *    Also, for flushing from kswapd and also for clones, we
 *    use cpu_vm_mask as the list of cpus to make run the TLB.
 *
 * 2) TLB context numbers are shared globally across all processors
 *    in the system, this allows us to play several games to avoid
 *    cross calls.
 *
 *    One invariant is that when a cpu switches to a process, and
 *    that processes tsk->active_mm->cpu_vm_mask does not have the
 *    current cpu's bit set, that tlb context is flushed locally.
 *
 *    If the address space is non-shared (ie. mm->count == 1) we avoid
 *    cross calls when we want to flush the currently running process's
 *    tlb state.  This is done by clearing all cpu bits except the current
1031
 *    processor's in current->mm->cpu_vm_mask and performing the
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 *    flush locally only.  This will force any subsequent cpus which run
 *    this task to flush the context from the local tlb if the process
 *    migrates to another cpu (again).
 *
 * 3) For shared address spaces (threads) and swapping we bite the
 *    bullet for most cases and perform the cross call (but only to
 *    the cpus listed in cpu_vm_mask).
 *
 *    The performance gain from "optimizing" away the cross call for threads is
 *    questionable (in theory the big win for threads is the massive sharing of
 *    address space state across processors).
 */
1044 1045 1046 1047 1048

/* This currently is only used by the hugetlb arch pre-fault
 * hook on UltraSPARC-III+ and later when changing the pagesize
 * bits of the context register for an address space.
 */
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void smp_flush_tlb_mm(struct mm_struct *mm)
{
1051 1052
	u32 ctx = CTX_HWBITS(mm->context);
	int cpu = get_cpu();
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1054
	if (atomic_read(&mm->mm_users) == 1) {
1055
		cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1056 1057
		goto local_flush_and_out;
	}
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1059 1060
	smp_cross_call_masked(&xcall_flush_tlb_mm,
			      ctx, 0, 0,
1061
			      mm_cpumask(mm));
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1063 1064
local_flush_and_out:
	__flush_tlb_mm(ctx, SECONDARY_CONTEXT);
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1065

1066
	put_cpu();
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1067 1068
}

1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081
struct tlb_pending_info {
	unsigned long ctx;
	unsigned long nr;
	unsigned long *vaddrs;
};

static void tlb_pending_func(void *info)
{
	struct tlb_pending_info *t = info;

	__flush_tlb_pending(t->ctx, t->nr, t->vaddrs);
}

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void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
{
	u32 ctx = CTX_HWBITS(mm->context);
1085
	struct tlb_pending_info info;
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	int cpu = get_cpu();

1088 1089 1090 1091
	info.ctx = ctx;
	info.nr = nr;
	info.vaddrs = vaddrs;

1092
	if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1093
		cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1094
	else
1095 1096
		smp_call_function_many(mm_cpumask(mm), tlb_pending_func,
				       &info, 1);
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	__flush_tlb_pending(ctx, nr, vaddrs);

	put_cpu();
}

1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118
void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr)
{
	unsigned long context = CTX_HWBITS(mm->context);
	int cpu = get_cpu();

	if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
		cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
	else
		smp_cross_call_masked(&xcall_flush_tlb_page,
				      context, vaddr, 0,
				      mm_cpumask(mm));
	__flush_tlb_page(context, vaddr);

	put_cpu();
}

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void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	start &= PAGE_MASK;
	end    = PAGE_ALIGN(end);
	if (start != end) {
		smp_cross_call(&xcall_flush_tlb_kernel_range,
			       0, start, end);

		__flush_tlb_kernel_range(start, end);
	}
}

/* CPU capture. */
/* #define CAPTURE_DEBUG */
extern unsigned long xcall_capture;

static atomic_t smp_capture_depth = ATOMIC_INIT(0);
static atomic_t smp_capture_registry = ATOMIC_INIT(0);
static unsigned long penguins_are_doing_time;

void smp_capture(void)
{
	int result = atomic_add_ret(1, &smp_capture_depth);

	if (result == 1) {
		int ncpus = num_online_cpus();

#ifdef CAPTURE_DEBUG
		printk("CPU[%d]: Sending penguins to jail...",
		       smp_processor_id());
#endif
		penguins_are_doing_time = 1;
		atomic_inc(&smp_capture_registry);
		smp_cross_call(&xcall_capture, 0, 0, 0);
		while (atomic_read(&smp_capture_registry) != ncpus)
1154
			rmb();
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#ifdef CAPTURE_DEBUG
		printk("done\n");
#endif
	}
}

void smp_release(void)
{
	if (atomic_dec_and_test(&smp_capture_depth)) {
#ifdef CAPTURE_DEBUG
		printk("CPU[%d]: Giving pardon to "
		       "imprisoned penguins\n",
		       smp_processor_id());
#endif
		penguins_are_doing_time = 0;
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		membar_safe("#StoreLoad");
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		atomic_dec(&smp_capture_registry);
	}
}

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/* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
 * set, so they can service tlb flush xcalls...
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 */
extern void prom_world(int);
1179

1180
void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs)
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{
	clear_softint(1 << irq);

	preempt_disable();

	__asm__ __volatile__("flushw");
	prom_world(1);
	atomic_inc(&smp_capture_registry);
1189
	membar_safe("#StoreLoad");
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	while (penguins_are_doing_time)
1191
		rmb();
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	atomic_dec(&smp_capture_registry);
	prom_world(0);

	preempt_enable();
}

/* /proc/profile writes can call this, don't __init it please. */
int setup_profiling_timer(unsigned int multiplier)
{
1201
	return -EINVAL;
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}

void __init smp_prepare_cpus(unsigned int max_cpus)
{
}

1208
void smp_prepare_boot_cpu(void)
1209 1210 1211
{
}

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void __init smp_setup_processor_id(void)
{
	if (tlb_type == spitfire)
1215
		xcall_deliver_impl = spitfire_xcall_deliver;
1216
	else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1217
		xcall_deliver_impl = cheetah_xcall_deliver;
1218
	else
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		xcall_deliver_impl = hypervisor_xcall_deliver;
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}

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void smp_fill_in_sib_core_maps(void)
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{
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	unsigned int i;

1226
	for_each_present_cpu(i) {
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		unsigned int j;

1229
		cpumask_clear(&cpu_core_map[i]);
1230
		if (cpu_data(i).core_id == 0) {
1231
			cpumask_set_cpu(i, &cpu_core_map[i]);
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			continue;
		}

1235
		for_each_present_cpu(j) {
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			if (cpu_data(i).core_id ==
			    cpu_data(j).core_id)
1238
				cpumask_set_cpu(j, &cpu_core_map[i]);
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		}
	}

1242
	for_each_present_cpu(i) {
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		unsigned int j;

1245
		cpumask_clear(&per_cpu(cpu_sibling_map, i));
1246
		if (cpu_data(i).proc_id == -1) {
1247
			cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i));
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			continue;
		}

1251
		for_each_present_cpu(j) {
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			if (cpu_data(i).proc_id ==
			    cpu_data(j).proc_id)
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				cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i));
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		}
	}
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}

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int __cpu_up(unsigned int cpu, struct task_struct *tidle)
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{
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	int ret = smp_boot_one_cpu(cpu, tidle);
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	if (!ret) {
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		cpumask_set_cpu(cpu, &smp_commenced_mask);
		while (!cpu_online(cpu))
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			mb();
1267
		if (!cpu_online(cpu)) {
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			ret = -ENODEV;
		} else {
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			/* On SUN4V, writes to %tick and %stick are
			 * not allowed.
			 */
			if (tlb_type != hypervisor)
				smp_synchronize_one_tick(cpu);
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		}
	}
	return ret;
}

1280
#ifdef CONFIG_HOTPLUG_CPU
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void cpu_play_dead(void)
{
	int cpu = smp_processor_id();
	unsigned long pstate;

	idle_task_exit();

	if (tlb_type == hypervisor) {
		struct trap_per_cpu *tb = &trap_block[cpu];

		sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
				tb->cpu_mondo_pa, 0);
		sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
				tb->dev_mondo_pa, 0);
		sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
				tb->resum_mondo_pa, 0);
		sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
				tb->nonresum_mondo_pa, 0);
	}

1301
	cpumask_clear_cpu(cpu, &smp_commenced_mask);
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	membar_safe("#Sync");

	local_irq_disable();

	__asm__ __volatile__(
		"rdpr	%%pstate, %0\n\t"
		"wrpr	%0, %1, %%pstate"
		: "=r" (pstate)
		: "i" (PSTATE_IE));

	while (1)
		barrier();
}

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int __cpu_disable(void)
{
1318 1319 1320 1321
	int cpu = smp_processor_id();
	cpuinfo_sparc *c;
	int i;

1322 1323 1324
	for_each_cpu(i, &cpu_core_map[cpu])
		cpumask_clear_cpu(cpu, &cpu_core_map[i]);
	cpumask_clear(&cpu_core_map[cpu]);
1325

1326 1327 1328
	for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
		cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
	cpumask_clear(&per_cpu(cpu_sibling_map, cpu));
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	c = &cpu_data(cpu);

	c->core_id = 0;
	c->proc_id = -1;

	smp_wmb();

	/* Make sure no interrupts point to this cpu.  */
	fixup_irqs();

	local_irq_enable();
	mdelay(1);
	local_irq_disable();

1344
	set_cpu_online(cpu, false);
1345

1346 1347
	cpu_map_rebuild();

1348
	return 0;
1349 1350 1351 1352
}

void __cpu_die(unsigned int cpu)
{
1353 1354 1355 1356
	int i;

	for (i = 0; i < 100; i++) {
		smp_rmb();
1357
		if (!cpumask_test_cpu(cpu, &smp_commenced_mask))
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			break;
		msleep(100);
	}
1361
	if (cpumask_test_cpu(cpu, &smp_commenced_mask)) {
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		printk(KERN_ERR "CPU %u didn't die...\n", cpu);
	} else {
#if defined(CONFIG_SUN_LDOMS)
		unsigned long hv_err;
		int limit = 100;

		do {
			hv_err = sun4v_cpu_stop(cpu);
			if (hv_err == HV_EOK) {
1371
				set_cpu_present(cpu, false);
1372 1373 1374 1375 1376 1377 1378 1379 1380
				break;
			}
		} while (--limit > 0);
		if (limit <= 0) {
			printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
			       hv_err);
		}
#endif
	}
1381 1382 1383
}
#endif

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void __init smp_cpus_done(unsigned int max_cpus)
{
}

void smp_send_reschedule(int cpu)
{
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	if (cpu == smp_processor_id()) {
		WARN_ON_ONCE(preemptible());
		set_softint(1 << PIL_SMP_RECEIVE_SIGNAL);
	} else {
		xcall_deliver((u64) &xcall_receive_signal,
			      0, 0, cpumask_of(cpu));
	}
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}

1399
void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
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{
	clear_softint(1 << irq);
1402
	scheduler_ipi();
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}

/* This is a nop because we capture all other cpus
 * anyways when making the PROM active.
 */
void smp_send_stop(void)
{
}

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/**
 * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
 * @cpu: cpu to allocate for
 * @size: size allocation in bytes
 * @align: alignment
 *
 * Allocate @size bytes aligned at @align for cpu @cpu.  This wrapper
 * does the right thing for NUMA regardless of the current
 * configuration.
 *
 * RETURNS:
 * Pointer to the allocated area on success, NULL on failure.
 */
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static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size,
					size_t align)
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{
	const unsigned long goal = __pa(MAX_DMA_ADDRESS);
#ifdef CONFIG_NEED_MULTIPLE_NODES
	int node = cpu_to_node(cpu);
	void *ptr;

	if (!node_online(node) || !NODE_DATA(node)) {
		ptr = __alloc_bootmem(size, align, goal);
		pr_info("cpu %d has no node %d or node-local memory\n",
			cpu, node);
		pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
			 cpu, size, __pa(ptr));
	} else {
		ptr = __alloc_bootmem_node(NODE_DATA(node),
					   size, align, goal);
		pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
			 "%016lx\n", cpu, size, node, __pa(ptr));
	}
	return ptr;
#else
	return __alloc_bootmem(size, align, goal);
#endif
}

1451
static void __init pcpu_free_bootmem(void *ptr, size_t size)
1452
{
1453 1454
	free_bootmem(__pa(ptr), size);
}
1455

1456
static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
1457 1458 1459 1460 1461
{
	if (cpu_to_node(from) == cpu_to_node(to))
		return LOCAL_DISTANCE;
	else
		return REMOTE_DISTANCE;
1462 1463
}

1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486
static void __init pcpu_populate_pte(unsigned long addr)
{
	pgd_t *pgd = pgd_offset_k(addr);
	pud_t *pud;
	pmd_t *pmd;

	pud = pud_offset(pgd, addr);
	if (pud_none(*pud)) {
		pmd_t *new;

		new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
		pud_populate(&init_mm, pud, new);
	}

	pmd = pmd_offset(pud, addr);
	if (!pmd_present(*pmd)) {
		pte_t *new;

		new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
		pmd_populate_kernel(&init_mm, pmd, new);
	}
}

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void __init setup_per_cpu_areas(void)
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{
1489 1490
	unsigned long delta;
	unsigned int cpu;
1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510
	int rc = -EINVAL;

	if (pcpu_chosen_fc != PCPU_FC_PAGE) {
		rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
					    PERCPU_DYNAMIC_RESERVE, 4 << 20,
					    pcpu_cpu_distance,
					    pcpu_alloc_bootmem,
					    pcpu_free_bootmem);
		if (rc)
			pr_warning("PERCPU: %s allocator failed (%d), "
				   "falling back to page size\n",
				   pcpu_fc_names[pcpu_chosen_fc], rc);
	}
	if (rc < 0)
		rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE,
					   pcpu_alloc_bootmem,
					   pcpu_free_bootmem,
					   pcpu_populate_pte);
	if (rc < 0)
		panic("cannot initialize percpu area (err=%d)", rc);
1511

1512
	delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
1513 1514
	for_each_possible_cpu(cpu)
		__per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu];
1515 1516 1517

	/* Setup %g5 for the boot cpu.  */
	__local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1518 1519 1520

	of_fill_in_cpu_data();
	if (tlb_type == hypervisor)
1521
		mdesc_fill_in_cpu_data(cpu_all_mask);
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}
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