intel_overlay.c 39.7 KB
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/*
 * Copyright © 2009
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Daniel Vetter <daniel@ffwll.ch>
 *
 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
 */
#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_drv.h"

/* Limits for overlay size. According to intel doc, the real limits are:
 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
 * the mininum of both.  */
#define IMAGE_MAX_WIDTH		2048
#define IMAGE_MAX_HEIGHT	2046 /* 2 * 1023 */
/* on 830 and 845 these large limits result in the card hanging */
#define IMAGE_MAX_WIDTH_LEGACY	1024
#define IMAGE_MAX_HEIGHT_LEGACY	1088

/* overlay register definitions */
/* OCMD register */
#define OCMD_TILED_SURFACE	(0x1<<19)
#define OCMD_MIRROR_MASK	(0x3<<17)
#define OCMD_MIRROR_MODE	(0x3<<17)
#define OCMD_MIRROR_HORIZONTAL	(0x1<<17)
#define OCMD_MIRROR_VERTICAL	(0x2<<17)
#define OCMD_MIRROR_BOTH	(0x3<<17)
#define OCMD_BYTEORDER_MASK	(0x3<<14) /* zero for YUYV or FOURCC YUY2 */
#define OCMD_UV_SWAP		(0x1<<14) /* YVYU */
#define OCMD_Y_SWAP		(0x2<<14) /* UYVY or FOURCC UYVY */
#define OCMD_Y_AND_UV_SWAP	(0x3<<14) /* VYUY */
#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
#define OCMD_RGB_888		(0x1<<10) /* not in i965 Intel docs */
#define OCMD_RGB_555		(0x2<<10) /* not in i965 Intel docs */
#define OCMD_RGB_565		(0x3<<10) /* not in i965 Intel docs */
#define OCMD_YUV_422_PACKED	(0x8<<10)
#define OCMD_YUV_411_PACKED	(0x9<<10) /* not in i965 Intel docs */
#define OCMD_YUV_420_PLANAR	(0xc<<10)
#define OCMD_YUV_422_PLANAR	(0xd<<10)
#define OCMD_YUV_410_PLANAR	(0xe<<10) /* also 411 */
#define OCMD_TVSYNCFLIP_PARITY	(0x1<<9)
#define OCMD_TVSYNCFLIP_ENABLE	(0x1<<7)
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#define OCMD_BUF_TYPE_MASK	(0x1<<5)
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#define OCMD_BUF_TYPE_FRAME	(0x0<<5)
#define OCMD_BUF_TYPE_FIELD	(0x1<<5)
#define OCMD_TEST_MODE		(0x1<<4)
#define OCMD_BUFFER_SELECT	(0x3<<2)
#define OCMD_BUFFER0		(0x0<<2)
#define OCMD_BUFFER1		(0x1<<2)
#define OCMD_FIELD_SELECT	(0x1<<2)
#define OCMD_FIELD0		(0x0<<1)
#define OCMD_FIELD1		(0x1<<1)
#define OCMD_ENABLE		(0x1<<0)

/* OCONFIG register */
#define OCONF_PIPE_MASK		(0x1<<18)
#define OCONF_PIPE_A		(0x0<<18)
#define OCONF_PIPE_B		(0x1<<18)
#define OCONF_GAMMA2_ENABLE	(0x1<<16)
#define OCONF_CSC_MODE_BT601	(0x0<<5)
#define OCONF_CSC_MODE_BT709	(0x1<<5)
#define OCONF_CSC_BYPASS	(0x1<<4)
#define OCONF_CC_OUT_8BIT	(0x1<<3)
#define OCONF_TEST_MODE		(0x1<<2)
#define OCONF_THREE_LINE_BUFFER	(0x1<<0)
#define OCONF_TWO_LINE_BUFFER	(0x0<<0)

/* DCLRKM (dst-key) register */
#define DST_KEY_ENABLE		(0x1<<31)
#define CLK_RGB24_MASK		0x0
#define CLK_RGB16_MASK		0x070307
#define CLK_RGB15_MASK		0x070707
#define CLK_RGB8I_MASK		0xffffff

#define RGB16_TO_COLORKEY(c) \
	(((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
#define RGB15_TO_COLORKEY(c) \
	(((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))

/* overlay flip addr flag */
#define OFC_UPDATE		0x1

/* polyphase filter coefficients */
#define N_HORIZ_Y_TAPS          5
#define N_VERT_Y_TAPS           3
#define N_HORIZ_UV_TAPS         3
#define N_VERT_UV_TAPS          3
#define N_PHASES                17
#define MAX_TAPS                5

/* memory bufferd overlay registers */
struct overlay_registers {
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	u32 OBUF_0Y;
	u32 OBUF_1Y;
	u32 OBUF_0U;
	u32 OBUF_0V;
	u32 OBUF_1U;
	u32 OBUF_1V;
	u32 OSTRIDE;
	u32 YRGB_VPH;
	u32 UV_VPH;
	u32 HORZ_PH;
	u32 INIT_PHS;
	u32 DWINPOS;
	u32 DWINSZ;
	u32 SWIDTH;
	u32 SWIDTHSW;
	u32 SHEIGHT;
	u32 YRGBSCALE;
	u32 UVSCALE;
	u32 OCLRC0;
	u32 OCLRC1;
	u32 DCLRKV;
	u32 DCLRKM;
	u32 SCLRKVH;
	u32 SCLRKVL;
	u32 SCLRKEN;
	u32 OCONFIG;
	u32 OCMD;
	u32 RESERVED1; /* 0x6C */
	u32 OSTART_0Y;
	u32 OSTART_1Y;
	u32 OSTART_0U;
	u32 OSTART_0V;
	u32 OSTART_1U;
	u32 OSTART_1V;
	u32 OTILEOFF_0Y;
	u32 OTILEOFF_1Y;
	u32 OTILEOFF_0U;
	u32 OTILEOFF_0V;
	u32 OTILEOFF_1U;
	u32 OTILEOFF_1V;
	u32 FASTHSCALE; /* 0xA0 */
	u32 UVSCALEV; /* 0xA4 */
	u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
	u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
	u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
	u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
	u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
	u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
	u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
	u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
	u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
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};

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struct intel_overlay {
	struct drm_device *dev;
	struct intel_crtc *crtc;
	struct drm_i915_gem_object *vid_bo;
	struct drm_i915_gem_object *old_vid_bo;
	int active;
	int pfit_active;
	u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
	u32 color_key;
	u32 brightness, contrast, saturation;
	u32 old_xscale, old_yscale;
	/* register access */
	u32 flip_addr;
	struct drm_i915_gem_object *reg_bo;
	/* flip handling */
	uint32_t last_flip_req;
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	void (*flip_tail)(struct intel_overlay *);
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};
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static struct overlay_registers __iomem *
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intel_overlay_map_regs(struct intel_overlay *overlay)
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{
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	drm_i915_private_t *dev_priv = overlay->dev->dev_private;
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	struct overlay_registers __iomem *regs;
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	if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
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		regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_obj->handle->vaddr;
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	else
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		regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
					 overlay->reg_bo->gtt_offset);
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	return regs;
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}
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static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
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				     struct overlay_registers __iomem *regs)
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{
	if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
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		io_mapping_unmap(regs);
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}

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static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
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					 struct drm_i915_gem_request *request,
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					 void (*tail)(struct intel_overlay *))
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{
	struct drm_device *dev = overlay->dev;
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	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
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	int ret;
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	BUG_ON(overlay->last_flip_req);
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	ret = i915_add_request(ring, NULL, request);
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	if (ret) {
	    kfree(request);
	    return ret;
	}
	overlay->last_flip_req = request->seqno;
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	overlay->flip_tail = tail;
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	ret = i915_wait_seqno(ring, overlay->last_flip_req);
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	if (ret)
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		return ret;
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	i915_gem_retire_requests(dev);
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	overlay->last_flip_req = 0;
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	return 0;
}

/* overlay needs to be disable in OCMD reg */
static int intel_overlay_on(struct intel_overlay *overlay)
{
	struct drm_device *dev = overlay->dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
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	struct drm_i915_gem_request *request;
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	int ret;

	BUG_ON(overlay->active);
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	overlay->active = 1;
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	WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
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	request = kzalloc(sizeof(*request), GFP_KERNEL);
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	if (request == NULL) {
		ret = -ENOMEM;
		goto out;
	}
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	ret = intel_ring_begin(ring, 4);
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	if (ret) {
		kfree(request);
		goto out;
	}

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	intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
	intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
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	ret = intel_overlay_do_wait_request(overlay, request, NULL);
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out:
	return ret;
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}

/* overlay needs to be enabled in OCMD reg */
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static int intel_overlay_continue(struct intel_overlay *overlay,
				  bool load_polyphase_filter)
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{
	struct drm_device *dev = overlay->dev;
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	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
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	struct drm_i915_gem_request *request;
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	u32 flip_addr = overlay->flip_addr;
	u32 tmp;
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	int ret;
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	BUG_ON(!overlay->active);

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	request = kzalloc(sizeof(*request), GFP_KERNEL);
	if (request == NULL)
		return -ENOMEM;

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	if (load_polyphase_filter)
		flip_addr |= OFC_UPDATE;

	/* check for underruns */
	tmp = I915_READ(DOVSTA);
	if (tmp & (1 << 17))
		DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);

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	ret = intel_ring_begin(ring, 2);
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	if (ret) {
		kfree(request);
		return ret;
	}
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	intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
	intel_ring_emit(ring, flip_addr);
	intel_ring_advance(ring);
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	ret = i915_add_request(ring, NULL, request);
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	if (ret) {
		kfree(request);
		return ret;
	}

	overlay->last_flip_req = request->seqno;
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	return 0;
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}

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static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
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{
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	struct drm_i915_gem_object *obj = overlay->old_vid_bo;
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	i915_gem_object_unpin(obj);
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	drm_gem_object_unreference(&obj->base);
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	overlay->old_vid_bo = NULL;
}
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static void intel_overlay_off_tail(struct intel_overlay *overlay)
{
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	struct drm_i915_gem_object *obj = overlay->vid_bo;
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	/* never have the overlay hw on without showing a frame */
	BUG_ON(!overlay->vid_bo);
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	i915_gem_object_unpin(obj);
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	drm_gem_object_unreference(&obj->base);
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	overlay->vid_bo = NULL;
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	overlay->crtc->overlay = NULL;
	overlay->crtc = NULL;
	overlay->active = 0;
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}

/* overlay needs to be disabled in OCMD reg */
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static int intel_overlay_off(struct intel_overlay *overlay)
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{
	struct drm_device *dev = overlay->dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
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	u32 flip_addr = overlay->flip_addr;
	struct drm_i915_gem_request *request;
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	int ret;
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	BUG_ON(!overlay->active);

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	request = kzalloc(sizeof(*request), GFP_KERNEL);
	if (request == NULL)
		return -ENOMEM;

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	/* According to intel docs the overlay hw may hang (when switching
	 * off) without loading the filter coeffs. It is however unclear whether
	 * this applies to the disabling of the overlay or to the switching off
	 * of the hw. Do it in both cases */
	flip_addr |= OFC_UPDATE;

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	ret = intel_ring_begin(ring, 6);
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	if (ret) {
		kfree(request);
		return ret;
	}
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	/* wait for overlay to go idle */
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	intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
	intel_ring_emit(ring, flip_addr);
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
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	/* turn overlay off */
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	intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
	intel_ring_emit(ring, flip_addr);
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
	intel_ring_advance(ring);
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	return intel_overlay_do_wait_request(overlay, request,
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					     intel_overlay_off_tail);
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}

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/* recover from an interruption due to a signal
 * We have to be careful not to repeat work forever an make forward progess. */
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static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
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{
	struct drm_device *dev = overlay->dev;
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	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
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	int ret;

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	if (overlay->last_flip_req == 0)
		return 0;
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	ret = i915_wait_seqno(ring, overlay->last_flip_req);
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	if (ret)
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		return ret;
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	i915_gem_retire_requests(dev);
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	if (overlay->flip_tail)
		overlay->flip_tail(overlay);
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	overlay->last_flip_req = 0;
	return 0;
}

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/* Wait for pending overlay flip and release old frame.
 * Needs to be called before the overlay register are changed
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 * via intel_overlay_(un)map_regs
 */
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static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
{
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	struct drm_device *dev = overlay->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
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	int ret;

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	/* Only wait if there is actually an old frame to release to
	 * guarantee forward progress.
	 */
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	if (!overlay->old_vid_bo)
		return 0;

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	if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
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		struct drm_i915_gem_request *request;
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		/* synchronous slowpath */
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		request = kzalloc(sizeof(*request), GFP_KERNEL);
		if (request == NULL)
			return -ENOMEM;
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		ret = intel_ring_begin(ring, 2);
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		if (ret) {
			kfree(request);
			return ret;
		}

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		intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
		intel_ring_emit(ring, MI_NOOP);
		intel_ring_advance(ring);
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		ret = intel_overlay_do_wait_request(overlay, request,
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						    intel_overlay_release_old_vid_tail);
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		if (ret)
			return ret;
	}
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	intel_overlay_release_old_vid_tail(overlay);
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	return 0;
}

struct put_image_params {
	int format;
	short dst_x;
	short dst_y;
	short dst_w;
	short dst_h;
	short src_w;
	short src_scan_h;
	short src_scan_w;
	short src_h;
	short stride_Y;
	short stride_UV;
	int offset_Y;
	int offset_U;
	int offset_V;
};

static int packed_depth_bytes(u32 format)
{
	switch (format & I915_OVERLAY_DEPTH_MASK) {
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	case I915_OVERLAY_YUV422:
		return 4;
	case I915_OVERLAY_YUV411:
		/* return 6; not implemented */
	default:
		return -EINVAL;
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	}
}

static int packed_width_bytes(u32 format, short width)
{
	switch (format & I915_OVERLAY_DEPTH_MASK) {
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	case I915_OVERLAY_YUV422:
		return width << 1;
	default:
		return -EINVAL;
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	}
}

static int uv_hsubsampling(u32 format)
{
	switch (format & I915_OVERLAY_DEPTH_MASK) {
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	case I915_OVERLAY_YUV422:
	case I915_OVERLAY_YUV420:
		return 2;
	case I915_OVERLAY_YUV411:
	case I915_OVERLAY_YUV410:
		return 4;
	default:
		return -EINVAL;
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	}
}

static int uv_vsubsampling(u32 format)
{
	switch (format & I915_OVERLAY_DEPTH_MASK) {
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	case I915_OVERLAY_YUV420:
	case I915_OVERLAY_YUV410:
		return 2;
	case I915_OVERLAY_YUV422:
	case I915_OVERLAY_YUV411:
		return 1;
	default:
		return -EINVAL;
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	}
}

static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
{
	u32 mask, shift, ret;
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	if (IS_GEN2(dev)) {
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		mask = 0x1f;
		shift = 5;
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	} else {
		mask = 0x3f;
		shift = 6;
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	}
	ret = ((offset + width + mask) >> shift) - (offset >> shift);
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	if (!IS_GEN2(dev))
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		ret <<= 1;
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	ret -= 1;
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	return ret << 2;
}

static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
	0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
	0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
	0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
	0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
	0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
	0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
	0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
	0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
	0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
	0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
	0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
	0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
	0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
	0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
	0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
	0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
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	0xb000, 0x3000, 0x0800, 0x3000, 0xb000
};

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static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
	0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
	0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
	0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
	0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
	0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
	0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
	0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
	0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
C
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569 570
	0x3000, 0x0800, 0x3000
};
571

572
static void update_polyphase_filter(struct overlay_registers __iomem *regs)
573
{
574 575 576
	memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
	memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
		    sizeof(uv_static_hcoeffs));
577 578 579
}

static bool update_scaling_factors(struct intel_overlay *overlay,
580
				   struct overlay_registers __iomem *regs,
581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603
				   struct put_image_params *params)
{
	/* fixed point with a 12 bit shift */
	u32 xscale, yscale, xscale_UV, yscale_UV;
#define FP_SHIFT 12
#define FRACT_MASK 0xfff
	bool scale_changed = false;
	int uv_hscale = uv_hsubsampling(params->format);
	int uv_vscale = uv_vsubsampling(params->format);

	if (params->dst_w > 1)
		xscale = ((params->src_scan_w - 1) << FP_SHIFT)
			/(params->dst_w);
	else
		xscale = 1 << FP_SHIFT;

	if (params->dst_h > 1)
		yscale = ((params->src_scan_h - 1) << FP_SHIFT)
			/(params->dst_h);
	else
		yscale = 1 << FP_SHIFT;

	/*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
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604 605 606 607 608
	xscale_UV = xscale/uv_hscale;
	yscale_UV = yscale/uv_vscale;
	/* make the Y scale to UV scale ratio an exact multiply */
	xscale = xscale_UV * uv_hscale;
	yscale = yscale_UV * uv_vscale;
609
	/*} else {
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610 611 612
	  xscale_UV = 0;
	  yscale_UV = 0;
	  }*/
613 614 615 616 617 618

	if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
		scale_changed = true;
	overlay->old_xscale = xscale;
	overlay->old_yscale = yscale;

619 620 621 622
	iowrite32(((yscale & FRACT_MASK) << 20) |
		  ((xscale >> FP_SHIFT)  << 16) |
		  ((xscale & FRACT_MASK) << 3),
		 &regs->YRGBSCALE);
C
Chris Wilson 已提交
623

624 625 626 627
	iowrite32(((yscale_UV & FRACT_MASK) << 20) |
		  ((xscale_UV >> FP_SHIFT)  << 16) |
		  ((xscale_UV & FRACT_MASK) << 3),
		 &regs->UVSCALE);
C
Chris Wilson 已提交
628

629 630 631
	iowrite32((((yscale    >> FP_SHIFT) << 16) |
		   ((yscale_UV >> FP_SHIFT) << 0)),
		 &regs->UVSCALEV);
632 633 634 635 636 637 638 639

	if (scale_changed)
		update_polyphase_filter(regs);

	return scale_changed;
}

static void update_colorkey(struct intel_overlay *overlay,
640
			    struct overlay_registers __iomem *regs)
641 642
{
	u32 key = overlay->color_key;
643

644
	switch (overlay->crtc->base.fb->bits_per_pixel) {
C
Chris Wilson 已提交
645
	case 8:
646 647
		iowrite32(0, &regs->DCLRKV);
		iowrite32(CLK_RGB8I_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
648 649
		break;

C
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650 651
	case 16:
		if (overlay->crtc->base.fb->depth == 15) {
652 653 654
			iowrite32(RGB15_TO_COLORKEY(key), &regs->DCLRKV);
			iowrite32(CLK_RGB15_MASK | DST_KEY_ENABLE,
				  &regs->DCLRKM);
C
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655
		} else {
656 657 658
			iowrite32(RGB16_TO_COLORKEY(key), &regs->DCLRKV);
			iowrite32(CLK_RGB16_MASK | DST_KEY_ENABLE,
				  &regs->DCLRKM);
C
Chris Wilson 已提交
659
		}
660 661
		break;

C
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662 663
	case 24:
	case 32:
664 665
		iowrite32(key, &regs->DCLRKV);
		iowrite32(CLK_RGB24_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
666
		break;
667 668 669 670 671 672 673 674 675
	}
}

static u32 overlay_cmd_reg(struct put_image_params *params)
{
	u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;

	if (params->format & I915_OVERLAY_YUV_PLANAR) {
		switch (params->format & I915_OVERLAY_DEPTH_MASK) {
C
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676 677 678 679 680 681 682 683 684 685
		case I915_OVERLAY_YUV422:
			cmd |= OCMD_YUV_422_PLANAR;
			break;
		case I915_OVERLAY_YUV420:
			cmd |= OCMD_YUV_420_PLANAR;
			break;
		case I915_OVERLAY_YUV411:
		case I915_OVERLAY_YUV410:
			cmd |= OCMD_YUV_410_PLANAR;
			break;
686 687 688
		}
	} else { /* YUV packed */
		switch (params->format & I915_OVERLAY_DEPTH_MASK) {
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689 690 691 692 693 694
		case I915_OVERLAY_YUV422:
			cmd |= OCMD_YUV_422_PACKED;
			break;
		case I915_OVERLAY_YUV411:
			cmd |= OCMD_YUV_411_PACKED;
			break;
695 696 697
		}

		switch (params->format & I915_OVERLAY_SWAP_MASK) {
C
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698 699 700 701 702 703 704 705 706 707 708
		case I915_OVERLAY_NO_SWAP:
			break;
		case I915_OVERLAY_UV_SWAP:
			cmd |= OCMD_UV_SWAP;
			break;
		case I915_OVERLAY_Y_SWAP:
			cmd |= OCMD_Y_SWAP;
			break;
		case I915_OVERLAY_Y_AND_UV_SWAP:
			cmd |= OCMD_Y_AND_UV_SWAP;
			break;
709 710 711 712 713 714
		}
	}

	return cmd;
}

715
static int intel_overlay_do_put_image(struct intel_overlay *overlay,
716
				      struct drm_i915_gem_object *new_bo,
717
				      struct put_image_params *params)
718 719
{
	int ret, tmp_width;
720
	struct overlay_registers __iomem *regs;
721 722
	bool scale_changed = false;
	struct drm_device *dev = overlay->dev;
723
	u32 swidth, swidthsw, sheight, ostride;
724 725 726 727 728 729 730 731 732

	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
	BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
	BUG_ON(!overlay);

	ret = intel_overlay_release_old_vid(overlay);
	if (ret != 0)
		return ret;

733
	ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
734 735 736
	if (ret != 0)
		return ret;

737 738 739 740
	ret = i915_gem_object_put_fence(new_bo);
	if (ret)
		goto out_unpin;

741
	if (!overlay->active) {
742
		u32 oconfig;
743
		regs = intel_overlay_map_regs(overlay);
744 745 746 747
		if (!regs) {
			ret = -ENOMEM;
			goto out_unpin;
		}
748
		oconfig = OCONF_CC_OUT_8BIT;
749
		if (IS_GEN4(overlay->dev))
750 751
			oconfig |= OCONF_CSC_MODE_BT709;
		oconfig |= overlay->crtc->pipe == 0 ?
752
			OCONF_PIPE_A : OCONF_PIPE_B;
753
		iowrite32(oconfig, &regs->OCONFIG);
754
		intel_overlay_unmap_regs(overlay, regs);
755 756 757 758 759 760

		ret = intel_overlay_on(overlay);
		if (ret != 0)
			goto out_unpin;
	}

761
	regs = intel_overlay_map_regs(overlay);
762 763 764 765 766
	if (!regs) {
		ret = -ENOMEM;
		goto out_unpin;
	}

767 768
	iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
	iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
769 770 771 772 773 774

	if (params->format & I915_OVERLAY_YUV_PACKED)
		tmp_width = packed_width_bytes(params->format, params->src_w);
	else
		tmp_width = params->src_w;

775 776 777 778 779
	swidth = params->src_w;
	swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width);
	sheight = params->src_h;
	iowrite32(new_bo->gtt_offset + params->offset_Y, &regs->OBUF_0Y);
	ostride = params->stride_Y;
780 781 782 783 784

	if (params->format & I915_OVERLAY_YUV_PLANAR) {
		int uv_hscale = uv_hsubsampling(params->format);
		int uv_vscale = uv_vsubsampling(params->format);
		u32 tmp_U, tmp_V;
785
		swidth |= (params->src_w/uv_hscale) << 16;
786
		tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
C
Chris Wilson 已提交
787
				      params->src_w/uv_hscale);
788
		tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
C
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789
				      params->src_w/uv_hscale);
790 791 792 793 794
		swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
		sheight |= (params->src_h/uv_vscale) << 16;
		iowrite32(new_bo->gtt_offset + params->offset_U, &regs->OBUF_0U);
		iowrite32(new_bo->gtt_offset + params->offset_V, &regs->OBUF_0V);
		ostride |= params->stride_UV << 16;
795 796
	}

797 798 799 800 801
	iowrite32(swidth, &regs->SWIDTH);
	iowrite32(swidthsw, &regs->SWIDTHSW);
	iowrite32(sheight, &regs->SHEIGHT);
	iowrite32(ostride, &regs->OSTRIDE);

802 803 804 805
	scale_changed = update_scaling_factors(overlay, regs, params);

	update_colorkey(overlay, regs);

806
	iowrite32(overlay_cmd_reg(params), &regs->OCMD);
807

808
	intel_overlay_unmap_regs(overlay, regs);
809

C
Chris Wilson 已提交
810 811 812
	ret = intel_overlay_continue(overlay, scale_changed);
	if (ret)
		goto out_unpin;
813 814

	overlay->old_vid_bo = overlay->vid_bo;
815
	overlay->vid_bo = new_bo;
816 817 818 819 820 821 822 823

	return 0;

out_unpin:
	i915_gem_object_unpin(new_bo);
	return ret;
}

824
int intel_overlay_switch_off(struct intel_overlay *overlay)
825
{
826
	struct overlay_registers __iomem *regs;
827
	struct drm_device *dev = overlay->dev;
828
	int ret;
829 830 831 832

	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
	BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));

833
	ret = intel_overlay_recover_from_interrupt(overlay);
834 835
	if (ret != 0)
		return ret;
836

837 838 839 840 841 842 843
	if (!overlay->active)
		return 0;

	ret = intel_overlay_release_old_vid(overlay);
	if (ret != 0)
		return ret;

844
	regs = intel_overlay_map_regs(overlay);
845
	iowrite32(0, &regs->OCMD);
846
	intel_overlay_unmap_regs(overlay, regs);
847

848
	ret = intel_overlay_off(overlay);
849 850 851
	if (ret != 0)
		return ret;

852
	intel_overlay_off_tail(overlay);
853 854 855 856 857 858
	return 0;
}

static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
					  struct intel_crtc *crtc)
{
C
Chris Wilson 已提交
859
	drm_i915_private_t *dev_priv = overlay->dev->dev_private;
860

861
	if (!crtc->active)
862 863 864
		return -EINVAL;

	/* can't use the overlay with double wide pipe */
865
	if (INTEL_INFO(overlay->dev)->gen < 4 &&
866
	    (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
867 868 869 870 871 872 873 874
		return -EINVAL;

	return 0;
}

static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
{
	struct drm_device *dev = overlay->dev;
C
Chris Wilson 已提交
875
	drm_i915_private_t *dev_priv = dev->dev_private;
876
	u32 pfit_control = I915_READ(PFIT_CONTROL);
877
	u32 ratio;
878 879

	/* XXX: This is not the same logic as in the xorg driver, but more in
880 881
	 * line with the intel documentation for the i965
	 */
882
	if (INTEL_INFO(dev)->gen >= 4) {
883
		/* on i965 use the PGM reg to read out the autoscaler values */
884 885
		ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
	} else {
886 887
		if (pfit_control & VERT_AUTO_SCALE)
			ratio = I915_READ(PFIT_AUTO_RATIOS);
888
		else
889 890
			ratio = I915_READ(PFIT_PGM_RATIOS);
		ratio >>= PFIT_VERT_SCALE_SHIFT;
891 892 893 894 895 896 897 898 899 900
	}

	overlay->pfit_vscale_ratio = ratio;
}

static int check_overlay_dst(struct intel_overlay *overlay,
			     struct drm_intel_overlay_put_image *rec)
{
	struct drm_display_mode *mode = &overlay->crtc->base.mode;

901 902 903 904
	if (rec->dst_x < mode->hdisplay &&
	    rec->dst_x + rec->dst_width <= mode->hdisplay &&
	    rec->dst_y < mode->vdisplay &&
	    rec->dst_y + rec->dst_height <= mode->vdisplay)
905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926
		return 0;
	else
		return -EINVAL;
}

static int check_overlay_scaling(struct put_image_params *rec)
{
	u32 tmp;

	/* downscaling limit is 8.0 */
	tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
	if (tmp > 7)
		return -EINVAL;
	tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
	if (tmp > 7)
		return -EINVAL;

	return 0;
}

static int check_overlay_src(struct drm_device *dev,
			     struct drm_intel_overlay_put_image *rec,
927
			     struct drm_i915_gem_object *new_bo)
928 929 930
{
	int uv_hscale = uv_hsubsampling(rec->flags);
	int uv_vscale = uv_vsubsampling(rec->flags);
931 932 933
	u32 stride_mask;
	int depth;
	u32 tmp;
934 935 936

	/* check src dimensions */
	if (IS_845G(dev) || IS_I830(dev)) {
C
Chris Wilson 已提交
937
		if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
938
		    rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
939 940
			return -EINVAL;
	} else {
C
Chris Wilson 已提交
941
		if (rec->src_height > IMAGE_MAX_HEIGHT ||
942
		    rec->src_width  > IMAGE_MAX_WIDTH)
943 944
			return -EINVAL;
	}
945

946
	/* better safe than sorry, use 4 as the maximal subsampling ratio */
C
Chris Wilson 已提交
947
	if (rec->src_height < N_VERT_Y_TAPS*4 ||
948
	    rec->src_width  < N_HORIZ_Y_TAPS*4)
949 950
		return -EINVAL;

951
	/* check alignment constraints */
952
	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
C
Chris Wilson 已提交
953 954 955
	case I915_OVERLAY_RGB:
		/* not implemented */
		return -EINVAL;
956

C
Chris Wilson 已提交
957 958
	case I915_OVERLAY_YUV_PACKED:
		if (uv_vscale != 1)
959
			return -EINVAL;
960 961

		depth = packed_depth_bytes(rec->flags);
C
Chris Wilson 已提交
962 963
		if (depth < 0)
			return depth;
964

C
Chris Wilson 已提交
965 966 967 968 969 970 971 972
		/* ignore UV planes */
		rec->stride_UV = 0;
		rec->offset_U = 0;
		rec->offset_V = 0;
		/* check pixel alignment */
		if (rec->offset_Y % depth)
			return -EINVAL;
		break;
973

C
Chris Wilson 已提交
974 975
	case I915_OVERLAY_YUV_PLANAR:
		if (uv_vscale < 0 || uv_hscale < 0)
976
			return -EINVAL;
C
Chris Wilson 已提交
977 978
		/* no offset restrictions for planar formats */
		break;
979

C
Chris Wilson 已提交
980 981
	default:
		return -EINVAL;
982 983 984 985 986 987
	}

	if (rec->src_width % uv_hscale)
		return -EINVAL;

	/* stride checking */
988 989 990 991
	if (IS_I830(dev) || IS_845G(dev))
		stride_mask = 255;
	else
		stride_mask = 63;
992 993 994

	if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
		return -EINVAL;
995
	if (IS_GEN4(dev) && rec->stride_Y < 512)
996 997 998
		return -EINVAL;

	tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
999 1000
		4096 : 8192;
	if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1001 1002 1003 1004
		return -EINVAL;

	/* check buffer dimensions */
	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
C
Chris Wilson 已提交
1005 1006 1007 1008 1009 1010 1011
	case I915_OVERLAY_RGB:
	case I915_OVERLAY_YUV_PACKED:
		/* always 4 Y values per depth pixels */
		if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
			return -EINVAL;

		tmp = rec->stride_Y*rec->src_height;
1012
		if (rec->offset_Y + tmp > new_bo->base.size)
C
Chris Wilson 已提交
1013 1014 1015 1016 1017 1018 1019 1020 1021
			return -EINVAL;
		break;

	case I915_OVERLAY_YUV_PLANAR:
		if (rec->src_width > rec->stride_Y)
			return -EINVAL;
		if (rec->src_width/uv_hscale > rec->stride_UV)
			return -EINVAL;

1022
		tmp = rec->stride_Y * rec->src_height;
1023
		if (rec->offset_Y + tmp > new_bo->base.size)
C
Chris Wilson 已提交
1024
			return -EINVAL;
1025 1026

		tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1027 1028
		if (rec->offset_U + tmp > new_bo->base.size ||
		    rec->offset_V + tmp > new_bo->base.size)
C
Chris Wilson 已提交
1029 1030
			return -EINVAL;
		break;
1031 1032 1033 1034 1035
	}

	return 0;
}

1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055
/**
 * Return the pipe currently connected to the panel fitter,
 * or -1 if the panel fitter is not present or not in use
 */
static int intel_panel_fitter_pipe(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32  pfit_control;

	/* i830 doesn't have a panel fitter */
	if (IS_I830(dev))
		return -1;

	pfit_control = I915_READ(PFIT_CONTROL);

	/* See if the panel fitter is in use */
	if ((pfit_control & PFIT_ENABLE) == 0)
		return -1;

	/* 965 can place panel fitter on either pipe */
1056
	if (IS_GEN4(dev))
1057 1058 1059 1060 1061 1062
		return (pfit_control >> 29) & 0x3;

	/* older chips can only use pipe 1 */
	return 1;
}

1063
int intel_overlay_put_image(struct drm_device *dev, void *data,
1064
			    struct drm_file *file_priv)
1065 1066 1067 1068 1069 1070
{
	struct drm_intel_overlay_put_image *put_image_rec = data;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_overlay *overlay;
	struct drm_mode_object *drmmode_obj;
	struct intel_crtc *crtc;
1071
	struct drm_i915_gem_object *new_bo;
1072 1073 1074
	struct put_image_params *params;
	int ret;

1075
	/* No need to check for DRIVER_MODESET - we don't set it up then. */
1076 1077 1078 1079 1080 1081 1082 1083 1084 1085
	overlay = dev_priv->overlay;
	if (!overlay) {
		DRM_DEBUG("userspace bug: no overlay\n");
		return -ENODEV;
	}

	if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
		mutex_lock(&dev->mode_config.mutex);
		mutex_lock(&dev->struct_mutex);

1086
		ret = intel_overlay_switch_off(overlay);
1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098

		mutex_unlock(&dev->struct_mutex);
		mutex_unlock(&dev->mode_config.mutex);

		return ret;
	}

	params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
	if (!params)
		return -ENOMEM;

	drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
C
Chris Wilson 已提交
1099
					   DRM_MODE_OBJECT_CRTC);
1100 1101 1102 1103
	if (!drmmode_obj) {
		ret = -ENOENT;
		goto out_free;
	}
1104 1105
	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));

1106 1107
	new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
						   put_image_rec->bo_handle));
1108
	if (&new_bo->base == NULL) {
1109 1110 1111
		ret = -ENOENT;
		goto out_free;
	}
1112 1113 1114 1115

	mutex_lock(&dev->mode_config.mutex);
	mutex_lock(&dev->struct_mutex);

1116 1117 1118 1119 1120 1121
	if (new_bo->tiling_mode) {
		DRM_ERROR("buffer used for overlay image can not be tiled\n");
		ret = -EINVAL;
		goto out_unlock;
	}

1122
	ret = intel_overlay_recover_from_interrupt(overlay);
1123 1124
	if (ret != 0)
		goto out_unlock;
1125

1126 1127
	if (overlay->crtc != crtc) {
		struct drm_display_mode *mode = &crtc->base.mode;
1128
		ret = intel_overlay_switch_off(overlay);
1129 1130 1131 1132 1133 1134 1135 1136 1137 1138
		if (ret != 0)
			goto out_unlock;

		ret = check_overlay_possible_on_crtc(overlay, crtc);
		if (ret != 0)
			goto out_unlock;

		overlay->crtc = crtc;
		crtc->overlay = overlay;

1139 1140 1141
		/* line too wide, i.e. one-line-mode */
		if (mode->hdisplay > 1024 &&
		    intel_panel_fitter_pipe(dev) == crtc->pipe) {
1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153
			overlay->pfit_active = 1;
			update_pfit_vscale_ratio(overlay);
		} else
			overlay->pfit_active = 0;
	}

	ret = check_overlay_dst(overlay, put_image_rec);
	if (ret != 0)
		goto out_unlock;

	if (overlay->pfit_active) {
		params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
C
Chris Wilson 已提交
1154
				 overlay->pfit_vscale_ratio);
1155 1156
		/* shifting right rounds downwards, so add 1 */
		params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
C
Chris Wilson 已提交
1157
				 overlay->pfit_vscale_ratio) + 1;
1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168
	} else {
		params->dst_y = put_image_rec->dst_y;
		params->dst_h = put_image_rec->dst_height;
	}
	params->dst_x = put_image_rec->dst_x;
	params->dst_w = put_image_rec->dst_width;

	params->src_w = put_image_rec->src_width;
	params->src_h = put_image_rec->src_height;
	params->src_scan_w = put_image_rec->src_scan_width;
	params->src_scan_h = put_image_rec->src_scan_height;
C
Chris Wilson 已提交
1169 1170
	if (params->src_scan_h > params->src_h ||
	    params->src_scan_w > params->src_w) {
1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203
		ret = -EINVAL;
		goto out_unlock;
	}

	ret = check_overlay_src(dev, put_image_rec, new_bo);
	if (ret != 0)
		goto out_unlock;
	params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
	params->stride_Y = put_image_rec->stride_Y;
	params->stride_UV = put_image_rec->stride_UV;
	params->offset_Y = put_image_rec->offset_Y;
	params->offset_U = put_image_rec->offset_U;
	params->offset_V = put_image_rec->offset_V;

	/* Check scaling after src size to prevent a divide-by-zero. */
	ret = check_overlay_scaling(params);
	if (ret != 0)
		goto out_unlock;

	ret = intel_overlay_do_put_image(overlay, new_bo, params);
	if (ret != 0)
		goto out_unlock;

	mutex_unlock(&dev->struct_mutex);
	mutex_unlock(&dev->mode_config.mutex);

	kfree(params);

	return 0;

out_unlock:
	mutex_unlock(&dev->struct_mutex);
	mutex_unlock(&dev->mode_config.mutex);
1204
	drm_gem_object_unreference_unlocked(&new_bo->base);
1205
out_free:
1206 1207 1208 1209 1210 1211
	kfree(params);

	return ret;
}

static void update_reg_attrs(struct intel_overlay *overlay,
1212
			     struct overlay_registers __iomem *regs)
1213
{
1214 1215 1216
	iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
		  &regs->OCLRC0);
	iowrite32(overlay->saturation, &regs->OCLRC1);
1217 1218 1219 1220 1221 1222 1223 1224 1225 1226
}

static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
{
	int i;

	if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
		return false;

	for (i = 0; i < 3; i++) {
C
Chris Wilson 已提交
1227
		if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
			return false;
	}

	return true;
}

static bool check_gamma5_errata(u32 gamma5)
{
	int i;

	for (i = 0; i < 3; i++) {
		if (((gamma5 >> i*8) & 0xff) == 0x80)
			return false;
	}

	return true;
}

static int check_gamma(struct drm_intel_overlay_attrs *attrs)
{
C
Chris Wilson 已提交
1248 1249 1250 1251 1252 1253 1254
	if (!check_gamma_bounds(0, attrs->gamma0) ||
	    !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
	    !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
	    !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
	    !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
	    !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
	    !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1255
		return -EINVAL;
C
Chris Wilson 已提交
1256

1257 1258
	if (!check_gamma5_errata(attrs->gamma5))
		return -EINVAL;
C
Chris Wilson 已提交
1259

1260 1261 1262 1263
	return 0;
}

int intel_overlay_attrs(struct drm_device *dev, void *data,
1264
			struct drm_file *file_priv)
1265 1266
{
	struct drm_intel_overlay_attrs *attrs = data;
1267
	drm_i915_private_t *dev_priv = dev->dev_private;
1268
	struct intel_overlay *overlay;
1269
	struct overlay_registers __iomem *regs;
1270 1271
	int ret;

1272
	/* No need to check for DRIVER_MODESET - we don't set it up then. */
1273 1274 1275 1276 1277 1278 1279 1280 1281
	overlay = dev_priv->overlay;
	if (!overlay) {
		DRM_DEBUG("userspace bug: no overlay\n");
		return -ENODEV;
	}

	mutex_lock(&dev->mode_config.mutex);
	mutex_lock(&dev->struct_mutex);

1282
	ret = -EINVAL;
1283
	if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1284
		attrs->color_key  = overlay->color_key;
1285
		attrs->brightness = overlay->brightness;
1286
		attrs->contrast   = overlay->contrast;
1287 1288
		attrs->saturation = overlay->saturation;

1289
		if (!IS_GEN2(dev)) {
1290 1291 1292 1293 1294 1295 1296 1297
			attrs->gamma0 = I915_READ(OGAMC0);
			attrs->gamma1 = I915_READ(OGAMC1);
			attrs->gamma2 = I915_READ(OGAMC2);
			attrs->gamma3 = I915_READ(OGAMC3);
			attrs->gamma4 = I915_READ(OGAMC4);
			attrs->gamma5 = I915_READ(OGAMC5);
		}
	} else {
1298
		if (attrs->brightness < -128 || attrs->brightness > 127)
1299
			goto out_unlock;
1300
		if (attrs->contrast > 255)
1301
			goto out_unlock;
1302
		if (attrs->saturation > 1023)
1303 1304
			goto out_unlock;

1305 1306 1307 1308
		overlay->color_key  = attrs->color_key;
		overlay->brightness = attrs->brightness;
		overlay->contrast   = attrs->contrast;
		overlay->saturation = attrs->saturation;
1309

1310
		regs = intel_overlay_map_regs(overlay);
1311 1312 1313 1314 1315 1316 1317
		if (!regs) {
			ret = -ENOMEM;
			goto out_unlock;
		}

		update_reg_attrs(overlay, regs);

1318
		intel_overlay_unmap_regs(overlay, regs);
1319 1320

		if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1321
			if (IS_GEN2(dev))
1322 1323 1324 1325 1326 1327 1328 1329
				goto out_unlock;

			if (overlay->active) {
				ret = -EBUSY;
				goto out_unlock;
			}

			ret = check_gamma(attrs);
1330
			if (ret)
1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341
				goto out_unlock;

			I915_WRITE(OGAMC0, attrs->gamma0);
			I915_WRITE(OGAMC1, attrs->gamma1);
			I915_WRITE(OGAMC2, attrs->gamma2);
			I915_WRITE(OGAMC3, attrs->gamma3);
			I915_WRITE(OGAMC4, attrs->gamma4);
			I915_WRITE(OGAMC5, attrs->gamma5);
		}
	}

1342
	ret = 0;
1343 1344 1345 1346 1347 1348 1349 1350 1351
out_unlock:
	mutex_unlock(&dev->struct_mutex);
	mutex_unlock(&dev->mode_config.mutex);

	return ret;
}

void intel_setup_overlay(struct drm_device *dev)
{
1352
	drm_i915_private_t *dev_priv = dev->dev_private;
1353
	struct intel_overlay *overlay;
1354
	struct drm_i915_gem_object *reg_bo;
1355
	struct overlay_registers __iomem *regs;
1356 1357
	int ret;

1358
	if (!HAS_OVERLAY(dev))
1359 1360 1361 1362 1363
		return;

	overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
	if (!overlay)
		return;
1364 1365 1366 1367 1368

	mutex_lock(&dev->struct_mutex);
	if (WARN_ON(dev_priv->overlay))
		goto out_free;

1369 1370
	overlay->dev = dev;

1371
	reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1372 1373
	if (!reg_bo)
		goto out_free;
1374
	overlay->reg_bo = reg_bo;
1375

1376
	if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1377
		ret = i915_gem_attach_phys_object(dev, reg_bo,
1378
						  I915_GEM_PHYS_OVERLAY_REGS,
1379
						  PAGE_SIZE);
1380 1381 1382 1383
		if (ret) {
			DRM_ERROR("failed to attach phys overlay regs\n");
			goto out_free_bo;
		}
1384
		overlay->flip_addr = reg_bo->phys_obj->handle->busaddr;
1385
	} else {
1386
		ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true, false);
1387
		if (ret) {
1388 1389 1390
			DRM_ERROR("failed to pin overlay register bo\n");
			goto out_free_bo;
		}
1391
		overlay->flip_addr = reg_bo->gtt_offset;
1392 1393 1394

		ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
		if (ret) {
1395 1396 1397
			DRM_ERROR("failed to move overlay register bo into the GTT\n");
			goto out_unpin_bo;
		}
1398 1399 1400 1401 1402 1403 1404 1405
	}

	/* init all values */
	overlay->color_key = 0x0101fe;
	overlay->brightness = -19;
	overlay->contrast = 75;
	overlay->saturation = 146;

1406
	regs = intel_overlay_map_regs(overlay);
1407
	if (!regs)
1408
		goto out_unpin_bo;
1409

1410
	memset_io(regs, 0, sizeof(struct overlay_registers));
1411 1412 1413
	update_polyphase_filter(regs);
	update_reg_attrs(overlay, regs);

1414
	intel_overlay_unmap_regs(overlay, regs);
1415 1416

	dev_priv->overlay = overlay;
1417
	mutex_unlock(&dev->struct_mutex);
1418 1419 1420
	DRM_INFO("initialized overlay support\n");
	return;

1421
out_unpin_bo:
1422 1423
	if (!OVERLAY_NEEDS_PHYSICAL(dev))
		i915_gem_object_unpin(reg_bo);
1424
out_free_bo:
1425
	drm_gem_object_unreference(&reg_bo->base);
1426
out_free:
1427
	mutex_unlock(&dev->struct_mutex);
1428 1429 1430 1431 1432 1433
	kfree(overlay);
	return;
}

void intel_cleanup_overlay(struct drm_device *dev)
{
C
Chris Wilson 已提交
1434
	drm_i915_private_t *dev_priv = dev->dev_private;
1435

1436 1437
	if (!dev_priv->overlay)
		return;
1438

1439 1440 1441 1442 1443 1444 1445
	/* The bo's should be free'd by the generic code already.
	 * Furthermore modesetting teardown happens beforehand so the
	 * hardware should be off already */
	BUG_ON(dev_priv->overlay->active);

	drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
	kfree(dev_priv->overlay);
1446
}
1447

1448 1449 1450
#ifdef CONFIG_DEBUG_FS
#include <linux/seq_file.h>

1451 1452 1453 1454 1455 1456 1457
struct intel_overlay_error_state {
	struct overlay_registers regs;
	unsigned long base;
	u32 dovsta;
	u32 isr;
};

1458
static struct overlay_registers __iomem *
1459
intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1460
{
1461
	drm_i915_private_t *dev_priv = overlay->dev->dev_private;
1462
	struct overlay_registers __iomem *regs;
1463 1464

	if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1465 1466 1467 1468
		/* Cast to make sparse happy, but it's wc memory anyway, so
		 * equivalent to the wc io mapping on X86. */
		regs = (struct overlay_registers __iomem *)
			overlay->reg_bo->phys_obj->handle->vaddr;
1469 1470
	else
		regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1471
						overlay->reg_bo->gtt_offset);
1472 1473 1474 1475 1476

	return regs;
}

static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1477
					struct overlay_registers __iomem *regs)
1478 1479
{
	if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1480
		io_mapping_unmap_atomic(regs);
1481 1482 1483
}


1484 1485 1486
struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_device *dev)
{
1487
	drm_i915_private_t *dev_priv = dev->dev_private;
1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500
	struct intel_overlay *overlay = dev_priv->overlay;
	struct intel_overlay_error_state *error;
	struct overlay_registers __iomem *regs;

	if (!overlay || !overlay->active)
		return NULL;

	error = kmalloc(sizeof(*error), GFP_ATOMIC);
	if (error == NULL)
		return NULL;

	error->dovsta = I915_READ(DOVSTA);
	error->isr = I915_READ(ISR);
1501
	if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1502
		error->base = (__force long)overlay->reg_bo->phys_obj->handle->vaddr;
1503
	else
1504
		error->base = overlay->reg_bo->gtt_offset;
1505 1506 1507 1508 1509 1510

	regs = intel_overlay_map_regs_atomic(overlay);
	if (!regs)
		goto err;

	memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1511
	intel_overlay_unmap_regs_atomic(overlay, regs);
1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571

	return error;

err:
	kfree(error);
	return NULL;
}

void
intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
{
	seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
		   error->dovsta, error->isr);
	seq_printf(m, "  Register file at 0x%08lx:\n",
		   error->base);

#define P(x) seq_printf(m, "    " #x ":	0x%08x\n", error->regs.x)
	P(OBUF_0Y);
	P(OBUF_1Y);
	P(OBUF_0U);
	P(OBUF_0V);
	P(OBUF_1U);
	P(OBUF_1V);
	P(OSTRIDE);
	P(YRGB_VPH);
	P(UV_VPH);
	P(HORZ_PH);
	P(INIT_PHS);
	P(DWINPOS);
	P(DWINSZ);
	P(SWIDTH);
	P(SWIDTHSW);
	P(SHEIGHT);
	P(YRGBSCALE);
	P(UVSCALE);
	P(OCLRC0);
	P(OCLRC1);
	P(DCLRKV);
	P(DCLRKM);
	P(SCLRKVH);
	P(SCLRKVL);
	P(SCLRKEN);
	P(OCONFIG);
	P(OCMD);
	P(OSTART_0Y);
	P(OSTART_1Y);
	P(OSTART_0U);
	P(OSTART_0V);
	P(OSTART_1U);
	P(OSTART_1V);
	P(OTILEOFF_0Y);
	P(OTILEOFF_1Y);
	P(OTILEOFF_0U);
	P(OTILEOFF_0V);
	P(OTILEOFF_1U);
	P(OTILEOFF_1V);
	P(FASTHSCALE);
	P(UVSCALEV);
#undef P
}
1572
#endif