exynos-iommu.c 36.3 KB
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/*
 * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
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 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifdef CONFIG_EXYNOS_IOMMU_DEBUG
#define DEBUG
#endif

#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/of.h>
#include <linux/of_iommu.h>
#include <linux/of_platform.h>
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#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
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#include <linux/dma-iommu.h>
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typedef u32 sysmmu_iova_t;
typedef u32 sysmmu_pte_t;

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/* We do not consider super section mapping (16MB) */
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#define SECT_ORDER 20
#define LPAGE_ORDER 16
#define SPAGE_ORDER 12

#define SECT_SIZE (1 << SECT_ORDER)
#define LPAGE_SIZE (1 << LPAGE_ORDER)
#define SPAGE_SIZE (1 << SPAGE_ORDER)

#define SECT_MASK (~(SECT_SIZE - 1))
#define LPAGE_MASK (~(LPAGE_SIZE - 1))
#define SPAGE_MASK (~(SPAGE_SIZE - 1))

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#define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
			   ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
#define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
#define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
#define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
			  ((*(sent) & 3) == 1))
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#define lv1ent_section(sent) ((*(sent) & 3) == 2)

#define lv2ent_fault(pent) ((*(pent) & 3) == 0)
#define lv2ent_small(pent) ((*(pent) & 2) == 2)
#define lv2ent_large(pent) ((*(pent) & 3) == 1)

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/*
 * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
 * v5.0 introduced support for 36bit physical address space by shifting
 * all page entry values by 4 bits.
 * All SYSMMU controllers in the system support the address spaces of the same
 * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
 * value (0 or 4).
 */
static short PG_ENT_SHIFT = -1;
#define SYSMMU_PG_ENT_SHIFT 0
#define SYSMMU_V5_PG_ENT_SHIFT 4

#define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
#define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
#define section_offs(iova) (iova & (SECT_SIZE - 1))
#define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
#define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
#define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
#define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
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#define NUM_LV1ENTRIES 4096
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#define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
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static u32 lv1ent_offset(sysmmu_iova_t iova)
{
	return iova >> SECT_ORDER;
}

static u32 lv2ent_offset(sysmmu_iova_t iova)
{
	return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
}

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#define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
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#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
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#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
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#define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
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#define mk_lv1ent_sect(pa) ((pa >> PG_ENT_SHIFT) | 2)
#define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
#define mk_lv2ent_lpage(pa) ((pa >> PG_ENT_SHIFT) | 1)
#define mk_lv2ent_spage(pa) ((pa >> PG_ENT_SHIFT) | 2)
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#define CTRL_ENABLE	0x5
#define CTRL_BLOCK	0x7
#define CTRL_DISABLE	0x0

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#define CFG_LRU		0x1
#define CFG_QOS(n)	((n & 0xF) << 7)
#define CFG_ACGEN	(1 << 24) /* System MMU 3.3 only */
#define CFG_SYSSEL	(1 << 22) /* System MMU 3.2 only */
#define CFG_FLPDCACHE	(1 << 20) /* System MMU 3.2+ only */

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/* common registers */
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#define REG_MMU_CTRL		0x000
#define REG_MMU_CFG		0x004
#define REG_MMU_STATUS		0x008
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#define REG_MMU_VERSION		0x034

#define MMU_MAJ_VER(val)	((val) >> 7)
#define MMU_MIN_VER(val)	((val) & 0x7F)
#define MMU_RAW_VER(reg)	(((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */

#define MAKE_MMU_VER(maj, min)	((((maj) & 0xF) << 7) | ((min) & 0x7F))

/* v1.x - v3.x registers */
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#define REG_MMU_FLUSH		0x00C
#define REG_MMU_FLUSH_ENTRY	0x010
#define REG_PT_BASE_ADDR	0x014
#define REG_INT_STATUS		0x018
#define REG_INT_CLEAR		0x01C

#define REG_PAGE_FAULT_ADDR	0x024
#define REG_AW_FAULT_ADDR	0x028
#define REG_AR_FAULT_ADDR	0x02C
#define REG_DEFAULT_SLAVE_ADDR	0x030

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/* v5.x registers */
#define REG_V5_PT_BASE_PFN	0x00C
#define REG_V5_MMU_FLUSH_ALL	0x010
#define REG_V5_MMU_FLUSH_ENTRY	0x014
#define REG_V5_INT_STATUS	0x060
#define REG_V5_INT_CLEAR	0x064
#define REG_V5_FAULT_AR_VA	0x070
#define REG_V5_FAULT_AW_VA	0x080
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#define has_sysmmu(dev)		(dev->archdata.iommu != NULL)

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static struct device *dma_dev;
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static struct kmem_cache *lv2table_kmem_cache;
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static sysmmu_pte_t *zero_lv2_table;
#define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
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static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
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{
	return pgtable + lv1ent_offset(iova);
}

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static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
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{
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	return (sysmmu_pte_t *)phys_to_virt(
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				lv2table_base(sent)) + lv2ent_offset(iova);
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}

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/*
 * IOMMU fault information register
 */
struct sysmmu_fault_info {
	unsigned int bit;	/* bit number in STATUS register */
	unsigned short addr_reg; /* register to read VA fault address */
	const char *name;	/* human readable fault name */
	unsigned int type;	/* fault type for report_iommu_fault */
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};

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static const struct sysmmu_fault_info sysmmu_faults[] = {
	{ 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
	{ 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
	{ 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
	{ 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
	{ 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
	{ 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
	{ 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
	{ 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
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};

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static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
	{ 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
	{ 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
	{ 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
	{ 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
	{ 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
	{ 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
	{ 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
	{ 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
	{ 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
	{ 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
};

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/*
 * This structure is attached to dev.archdata.iommu of the master device
 * on device add, contains a list of SYSMMU controllers defined by device tree,
 * which are bound to given master device. It is usually referenced by 'owner'
 * pointer.
*/
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struct exynos_iommu_owner {
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	struct list_head controllers;	/* list of sysmmu_drvdata.owner_node */
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	struct iommu_domain *domain;	/* domain this device is attached */
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};

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/*
 * This structure exynos specific generalization of struct iommu_domain.
 * It contains list of SYSMMU controllers from all master devices, which has
 * been attached to this domain and page tables of IO address space defined by
 * it. It is usually referenced by 'domain' pointer.
 */
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struct exynos_iommu_domain {
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	struct list_head clients; /* list of sysmmu_drvdata.domain_node */
	sysmmu_pte_t *pgtable;	/* lv1 page table, 16KB */
	short *lv2entcnt;	/* free lv2 entry counter for each section */
	spinlock_t lock;	/* lock for modyfying list of clients */
	spinlock_t pgtablelock;	/* lock for modifying page table @ pgtable */
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	struct iommu_domain domain; /* generic domain data structure */
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};

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/*
 * This structure hold all data of a single SYSMMU controller, this includes
 * hw resources like registers and clocks, pointers and list nodes to connect
 * it to all other structures, internal state and parameters read from device
 * tree. It is usually referenced by 'data' pointer.
 */
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struct sysmmu_drvdata {
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	struct device *sysmmu;		/* SYSMMU controller device */
	struct device *master;		/* master device (owner) */
	void __iomem *sfrbase;		/* our registers */
	struct clk *clk;		/* SYSMMU's clock */
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	struct clk *aclk;		/* SYSMMU's aclk clock */
	struct clk *pclk;		/* SYSMMU's pclk clock */
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	struct clk *clk_master;		/* master's device clock */
	int activations;		/* number of calls to sysmmu_enable */
	spinlock_t lock;		/* lock for modyfying state */
	struct exynos_iommu_domain *domain; /* domain we belong to */
	struct list_head domain_node;	/* node for domain clients list */
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	struct list_head owner_node;	/* node for owner controllers list */
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	phys_addr_t pgtable;		/* assigned page table structure */
	unsigned int version;		/* our version */
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};

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static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
{
	return container_of(dom, struct exynos_iommu_domain, domain);
}

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static bool set_sysmmu_active(struct sysmmu_drvdata *data)
{
	/* return true if the System MMU was not active previously
	   and it needs to be initialized */
	return ++data->activations == 1;
}

static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
{
	/* return true if the System MMU is needed to be disabled */
	BUG_ON(data->activations < 1);
	return --data->activations == 0;
}

static bool is_sysmmu_active(struct sysmmu_drvdata *data)
{
	return data->activations > 0;
}

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static void sysmmu_unblock(struct sysmmu_drvdata *data)
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{
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	writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
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}

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static bool sysmmu_block(struct sysmmu_drvdata *data)
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{
	int i = 120;

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	writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
	while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
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		--i;

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	if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
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		sysmmu_unblock(data);
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		return false;
	}

	return true;
}

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static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
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{
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	if (MMU_MAJ_VER(data->version) < 5)
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		writel(0x1, data->sfrbase + REG_MMU_FLUSH);
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	else
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		writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
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}

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static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
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				sysmmu_iova_t iova, unsigned int num_inv)
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{
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	unsigned int i;
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	for (i = 0; i < num_inv; i++) {
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		if (MMU_MAJ_VER(data->version) < 5)
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			writel((iova & SPAGE_MASK) | 1,
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				     data->sfrbase + REG_MMU_FLUSH_ENTRY);
		else
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			writel((iova & SPAGE_MASK) | 1,
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				     data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
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		iova += SPAGE_SIZE;
	}
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}

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static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
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{
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	if (MMU_MAJ_VER(data->version) < 5)
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		writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
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	else
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		writel(pgd >> PAGE_SHIFT,
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			     data->sfrbase + REG_V5_PT_BASE_PFN);
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	__sysmmu_tlb_invalidate(data);
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}

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static void __sysmmu_get_version(struct sysmmu_drvdata *data)
{
	u32 ver;

	clk_enable(data->clk_master);
	clk_enable(data->clk);
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	clk_enable(data->pclk);
	clk_enable(data->aclk);
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	ver = readl(data->sfrbase + REG_MMU_VERSION);
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	/* controllers on some SoCs don't report proper version */
	if (ver == 0x80000001u)
		data->version = MAKE_MMU_VER(1, 0);
	else
		data->version = MMU_RAW_VER(ver);

	dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
		MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));

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	clk_disable(data->aclk);
	clk_disable(data->pclk);
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	clk_disable(data->clk);
	clk_disable(data->clk_master);
}

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static void show_fault_information(struct sysmmu_drvdata *data,
				   const struct sysmmu_fault_info *finfo,
				   sysmmu_iova_t fault_addr)
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{
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	sysmmu_pte_t *ent;
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	dev_err(data->sysmmu, "%s FAULT occurred at %#x (page table base: %pa)\n",
		finfo->name, fault_addr, &data->pgtable);
	ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
	dev_err(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
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	if (lv1ent_page(ent)) {
		ent = page_entry(ent, fault_addr);
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		dev_err(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
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	}
}

static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
{
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	/* SYSMMU is in blocked state when interrupt occurred. */
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	struct sysmmu_drvdata *data = dev_id;
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	const struct sysmmu_fault_info *finfo;
	unsigned int i, n, itype;
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	sysmmu_iova_t fault_addr = -1;
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	unsigned short reg_status, reg_clear;
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	int ret = -ENOSYS;
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	WARN_ON(!is_sysmmu_active(data));

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	if (MMU_MAJ_VER(data->version) < 5) {
		reg_status = REG_INT_STATUS;
		reg_clear = REG_INT_CLEAR;
		finfo = sysmmu_faults;
		n = ARRAY_SIZE(sysmmu_faults);
	} else {
		reg_status = REG_V5_INT_STATUS;
		reg_clear = REG_V5_INT_CLEAR;
		finfo = sysmmu_v5_faults;
		n = ARRAY_SIZE(sysmmu_v5_faults);
	}

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	spin_lock(&data->lock);

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	clk_enable(data->clk_master);
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	itype = __ffs(readl(data->sfrbase + reg_status));
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	for (i = 0; i < n; i++, finfo++)
		if (finfo->bit == itype)
			break;
	/* unknown/unsupported fault */
	BUG_ON(i == n);

	/* print debug message */
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	fault_addr = readl(data->sfrbase + finfo->addr_reg);
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	show_fault_information(data, finfo, fault_addr);
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	if (data->domain)
		ret = report_iommu_fault(&data->domain->domain,
					data->master, fault_addr, finfo->type);
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	/* fault is not recovered by fault handler */
	BUG_ON(ret != 0);
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	writel(1 << itype, data->sfrbase + reg_clear);
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	sysmmu_unblock(data);
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	clk_disable(data->clk_master);
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	spin_unlock(&data->lock);
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	return IRQ_HANDLED;
}

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static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
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{
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	clk_enable(data->clk_master);
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	writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
	writel(0, data->sfrbase + REG_MMU_CFG);
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	clk_disable(data->aclk);
	clk_disable(data->pclk);
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	clk_disable(data->clk);
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	clk_disable(data->clk_master);
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}

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static bool __sysmmu_disable(struct sysmmu_drvdata *data)
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{
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	bool disabled;
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	unsigned long flags;

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	spin_lock_irqsave(&data->lock, flags);
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	disabled = set_sysmmu_inactive(data);

	if (disabled) {
		data->pgtable = 0;
		data->domain = NULL;

		__sysmmu_disable_nocount(data);
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		dev_dbg(data->sysmmu, "Disabled\n");
	} else  {
		dev_dbg(data->sysmmu, "%d times left to disable\n",
					data->activations);
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	}

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	spin_unlock_irqrestore(&data->lock, flags);

	return disabled;
}
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static void __sysmmu_init_config(struct sysmmu_drvdata *data)
{
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	unsigned int cfg;

	if (data->version <= MAKE_MMU_VER(3, 1))
		cfg = CFG_LRU | CFG_QOS(15);
	else if (data->version <= MAKE_MMU_VER(3, 2))
		cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL;
	else
		cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN;
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	writel(cfg, data->sfrbase + REG_MMU_CFG);
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}

static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
{
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	clk_enable(data->clk_master);
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	clk_enable(data->clk);
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	clk_enable(data->pclk);
	clk_enable(data->aclk);
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	writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
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	__sysmmu_init_config(data);

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	__sysmmu_set_ptbase(data, data->pgtable);
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	writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
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	clk_disable(data->clk_master);
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}
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static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable,
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			   struct exynos_iommu_domain *domain)
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{
	int ret = 0;
	unsigned long flags;

	spin_lock_irqsave(&data->lock, flags);
	if (set_sysmmu_active(data)) {
		data->pgtable = pgtable;
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		data->domain = domain;
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		__sysmmu_enable_nocount(data);

		dev_dbg(data->sysmmu, "Enabled\n");
	} else {
		ret = (pgtable == data->pgtable) ? 1 : -EBUSY;

		dev_dbg(data->sysmmu, "already enabled\n");
	}

	if (WARN_ON(ret < 0))
		set_sysmmu_inactive(data); /* decrement count */
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	spin_unlock_irqrestore(&data->lock, flags);
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	return ret;
}

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static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
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					    sysmmu_iova_t iova)
{
	unsigned long flags;

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	clk_enable(data->clk_master);
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	spin_lock_irqsave(&data->lock, flags);
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	if (is_sysmmu_active(data)) {
		if (data->version >= MAKE_MMU_VER(3, 3))
			__sysmmu_tlb_invalidate_entry(data, iova, 1);
	}
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	spin_unlock_irqrestore(&data->lock, flags);

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	clk_disable(data->clk_master);
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}

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static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
					sysmmu_iova_t iova, size_t size)
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{
	unsigned long flags;

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	spin_lock_irqsave(&data->lock, flags);
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	if (is_sysmmu_active(data)) {
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		unsigned int num_inv = 1;
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		clk_enable(data->clk_master);
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		/*
		 * L2TLB invalidation required
		 * 4KB page: 1 invalidation
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		 * 64KB page: 16 invalidations
		 * 1MB page: 64 invalidations
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		 * because it is set-associative TLB
		 * with 8-way and 64 sets.
		 * 1MB page can be cached in one of all sets.
		 * 64KB page can be one of 16 consecutive sets.
		 */
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		if (MMU_MAJ_VER(data->version) == 2)
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			num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);

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		if (sysmmu_block(data)) {
			__sysmmu_tlb_invalidate_entry(data, iova, num_inv);
			sysmmu_unblock(data);
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		}
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		clk_disable(data->clk_master);
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	} else {
569 570
		dev_dbg(data->master,
			"disabled. Skipping TLB invalidation @ %#x\n", iova);
571
	}
572
	spin_unlock_irqrestore(&data->lock, flags);
573 574
}

575
static int __init exynos_sysmmu_probe(struct platform_device *pdev)
576
{
577
	int irq, ret;
578
	struct device *dev = &pdev->dev;
579
	struct sysmmu_drvdata *data;
580
	struct resource *res;
581

582 583 584
	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;
585

586
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
587 588 589
	data->sfrbase = devm_ioremap_resource(dev, res);
	if (IS_ERR(data->sfrbase))
		return PTR_ERR(data->sfrbase);
590

591 592
	irq = platform_get_irq(pdev, 0);
	if (irq <= 0) {
593
		dev_err(dev, "Unable to find IRQ resource\n");
594
		return irq;
595 596
	}

597
	ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
598 599
				dev_name(dev), data);
	if (ret) {
600 601
		dev_err(dev, "Unabled to register handler of irq %d\n", irq);
		return ret;
602 603
	}

604
	data->clk = devm_clk_get(dev, "sysmmu");
605
	if (!IS_ERR(data->clk)) {
606 607 608 609 610
		ret = clk_prepare(data->clk);
		if (ret) {
			dev_err(dev, "Failed to prepare clk\n");
			return ret;
		}
611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639
	} else {
		data->clk = NULL;
	}

	data->aclk = devm_clk_get(dev, "aclk");
	if (!IS_ERR(data->aclk)) {
		ret = clk_prepare(data->aclk);
		if (ret) {
			dev_err(dev, "Failed to prepare aclk\n");
			return ret;
		}
	} else {
		data->aclk = NULL;
	}

	data->pclk = devm_clk_get(dev, "pclk");
	if (!IS_ERR(data->pclk)) {
		ret = clk_prepare(data->pclk);
		if (ret) {
			dev_err(dev, "Failed to prepare pclk\n");
			return ret;
		}
	} else {
		data->pclk = NULL;
	}

	if (!data->clk && (!data->aclk || !data->pclk)) {
		dev_err(dev, "Failed to get device clock(s)!\n");
		return -ENOSYS;
640 641
	}

642 643 644 645 646 647 648
	data->clk_master = devm_clk_get(dev, "master");
	if (!IS_ERR(data->clk_master)) {
		ret = clk_prepare(data->clk_master);
		if (ret) {
			dev_err(dev, "Failed to prepare master's clk\n");
			return ret;
		}
649 650
	} else {
		data->clk_master = NULL;
651 652
	}

653
	data->sysmmu = dev;
654
	spin_lock_init(&data->lock);
655

656 657
	platform_set_drvdata(pdev, data);

658
	__sysmmu_get_version(data);
659 660 661 662 663 664 665
	if (PG_ENT_SHIFT < 0) {
		if (MMU_MAJ_VER(data->version) < 5)
			PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
		else
			PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
	}

666
	pm_runtime_enable(dev);
667 668 669 670

	return 0;
}

671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700
#ifdef CONFIG_PM_SLEEP
static int exynos_sysmmu_suspend(struct device *dev)
{
	struct sysmmu_drvdata *data = dev_get_drvdata(dev);

	dev_dbg(dev, "suspend\n");
	if (is_sysmmu_active(data)) {
		__sysmmu_disable_nocount(data);
		pm_runtime_put(dev);
	}
	return 0;
}

static int exynos_sysmmu_resume(struct device *dev)
{
	struct sysmmu_drvdata *data = dev_get_drvdata(dev);

	dev_dbg(dev, "resume\n");
	if (is_sysmmu_active(data)) {
		pm_runtime_get_sync(dev);
		__sysmmu_enable_nocount(data);
	}
	return 0;
}
#endif

static const struct dev_pm_ops sysmmu_pm_ops = {
	SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume)
};

701 702 703 704 705 706 707 708
static const struct of_device_id sysmmu_of_match[] __initconst = {
	{ .compatible	= "samsung,exynos-sysmmu", },
	{ },
};

static struct platform_driver exynos_sysmmu_driver __refdata = {
	.probe	= exynos_sysmmu_probe,
	.driver	= {
709
		.name		= "exynos-sysmmu",
710
		.of_match_table	= sysmmu_of_match,
711
		.pm		= &sysmmu_pm_ops,
712 713 714
	}
};

715
static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
716
{
717 718 719 720 721
	dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
				DMA_TO_DEVICE);
	*ent = val;
	dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
				   DMA_TO_DEVICE);
722 723
}

724
static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
725
{
726
	struct exynos_iommu_domain *domain;
727
	dma_addr_t handle;
728
	int i;
729

730 731
	/* Check if correct PTE offsets are initialized */
	BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
732

733 734
	domain = kzalloc(sizeof(*domain), GFP_KERNEL);
	if (!domain)
735
		return NULL;
736

737 738 739 740 741 742 743
	if (type == IOMMU_DOMAIN_DMA) {
		if (iommu_get_dma_cookie(&domain->domain) != 0)
			goto err_pgtable;
	} else if (type != IOMMU_DOMAIN_UNMANAGED) {
		goto err_pgtable;
	}

744 745
	domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
	if (!domain->pgtable)
746
		goto err_dma_cookie;
747

748 749
	domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
	if (!domain->lv2entcnt)
750 751
		goto err_counter;

752
	/* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
753
	for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
754 755 756 757 758 759 760 761
		domain->pgtable[i + 0] = ZERO_LV2LINK;
		domain->pgtable[i + 1] = ZERO_LV2LINK;
		domain->pgtable[i + 2] = ZERO_LV2LINK;
		domain->pgtable[i + 3] = ZERO_LV2LINK;
		domain->pgtable[i + 4] = ZERO_LV2LINK;
		domain->pgtable[i + 5] = ZERO_LV2LINK;
		domain->pgtable[i + 6] = ZERO_LV2LINK;
		domain->pgtable[i + 7] = ZERO_LV2LINK;
762 763
	}

764 765 766 767
	handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
				DMA_TO_DEVICE);
	/* For mapping page table entries we rely on dma == phys */
	BUG_ON(handle != virt_to_phys(domain->pgtable));
768

769 770 771
	spin_lock_init(&domain->lock);
	spin_lock_init(&domain->pgtablelock);
	INIT_LIST_HEAD(&domain->clients);
772

773 774 775
	domain->domain.geometry.aperture_start = 0;
	domain->domain.geometry.aperture_end   = ~0UL;
	domain->domain.geometry.force_aperture = true;
776

777
	return &domain->domain;
778 779

err_counter:
780
	free_pages((unsigned long)domain->pgtable, 2);
781 782 783
err_dma_cookie:
	if (type == IOMMU_DOMAIN_DMA)
		iommu_put_dma_cookie(&domain->domain);
784
err_pgtable:
785
	kfree(domain);
786
	return NULL;
787 788
}

789
static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
790
{
791
	struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
792
	struct sysmmu_drvdata *data, *next;
793 794 795
	unsigned long flags;
	int i;

796
	WARN_ON(!list_empty(&domain->clients));
797

798
	spin_lock_irqsave(&domain->lock, flags);
799

800
	list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
801 802 803
		if (__sysmmu_disable(data))
			data->master = NULL;
		list_del_init(&data->domain_node);
804 805
	}

806
	spin_unlock_irqrestore(&domain->lock, flags);
807

808 809 810
	if (iommu_domain->type == IOMMU_DOMAIN_DMA)
		iommu_put_dma_cookie(iommu_domain);

811 812 813
	dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
			 DMA_TO_DEVICE);

814
	for (i = 0; i < NUM_LV1ENTRIES; i++)
815 816 817 818 819
		if (lv1ent_page(domain->pgtable + i)) {
			phys_addr_t base = lv2table_base(domain->pgtable + i);

			dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
					 DMA_TO_DEVICE);
820
			kmem_cache_free(lv2table_kmem_cache,
821 822
					phys_to_virt(base));
		}
823

824 825 826
	free_pages((unsigned long)domain->pgtable, 2);
	free_pages((unsigned long)domain->lv2entcnt, 1);
	kfree(domain);
827 828
}

829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863
static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
				    struct device *dev)
{
	struct exynos_iommu_owner *owner = dev->archdata.iommu;
	struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
	phys_addr_t pagetable = virt_to_phys(domain->pgtable);
	struct sysmmu_drvdata *data, *next;
	unsigned long flags;
	bool found = false;

	if (!has_sysmmu(dev) || owner->domain != iommu_domain)
		return;

	spin_lock_irqsave(&domain->lock, flags);
	list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
		if (data->master == dev) {
			if (__sysmmu_disable(data)) {
				data->master = NULL;
				list_del_init(&data->domain_node);
			}
			pm_runtime_put(data->sysmmu);
			found = true;
		}
	}
	spin_unlock_irqrestore(&domain->lock, flags);

	owner->domain = NULL;

	if (found)
		dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
					__func__, &pagetable);
	else
		dev_err(dev, "%s: No IOMMU is attached\n", __func__);
}

864
static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
865 866
				   struct device *dev)
{
867
	struct exynos_iommu_owner *owner = dev->archdata.iommu;
868
	struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
869
	struct sysmmu_drvdata *data;
870
	phys_addr_t pagetable = virt_to_phys(domain->pgtable);
871
	unsigned long flags;
872
	int ret = -ENODEV;
873

874 875
	if (!has_sysmmu(dev))
		return -ENODEV;
876

877 878 879
	if (owner->domain)
		exynos_iommu_detach_device(owner->domain, dev);

880
	list_for_each_entry(data, &owner->controllers, owner_node) {
881
		pm_runtime_get_sync(data->sysmmu);
882
		ret = __sysmmu_enable(data, pagetable, domain);
883 884 885
		if (ret >= 0) {
			data->master = dev;

886 887 888
			spin_lock_irqsave(&domain->lock, flags);
			list_add_tail(&data->domain_node, &domain->clients);
			spin_unlock_irqrestore(&domain->lock, flags);
889 890
		}
	}
891 892

	if (ret < 0) {
893 894 895
		dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
					__func__, &pagetable);
		return ret;
896 897
	}

898
	owner->domain = iommu_domain;
899 900 901
	dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
		__func__, &pagetable, (ret == 0) ? "" : ", again");

902 903 904
	return ret;
}

905
static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
906
		sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
907
{
908
	if (lv1ent_section(sent)) {
909
		WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
910 911 912
		return ERR_PTR(-EADDRINUSE);
	}

913
	if (lv1ent_fault(sent)) {
914
		sysmmu_pte_t *pent;
915
		bool need_flush_flpd_cache = lv1ent_zero(sent);
916

917
		pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
918
		BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1));
919
		if (!pent)
920
			return ERR_PTR(-ENOMEM);
921

922
		update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
923
		kmemleak_ignore(pent);
924
		*pgcounter = NUM_LV2ENTRIES;
925
		dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE);
926 927

		/*
928 929 930 931
		 * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
		 * FLPD cache may cache the address of zero_l2_table. This
		 * function replaces the zero_l2_table with new L2 page table
		 * to write valid mappings.
932
		 * Accessing the valid area may cause page fault since FLPD
933 934 935
		 * cache may still cache zero_l2_table for the valid area
		 * instead of new L2 page table that has the mapping
		 * information of the valid area.
936 937 938 939 940 941 942 943 944
		 * Thus any replacement of zero_l2_table with other valid L2
		 * page table must involve FLPD cache invalidation for System
		 * MMU v3.3.
		 * FLPD cache invalidation is performed with TLB invalidation
		 * by VPN without blocking. It is safe to invalidate TLB without
		 * blocking because the target address of TLB invalidation is
		 * not currently mapped.
		 */
		if (need_flush_flpd_cache) {
945
			struct sysmmu_drvdata *data;
946

947 948
			spin_lock(&domain->lock);
			list_for_each_entry(data, &domain->clients, domain_node)
949
				sysmmu_tlb_invalidate_flpdcache(data, iova);
950
			spin_unlock(&domain->lock);
951
		}
952 953 954 955 956
	}

	return page_entry(sent, iova);
}

957
static int lv1set_section(struct exynos_iommu_domain *domain,
958
			  sysmmu_pte_t *sent, sysmmu_iova_t iova,
959
			  phys_addr_t paddr, short *pgcnt)
960
{
961
	if (lv1ent_section(sent)) {
962
		WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
963
			iova);
964
		return -EADDRINUSE;
965
	}
966 967

	if (lv1ent_page(sent)) {
968
		if (*pgcnt != NUM_LV2ENTRIES) {
969
			WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
970
				iova);
971
			return -EADDRINUSE;
972
		}
973

974
		kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
975 976 977
		*pgcnt = 0;
	}

978
	update_pte(sent, mk_lv1ent_sect(paddr));
979

980
	spin_lock(&domain->lock);
981
	if (lv1ent_page_zero(sent)) {
982
		struct sysmmu_drvdata *data;
983 984 985 986
		/*
		 * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
		 * entry by speculative prefetch of SLPD which has no mapping.
		 */
987
		list_for_each_entry(data, &domain->clients, domain_node)
988
			sysmmu_tlb_invalidate_flpdcache(data, iova);
989
	}
990
	spin_unlock(&domain->lock);
991

992 993 994
	return 0;
}

995
static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
996 997 998
								short *pgcnt)
{
	if (size == SPAGE_SIZE) {
999
		if (WARN_ON(!lv2ent_fault(pent)))
1000 1001
			return -EADDRINUSE;

1002
		update_pte(pent, mk_lv2ent_spage(paddr));
1003 1004 1005
		*pgcnt -= 1;
	} else { /* size == LPAGE_SIZE */
		int i;
1006
		dma_addr_t pent_base = virt_to_phys(pent);
1007

1008 1009 1010
		dma_sync_single_for_cpu(dma_dev, pent_base,
					sizeof(*pent) * SPAGES_PER_LPAGE,
					DMA_TO_DEVICE);
1011
		for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
1012
			if (WARN_ON(!lv2ent_fault(pent))) {
1013 1014
				if (i > 0)
					memset(pent - i, 0, sizeof(*pent) * i);
1015 1016 1017 1018 1019
				return -EADDRINUSE;
			}

			*pent = mk_lv2ent_lpage(paddr);
		}
1020 1021 1022
		dma_sync_single_for_device(dma_dev, pent_base,
					   sizeof(*pent) * SPAGES_PER_LPAGE,
					   DMA_TO_DEVICE);
1023 1024 1025 1026 1027 1028
		*pgcnt -= SPAGES_PER_LPAGE;
	}

	return 0;
}

1029 1030 1031
/*
 * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
 *
1032
 * System MMU v3.x has advanced logic to improve address translation
1033
 * performance with caching more page table entries by a page table walk.
1034 1035 1036 1037 1038 1039
 * However, the logic has a bug that while caching faulty page table entries,
 * System MMU reports page fault if the cached fault entry is hit even though
 * the fault entry is updated to a valid entry after the entry is cached.
 * To prevent caching faulty page table entries which may be updated to valid
 * entries later, the virtual memory manager should care about the workaround
 * for the problem. The following describes the workaround.
1040 1041
 *
 * Any two consecutive I/O virtual address regions must have a hole of 128KiB
1042
 * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
1043
 *
1044
 * Precisely, any start address of I/O virtual region must be aligned with
1045 1046 1047 1048 1049
 * the following sizes for System MMU v3.1 and v3.2.
 * System MMU v3.1: 128KiB
 * System MMU v3.2: 256KiB
 *
 * Because System MMU v3.3 caches page table entries more aggressively, it needs
1050 1051 1052
 * more workarounds.
 * - Any two consecutive I/O virtual regions must have a hole of size larger
 *   than or equal to 128KiB.
1053 1054
 * - Start address of an I/O virtual region must be aligned by 128KiB.
 */
1055 1056 1057
static int exynos_iommu_map(struct iommu_domain *iommu_domain,
			    unsigned long l_iova, phys_addr_t paddr, size_t size,
			    int prot)
1058
{
1059
	struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1060 1061
	sysmmu_pte_t *entry;
	sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1062 1063 1064
	unsigned long flags;
	int ret = -ENOMEM;

1065
	BUG_ON(domain->pgtable == NULL);
1066

1067
	spin_lock_irqsave(&domain->pgtablelock, flags);
1068

1069
	entry = section_entry(domain->pgtable, iova);
1070 1071

	if (size == SECT_SIZE) {
1072 1073
		ret = lv1set_section(domain, entry, iova, paddr,
				     &domain->lv2entcnt[lv1ent_offset(iova)]);
1074
	} else {
1075
		sysmmu_pte_t *pent;
1076

1077 1078
		pent = alloc_lv2entry(domain, entry, iova,
				      &domain->lv2entcnt[lv1ent_offset(iova)]);
1079

1080 1081
		if (IS_ERR(pent))
			ret = PTR_ERR(pent);
1082 1083
		else
			ret = lv2set_page(pent, paddr, size,
1084
				       &domain->lv2entcnt[lv1ent_offset(iova)]);
1085 1086
	}

1087
	if (ret)
1088 1089
		pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
			__func__, ret, size, iova);
1090

1091
	spin_unlock_irqrestore(&domain->pgtablelock, flags);
1092 1093 1094 1095

	return ret;
}

1096 1097
static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
					      sysmmu_iova_t iova, size_t size)
1098
{
1099
	struct sysmmu_drvdata *data;
1100 1101
	unsigned long flags;

1102
	spin_lock_irqsave(&domain->lock, flags);
1103

1104
	list_for_each_entry(data, &domain->clients, domain_node)
1105
		sysmmu_tlb_invalidate_entry(data, iova, size);
1106

1107
	spin_unlock_irqrestore(&domain->lock, flags);
1108 1109
}

1110 1111
static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
				 unsigned long l_iova, size_t size)
1112
{
1113
	struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1114 1115
	sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
	sysmmu_pte_t *ent;
1116
	size_t err_pgsize;
1117
	unsigned long flags;
1118

1119
	BUG_ON(domain->pgtable == NULL);
1120

1121
	spin_lock_irqsave(&domain->pgtablelock, flags);
1122

1123
	ent = section_entry(domain->pgtable, iova);
1124 1125

	if (lv1ent_section(ent)) {
1126
		if (WARN_ON(size < SECT_SIZE)) {
1127 1128 1129
			err_pgsize = SECT_SIZE;
			goto err;
		}
1130

1131
		/* workaround for h/w bug in System MMU v3.3 */
1132
		update_pte(ent, ZERO_LV2LINK);
1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152
		size = SECT_SIZE;
		goto done;
	}

	if (unlikely(lv1ent_fault(ent))) {
		if (size > SECT_SIZE)
			size = SECT_SIZE;
		goto done;
	}

	/* lv1ent_page(sent) == true here */

	ent = page_entry(ent, iova);

	if (unlikely(lv2ent_fault(ent))) {
		size = SPAGE_SIZE;
		goto done;
	}

	if (lv2ent_small(ent)) {
1153
		update_pte(ent, 0);
1154
		size = SPAGE_SIZE;
1155
		domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1156 1157 1158 1159
		goto done;
	}

	/* lv1ent_large(ent) == true here */
1160
	if (WARN_ON(size < LPAGE_SIZE)) {
1161 1162 1163
		err_pgsize = LPAGE_SIZE;
		goto err;
	}
1164

1165 1166 1167
	dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
				sizeof(*ent) * SPAGES_PER_LPAGE,
				DMA_TO_DEVICE);
1168
	memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1169 1170 1171
	dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
				   sizeof(*ent) * SPAGES_PER_LPAGE,
				   DMA_TO_DEVICE);
1172
	size = LPAGE_SIZE;
1173
	domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1174
done:
1175
	spin_unlock_irqrestore(&domain->pgtablelock, flags);
1176

1177
	exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1178 1179

	return size;
1180
err:
1181
	spin_unlock_irqrestore(&domain->pgtablelock, flags);
1182

1183 1184
	pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
		__func__, size, iova, err_pgsize);
1185 1186

	return 0;
1187 1188
}

1189
static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1190
					  dma_addr_t iova)
1191
{
1192
	struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1193
	sysmmu_pte_t *entry;
1194 1195 1196
	unsigned long flags;
	phys_addr_t phys = 0;

1197
	spin_lock_irqsave(&domain->pgtablelock, flags);
1198

1199
	entry = section_entry(domain->pgtable, iova);
1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211

	if (lv1ent_section(entry)) {
		phys = section_phys(entry) + section_offs(iova);
	} else if (lv1ent_page(entry)) {
		entry = page_entry(entry, iova);

		if (lv2ent_large(entry))
			phys = lpage_phys(entry) + lpage_offs(iova);
		else if (lv2ent_small(entry))
			phys = spage_phys(entry) + spage_offs(iova);
	}

1212
	spin_unlock_irqrestore(&domain->pgtablelock, flags);
1213 1214 1215 1216

	return phys;
}

1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227
static struct iommu_group *get_device_iommu_group(struct device *dev)
{
	struct iommu_group *group;

	group = iommu_group_get(dev);
	if (!group)
		group = iommu_group_alloc();

	return group;
}

1228 1229 1230 1231
static int exynos_iommu_add_device(struct device *dev)
{
	struct iommu_group *group;

1232 1233 1234
	if (!has_sysmmu(dev))
		return -ENODEV;

1235
	group = iommu_group_get_for_dev(dev);
1236

1237 1238
	if (IS_ERR(group))
		return PTR_ERR(group);
1239 1240 1241

	iommu_group_put(group);

1242
	return 0;
1243 1244 1245 1246
}

static void exynos_iommu_remove_device(struct device *dev)
{
1247 1248 1249
	if (!has_sysmmu(dev))
		return;

1250 1251 1252
	iommu_group_remove_device(dev);
}

1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279
static int exynos_iommu_of_xlate(struct device *dev,
				 struct of_phandle_args *spec)
{
	struct exynos_iommu_owner *owner = dev->archdata.iommu;
	struct platform_device *sysmmu = of_find_device_by_node(spec->np);
	struct sysmmu_drvdata *data;

	if (!sysmmu)
		return -ENODEV;

	data = platform_get_drvdata(sysmmu);
	if (!data)
		return -ENODEV;

	if (!owner) {
		owner = kzalloc(sizeof(*owner), GFP_KERNEL);
		if (!owner)
			return -ENOMEM;

		INIT_LIST_HEAD(&owner->controllers);
		dev->archdata.iommu = owner;
	}

	list_add_tail(&data->owner_node, &owner->controllers);
	return 0;
}

1280
static struct iommu_ops exynos_iommu_ops = {
1281 1282
	.domain_alloc = exynos_iommu_domain_alloc,
	.domain_free = exynos_iommu_domain_free,
1283 1284 1285 1286
	.attach_dev = exynos_iommu_attach_device,
	.detach_dev = exynos_iommu_detach_device,
	.map = exynos_iommu_map,
	.unmap = exynos_iommu_unmap,
1287
	.map_sg = default_iommu_map_sg,
1288
	.iova_to_phys = exynos_iommu_iova_to_phys,
1289
	.device_group = get_device_iommu_group,
1290 1291
	.add_device = exynos_iommu_add_device,
	.remove_device = exynos_iommu_remove_device,
1292
	.pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1293
	.of_xlate = exynos_iommu_of_xlate,
1294 1295
};

1296 1297
static bool init_done;

1298 1299 1300 1301
static int __init exynos_iommu_init(void)
{
	int ret;

1302 1303 1304 1305 1306 1307 1308
	lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
				LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
	if (!lv2table_kmem_cache) {
		pr_err("%s: Failed to create kmem cache\n", __func__);
		return -ENOMEM;
	}

1309
	ret = platform_driver_register(&exynos_sysmmu_driver);
1310 1311 1312 1313
	if (ret) {
		pr_err("%s: Failed to register driver\n", __func__);
		goto err_reg_driver;
	}
1314

1315 1316 1317 1318 1319 1320 1321 1322
	zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
	if (zero_lv2_table == NULL) {
		pr_err("%s: Failed to allocate zero level2 page table\n",
			__func__);
		ret = -ENOMEM;
		goto err_zero_lv2;
	}

1323 1324 1325 1326 1327 1328
	ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
	if (ret) {
		pr_err("%s: Failed to register exynos-iommu driver.\n",
								__func__);
		goto err_set_iommu;
	}
1329

1330 1331
	init_done = true;

1332 1333
	return 0;
err_set_iommu:
1334 1335
	kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
err_zero_lv2:
1336 1337 1338
	platform_driver_unregister(&exynos_sysmmu_driver);
err_reg_driver:
	kmem_cache_destroy(lv2table_kmem_cache);
1339 1340
	return ret;
}
1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352

static int __init exynos_iommu_of_setup(struct device_node *np)
{
	struct platform_device *pdev;

	if (!init_done)
		exynos_iommu_init();

	pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
	if (IS_ERR(pdev))
		return PTR_ERR(pdev);

1353 1354 1355 1356 1357 1358 1359
	/*
	 * use the first registered sysmmu device for performing
	 * dma mapping operations on iommu page tables (cpu cache flush)
	 */
	if (!dma_dev)
		dma_dev = &pdev->dev;

1360 1361 1362 1363 1364 1365
	of_iommu_set_ops(np, &exynos_iommu_ops);
	return 0;
}

IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
		 exynos_iommu_of_setup);
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