radeon_object.c 12.2 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
 *    Dave Airlie
 */
#include <linux/list.h>
#include <drm/drmP.h>
#include "radeon_drm.h"
#include "radeon.h"


int radeon_ttm_init(struct radeon_device *rdev);
void radeon_ttm_fini(struct radeon_device *rdev);
40
static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
41 42 43 44 45 46

/*
 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
 * function are calling it.
 */

47
static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
48
{
49
	struct radeon_bo *bo;
50

51 52 53 54 55 56
	bo = container_of(tbo, struct radeon_bo, tbo);
	mutex_lock(&bo->rdev->gem.mutex);
	list_del_init(&bo->list);
	mutex_unlock(&bo->rdev->gem.mutex);
	radeon_bo_clear_surface_reg(bo);
	kfree(bo);
57 58
}

59 60 61 62 63 64 65
bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
{
	if (bo->destroy == &radeon_ttm_bo_destroy)
		return true;
	return false;
}

66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
{
	u32 c = 0;

	rbo->placement.fpfn = 0;
	rbo->placement.lpfn = 0;
	rbo->placement.placement = rbo->placements;
	rbo->placement.busy_placement = rbo->placements;
	if (domain & RADEON_GEM_DOMAIN_VRAM)
		rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
					TTM_PL_FLAG_VRAM;
	if (domain & RADEON_GEM_DOMAIN_GTT)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
	if (domain & RADEON_GEM_DOMAIN_CPU)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
81 82
	if (!c)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
83 84 85 86
	rbo->placement.num_placement = c;
	rbo->placement.num_busy_placement = c;
}

87 88 89
int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
			unsigned long size, bool kernel, u32 domain,
			struct radeon_bo **bo_ptr)
90
{
91
	struct radeon_bo *bo;
92 93 94 95 96 97 98 99 100 101 102
	enum ttm_bo_type type;
	int r;

	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
		rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	}
	if (kernel) {
		type = ttm_bo_type_kernel;
	} else {
		type = ttm_bo_type_device;
	}
103 104 105
	*bo_ptr = NULL;
	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
	if (bo == NULL)
106
		return -ENOMEM;
107 108 109 110 111
	bo->rdev = rdev;
	bo->gobj = gobj;
	bo->surface_reg = -1;
	INIT_LIST_HEAD(&bo->list);

112
	radeon_ttm_placement_from_domain(bo, domain);
113
	/* Kernel allocation are uninterruptible */
114 115 116
	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
			&bo->placement, 0, 0, !kernel, NULL, size,
			&radeon_ttm_bo_destroy);
117
	if (unlikely(r != 0)) {
118 119
		if (r != -ERESTARTSYS)
			dev_err(rdev->dev,
120 121
				"object_init failed for (%lu, 0x%08X)\n",
				size, domain);
122 123
		return r;
	}
124
	*bo_ptr = bo;
125
	if (gobj) {
126 127 128
		mutex_lock(&bo->rdev->gem.mutex);
		list_add_tail(&bo->list, &rdev->gem.objects);
		mutex_unlock(&bo->rdev->gem.mutex);
129 130 131 132
	}
	return 0;
}

133
int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
134
{
135
	bool is_iomem;
136 137
	int r;

138
	if (bo->kptr) {
139
		if (ptr) {
140
			*ptr = bo->kptr;
141 142 143
		}
		return 0;
	}
144
	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
145 146 147
	if (r) {
		return r;
	}
148
	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
149
	if (ptr) {
150
		*ptr = bo->kptr;
151
	}
152
	radeon_bo_check_tiling(bo, 0, 0);
153 154 155
	return 0;
}

156
void radeon_bo_kunmap(struct radeon_bo *bo)
157
{
158
	if (bo->kptr == NULL)
159
		return;
160 161 162
	bo->kptr = NULL;
	radeon_bo_check_tiling(bo, 0, 0);
	ttm_bo_kunmap(&bo->kmap);
163 164
}

165
void radeon_bo_unref(struct radeon_bo **bo)
166
{
167
	struct ttm_buffer_object *tbo;
168

169
	if ((*bo) == NULL)
170
		return;
171 172 173 174
	tbo = &((*bo)->tbo);
	ttm_bo_unref(&tbo);
	if (tbo == NULL)
		*bo = NULL;
175 176
}

177
int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
178
{
179
	int r, i;
180

181 182 183 184
	if (bo->pin_count) {
		bo->pin_count++;
		if (gpu_addr)
			*gpu_addr = radeon_bo_gpu_offset(bo);
185 186
		return 0;
	}
187
	radeon_ttm_placement_from_domain(bo, domain);
188 189 190 191
	if (domain == RADEON_GEM_DOMAIN_VRAM) {
		/* force to pin into visible video ram */
		bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	}
192 193
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
194
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
195 196 197 198
	if (likely(r == 0)) {
		bo->pin_count = 1;
		if (gpu_addr != NULL)
			*gpu_addr = radeon_bo_gpu_offset(bo);
199
	}
200
	if (unlikely(r != 0))
201
		dev_err(bo->rdev->dev, "%p pin failed\n", bo);
202 203 204
	return r;
}

205
int radeon_bo_unpin(struct radeon_bo *bo)
206
{
207
	int r, i;
208

209 210 211
	if (!bo->pin_count) {
		dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
		return 0;
212
	}
213 214 215
	bo->pin_count--;
	if (bo->pin_count)
		return 0;
216 217
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
218
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
219
	if (unlikely(r != 0))
220
		dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
221
	return r;
222 223
}

224
int radeon_bo_evict_vram(struct radeon_device *rdev)
225
{
226 227
	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
	if (0 && (rdev->flags & RADEON_IS_IGP)) {
228 229 230
		if (rdev->mc.igp_sideport_enabled == false)
			/* Useless to evict on IGP chips */
			return 0;
231 232 233 234
	}
	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
}

235
void radeon_bo_force_delete(struct radeon_device *rdev)
236
{
237
	struct radeon_bo *bo, *n;
238 239 240 241 242
	struct drm_gem_object *gobj;

	if (list_empty(&rdev->gem.objects)) {
		return;
	}
243 244
	dev_err(rdev->dev, "Userspace still has active objects !\n");
	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
245
		mutex_lock(&rdev->ddev->struct_mutex);
246 247 248 249 250 251 252 253
		gobj = bo->gobj;
		dev_err(rdev->dev, "%p %p %lu %lu force free\n",
			gobj, bo, (unsigned long)gobj->size,
			*((unsigned long *)&gobj->refcount));
		mutex_lock(&bo->rdev->gem.mutex);
		list_del_init(&bo->list);
		mutex_unlock(&bo->rdev->gem.mutex);
		radeon_bo_unref(&bo);
254 255 256 257 258 259
		gobj->driver_private = NULL;
		drm_gem_object_unreference(gobj);
		mutex_unlock(&rdev->ddev->struct_mutex);
	}
}

260
int radeon_bo_init(struct radeon_device *rdev)
261
{
262 263 264 265 266 267 268 269
	/* Add an MTRR for the VRAM */
	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
			MTRR_TYPE_WRCOMB, 1);
	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
		rdev->mc.mc_vram_size >> 20,
		(unsigned long long)rdev->mc.aper_size >> 20);
	DRM_INFO("RAM width %dbits %cDR\n",
			rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
270 271 272
	return radeon_ttm_init(rdev);
}

273
void radeon_bo_fini(struct radeon_device *rdev)
274 275 276 277
{
	radeon_ttm_fini(rdev);
}

278 279
void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
				struct list_head *head)
280 281 282 283 284 285 286 287
{
	if (lobj->wdomain) {
		list_add(&lobj->list, head);
	} else {
		list_add_tail(&lobj->list, head);
	}
}

288
int radeon_bo_list_reserve(struct list_head *head)
289
{
290
	struct radeon_bo_list *lobj;
291 292
	int r;

293
	list_for_each_entry(lobj, head, list){
294 295 296
		r = radeon_bo_reserve(lobj->bo, false);
		if (unlikely(r != 0))
			return r;
297 298 299 300
	}
	return 0;
}

301
void radeon_bo_list_unreserve(struct list_head *head)
302
{
303
	struct radeon_bo_list *lobj;
304

305
	list_for_each_entry(lobj, head, list) {
306 307 308
		/* only unreserve object we successfully reserved */
		if (radeon_bo_is_reserved(lobj->bo))
			radeon_bo_unreserve(lobj->bo);
309 310 311
	}
}

312
int radeon_bo_list_validate(struct list_head *head)
313
{
314 315
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
316 317
	int r;

318
	r = radeon_bo_list_reserve(head);
319 320 321
	if (unlikely(r != 0)) {
		return r;
	}
322
	list_for_each_entry(lobj, head, list) {
323 324
		bo = lobj->bo;
		if (!bo->pin_count) {
325
			if (lobj->wdomain) {
326 327
				radeon_ttm_placement_from_domain(bo,
								lobj->wdomain);
328
			} else {
329 330
				radeon_ttm_placement_from_domain(bo,
								lobj->rdomain);
331
			}
332
			r = ttm_bo_validate(&bo->tbo, &bo->placement,
333
						true, false, false);
334
			if (unlikely(r))
335 336
				return r;
		}
337 338
		lobj->gpu_offset = radeon_bo_gpu_offset(bo);
		lobj->tiling_flags = bo->tiling_flags;
339 340 341 342
	}
	return 0;
}

343
void radeon_bo_list_fence(struct list_head *head, void *fence)
344
{
345
	struct radeon_bo_list *lobj;
346 347 348 349 350 351 352 353 354 355 356 357
	struct radeon_bo *bo;
	struct radeon_fence *old_fence = NULL;

	list_for_each_entry(lobj, head, list) {
		bo = lobj->bo;
		spin_lock(&bo->tbo.lock);
		old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
		bo->tbo.sync_obj = radeon_fence_ref(fence);
		bo->tbo.sync_obj_arg = NULL;
		spin_unlock(&bo->tbo.lock);
		if (old_fence) {
			radeon_fence_unref(&old_fence);
358
		}
359
	}
360 361
}

362
int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
363 364
			     struct vm_area_struct *vma)
{
365
	return ttm_fbdev_mmap(vma, &bo->tbo);
366 367
}

368
int radeon_bo_get_surface_reg(struct radeon_bo *bo)
369
{
370
	struct radeon_device *rdev = bo->rdev;
371
	struct radeon_surface_reg *reg;
372
	struct radeon_bo *old_object;
373 374 375
	int steal;
	int i;

376 377 378
	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!bo->tiling_flags)
379 380
		return 0;

381 382 383
	if (bo->surface_reg >= 0) {
		reg = &rdev->surface_regs[bo->surface_reg];
		i = bo->surface_reg;
384 385 386 387 388 389 390
		goto out;
	}

	steal = -1;
	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {

		reg = &rdev->surface_regs[i];
391
		if (!reg->bo)
392 393
			break;

394
		old_object = reg->bo;
395 396 397 398 399 400 401 402 403 404
		if (old_object->pin_count == 0)
			steal = i;
	}

	/* if we are all out */
	if (i == RADEON_GEM_MAX_SURFACES) {
		if (steal == -1)
			return -ENOMEM;
		/* find someone with a surface reg and nuke their BO */
		reg = &rdev->surface_regs[steal];
405
		old_object = reg->bo;
406 407
		/* blow away the mapping */
		DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
408
		ttm_bo_unmap_virtual(&old_object->tbo);
409 410 411 412
		old_object->surface_reg = -1;
		i = steal;
	}

413 414
	bo->surface_reg = i;
	reg->bo = bo;
415 416

out:
417 418 419
	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
			       bo->tbo.mem.mm_node->start << PAGE_SHIFT,
			       bo->tbo.num_pages << PAGE_SHIFT);
420 421 422
	return 0;
}

423
static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
424
{
425
	struct radeon_device *rdev = bo->rdev;
426 427
	struct radeon_surface_reg *reg;

428
	if (bo->surface_reg == -1)
429 430
		return;

431 432
	reg = &rdev->surface_regs[bo->surface_reg];
	radeon_clear_surface_reg(rdev, bo->surface_reg);
433

434 435
	reg->bo = NULL;
	bo->surface_reg = -1;
436 437
}

438 439
int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
				uint32_t tiling_flags, uint32_t pitch)
440
{
441 442 443 444 445 446 447 448 449
	int r;

	r = radeon_bo_reserve(bo, false);
	if (unlikely(r != 0))
		return r;
	bo->tiling_flags = tiling_flags;
	bo->pitch = pitch;
	radeon_bo_unreserve(bo);
	return 0;
450 451
}

452 453 454
void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
				uint32_t *tiling_flags,
				uint32_t *pitch)
455
{
456
	BUG_ON(!atomic_read(&bo->tbo.reserved));
457
	if (tiling_flags)
458
		*tiling_flags = bo->tiling_flags;
459
	if (pitch)
460
		*pitch = bo->pitch;
461 462
}

463 464
int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
				bool force_drop)
465
{
466 467 468
	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
469 470 471
		return 0;

	if (force_drop) {
472
		radeon_bo_clear_surface_reg(bo);
473 474 475
		return 0;
	}

476
	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
477 478 479
		if (!has_moved)
			return 0;

480 481
		if (bo->surface_reg >= 0)
			radeon_bo_clear_surface_reg(bo);
482 483 484
		return 0;
	}

485
	if ((bo->surface_reg >= 0) && !has_moved)
486 487
		return 0;

488
	return radeon_bo_get_surface_reg(bo);
489 490 491
}

void radeon_bo_move_notify(struct ttm_buffer_object *bo,
492
			   struct ttm_mem_reg *mem)
493
{
494 495 496 497
	struct radeon_bo *rbo;
	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return;
	rbo = container_of(bo, struct radeon_bo, tbo);
498
	radeon_bo_check_tiling(rbo, 0, 1);
499 500 501 502
}

void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
503 504 505 506
	struct radeon_bo *rbo;
	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return;
	rbo = container_of(bo, struct radeon_bo, tbo);
507
	radeon_bo_check_tiling(rbo, 0, 0);
508
}