exynos_mixer.c 32.2 KB
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/*
 * Copyright (C) 2011 Samsung Electronics Co.Ltd
 * Authors:
 * Seung-Woo Kim <sw0312.kim@samsung.com>
 *	Inki Dae <inki.dae@samsung.com>
 *	Joonyoung Shim <jy0922.shim@samsung.com>
 *
 * Based on drivers/media/video/s5p-tv/mixer_reg.c
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

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#include <drm/drmP.h>
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#include "regs-mixer.h"
#include "regs-vp.h"

#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/clk.h>
#include <linux/regulator/consumer.h>
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#include <linux/of.h>
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#include <linux/component.h>
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#include <drm/exynos_drm.h>

#include "exynos_drm_drv.h"
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#include "exynos_drm_crtc.h"
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#include "exynos_drm_plane.h"
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#include "exynos_drm_iommu.h"
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#include "exynos_mixer.h"
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#define MIXER_WIN_NR		3
#define MIXER_DEFAULT_WIN	0
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struct mixer_resources {
	int			irq;
	void __iomem		*mixer_regs;
	void __iomem		*vp_regs;
	spinlock_t		reg_slock;
	struct clk		*mixer;
	struct clk		*vp;
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	struct clk		*hdmi;
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	struct clk		*sclk_mixer;
	struct clk		*sclk_hdmi;
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	struct clk		*mout_mixer;
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};

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enum mixer_version_id {
	MXR_VER_0_0_0_16,
	MXR_VER_16_0_33_0,
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	MXR_VER_128_0_0_184,
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};

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struct mixer_context {
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	struct platform_device *pdev;
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	struct device		*dev;
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	struct drm_device	*drm_dev;
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	struct exynos_drm_crtc	*crtc;
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	struct exynos_drm_plane	planes[MIXER_WIN_NR];
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	int			pipe;
	bool			interlace;
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	bool			powered;
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	bool			vp_enabled;
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	bool			has_sclk;
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	u32			int_en;
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	struct mutex		mixer_mutex;
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	struct mixer_resources	mixer_res;
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	enum mixer_version_id	mxr_ver;
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	wait_queue_head_t	wait_vsync_queue;
	atomic_t		wait_vsync_event;
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};

struct mixer_drv_data {
	enum mixer_version_id	version;
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	bool					is_vp_enabled;
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	bool					has_sclk;
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};

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static const u8 filter_y_horiz_tap8[] = {
	0,	-1,	-1,	-1,	-1,	-1,	-1,	-1,
	-1,	-1,	-1,	-1,	-1,	0,	0,	0,
	0,	2,	4,	5,	6,	6,	6,	6,
	6,	5,	5,	4,	3,	2,	1,	1,
	0,	-6,	-12,	-16,	-18,	-20,	-21,	-20,
	-20,	-18,	-16,	-13,	-10,	-8,	-5,	-2,
	127,	126,	125,	121,	114,	107,	99,	89,
	79,	68,	57,	46,	35,	25,	16,	8,
};

static const u8 filter_y_vert_tap4[] = {
	0,	-3,	-6,	-8,	-8,	-8,	-8,	-7,
	-6,	-5,	-4,	-3,	-2,	-1,	-1,	0,
	127,	126,	124,	118,	111,	102,	92,	81,
	70,	59,	48,	37,	27,	19,	11,	5,
	0,	5,	11,	19,	27,	37,	48,	59,
	70,	81,	92,	102,	111,	118,	124,	126,
	0,	0,	-1,	-1,	-2,	-3,	-4,	-5,
	-6,	-7,	-8,	-8,	-8,	-8,	-6,	-3,
};

static const u8 filter_cr_horiz_tap4[] = {
	0,	-3,	-6,	-8,	-8,	-8,	-8,	-7,
	-6,	-5,	-4,	-3,	-2,	-1,	-1,	0,
	127,	126,	124,	118,	111,	102,	92,	81,
	70,	59,	48,	37,	27,	19,	11,	5,
};

static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id)
{
	return readl(res->vp_regs + reg_id);
}

static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id,
				 u32 val)
{
	writel(val, res->vp_regs + reg_id);
}

static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id,
				 u32 val, u32 mask)
{
	u32 old = vp_reg_read(res, reg_id);

	val = (val & mask) | (old & ~mask);
	writel(val, res->vp_regs + reg_id);
}

static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id)
{
	return readl(res->mixer_regs + reg_id);
}

static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id,
				 u32 val)
{
	writel(val, res->mixer_regs + reg_id);
}

static inline void mixer_reg_writemask(struct mixer_resources *res,
				 u32 reg_id, u32 val, u32 mask)
{
	u32 old = mixer_reg_read(res, reg_id);

	val = (val & mask) | (old & ~mask);
	writel(val, res->mixer_regs + reg_id);
}

static void mixer_regs_dump(struct mixer_context *ctx)
{
#define DUMPREG(reg_id) \
do { \
	DRM_DEBUG_KMS(#reg_id " = %08x\n", \
		(u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \
} while (0)

	DUMPREG(MXR_STATUS);
	DUMPREG(MXR_CFG);
	DUMPREG(MXR_INT_EN);
	DUMPREG(MXR_INT_STATUS);

	DUMPREG(MXR_LAYER_CFG);
	DUMPREG(MXR_VIDEO_CFG);

	DUMPREG(MXR_GRAPHIC0_CFG);
	DUMPREG(MXR_GRAPHIC0_BASE);
	DUMPREG(MXR_GRAPHIC0_SPAN);
	DUMPREG(MXR_GRAPHIC0_WH);
	DUMPREG(MXR_GRAPHIC0_SXY);
	DUMPREG(MXR_GRAPHIC0_DXY);

	DUMPREG(MXR_GRAPHIC1_CFG);
	DUMPREG(MXR_GRAPHIC1_BASE);
	DUMPREG(MXR_GRAPHIC1_SPAN);
	DUMPREG(MXR_GRAPHIC1_WH);
	DUMPREG(MXR_GRAPHIC1_SXY);
	DUMPREG(MXR_GRAPHIC1_DXY);
#undef DUMPREG
}

static void vp_regs_dump(struct mixer_context *ctx)
{
#define DUMPREG(reg_id) \
do { \
	DRM_DEBUG_KMS(#reg_id " = %08x\n", \
		(u32) readl(ctx->mixer_res.vp_regs + reg_id)); \
} while (0)

	DUMPREG(VP_ENABLE);
	DUMPREG(VP_SRESET);
	DUMPREG(VP_SHADOW_UPDATE);
	DUMPREG(VP_FIELD_ID);
	DUMPREG(VP_MODE);
	DUMPREG(VP_IMG_SIZE_Y);
	DUMPREG(VP_IMG_SIZE_C);
	DUMPREG(VP_PER_RATE_CTRL);
	DUMPREG(VP_TOP_Y_PTR);
	DUMPREG(VP_BOT_Y_PTR);
	DUMPREG(VP_TOP_C_PTR);
	DUMPREG(VP_BOT_C_PTR);
	DUMPREG(VP_ENDIAN_MODE);
	DUMPREG(VP_SRC_H_POSITION);
	DUMPREG(VP_SRC_V_POSITION);
	DUMPREG(VP_SRC_WIDTH);
	DUMPREG(VP_SRC_HEIGHT);
	DUMPREG(VP_DST_H_POSITION);
	DUMPREG(VP_DST_V_POSITION);
	DUMPREG(VP_DST_WIDTH);
	DUMPREG(VP_DST_HEIGHT);
	DUMPREG(VP_H_RATIO);
	DUMPREG(VP_V_RATIO);

#undef DUMPREG
}

static inline void vp_filter_set(struct mixer_resources *res,
		int reg_id, const u8 *data, unsigned int size)
{
	/* assure 4-byte align */
	BUG_ON(size & 3);
	for (; size; size -= 4, reg_id += 4, data += 4) {
		u32 val = (data[0] << 24) |  (data[1] << 16) |
			(data[2] << 8) | data[3];
		vp_reg_write(res, reg_id, val);
	}
}

static void vp_default_filter(struct mixer_resources *res)
{
	vp_filter_set(res, VP_POLY8_Y0_LL,
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		filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8));
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	vp_filter_set(res, VP_POLY4_Y0_LL,
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		filter_y_vert_tap4, sizeof(filter_y_vert_tap4));
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	vp_filter_set(res, VP_POLY4_C0_LL,
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		filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4));
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}

static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
{
	struct mixer_resources *res = &ctx->mixer_res;

	/* block update on vsync */
	mixer_reg_writemask(res, MXR_STATUS, enable ?
			MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);

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	if (ctx->vp_enabled)
		vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
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			VP_SHADOW_UPDATE_ENABLE : 0);
}

static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height)
{
	struct mixer_resources *res = &ctx->mixer_res;
	u32 val;

	/* choosing between interlace and progressive mode */
	val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE :
				MXR_CFG_SCAN_PROGRASSIVE);

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	if (ctx->mxr_ver != MXR_VER_128_0_0_184) {
		/* choosing between proper HD and SD mode */
		if (height <= 480)
			val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
		else if (height <= 576)
			val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
		else if (height <= 720)
			val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
		else if (height <= 1080)
			val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
		else
			val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
	}
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	mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
}

static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
{
	struct mixer_resources *res = &ctx->mixer_res;
	u32 val;

	if (height == 480) {
		val = MXR_CFG_RGB601_0_255;
	} else if (height == 576) {
		val = MXR_CFG_RGB601_0_255;
	} else if (height == 720) {
		val = MXR_CFG_RGB709_16_235;
		mixer_reg_write(res, MXR_CM_COEFF_Y,
				(1 << 30) | (94 << 20) | (314 << 10) |
				(32 << 0));
		mixer_reg_write(res, MXR_CM_COEFF_CB,
				(972 << 20) | (851 << 10) | (225 << 0));
		mixer_reg_write(res, MXR_CM_COEFF_CR,
				(225 << 20) | (820 << 10) | (1004 << 0));
	} else if (height == 1080) {
		val = MXR_CFG_RGB709_16_235;
		mixer_reg_write(res, MXR_CM_COEFF_Y,
				(1 << 30) | (94 << 20) | (314 << 10) |
				(32 << 0));
		mixer_reg_write(res, MXR_CM_COEFF_CB,
				(972 << 20) | (851 << 10) | (225 << 0));
		mixer_reg_write(res, MXR_CM_COEFF_CR,
				(225 << 20) | (820 << 10) | (1004 << 0));
	} else {
		val = MXR_CFG_RGB709_16_235;
		mixer_reg_write(res, MXR_CM_COEFF_Y,
				(1 << 30) | (94 << 20) | (314 << 10) |
				(32 << 0));
		mixer_reg_write(res, MXR_CM_COEFF_CB,
				(972 << 20) | (851 << 10) | (225 << 0));
		mixer_reg_write(res, MXR_CM_COEFF_CR,
				(225 << 20) | (820 << 10) | (1004 << 0));
	}

	mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
}

static void mixer_cfg_layer(struct mixer_context *ctx, int win, bool enable)
{
	struct mixer_resources *res = &ctx->mixer_res;
	u32 val = enable ? ~0 : 0;

	switch (win) {
	case 0:
		mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
		break;
	case 1:
		mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
		break;
	case 2:
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		if (ctx->vp_enabled) {
			vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
			mixer_reg_writemask(res, MXR_CFG, val,
				MXR_CFG_VP_ENABLE);
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			/* control blending of graphic layer 0 */
			mixer_reg_writemask(res, MXR_GRAPHIC_CFG(0), val,
					MXR_GRP_CFG_BLEND_PRE_MUL |
					MXR_GRP_CFG_PIXEL_BLEND_EN);
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		}
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		break;
	}
}

static void mixer_run(struct mixer_context *ctx)
{
	struct mixer_resources *res = &ctx->mixer_res;

	mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);

	mixer_regs_dump(ctx);
}

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static void mixer_stop(struct mixer_context *ctx)
{
	struct mixer_resources *res = &ctx->mixer_res;
	int timeout = 20;

	mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN);

	while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
			--timeout)
		usleep_range(10000, 12000);

	mixer_regs_dump(ctx);
}

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static void vp_video_buffer(struct mixer_context *ctx, int win)
{
	struct mixer_resources *res = &ctx->mixer_res;
	unsigned long flags;
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	struct exynos_drm_plane *plane;
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	unsigned int x_ratio, y_ratio;
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	unsigned int buf_num = 1;
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	dma_addr_t luma_addr[2], chroma_addr[2];
	bool tiled_mode = false;
	bool crcb_mode = false;
	u32 val;

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	plane = &ctx->planes[win];
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	switch (plane->pixel_format) {
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	case DRM_FORMAT_NV12:
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		crcb_mode = false;
		buf_num = 2;
		break;
	/* TODO: single buffer format NV12, NV21 */
	default:
		/* ignore pixel format at disable time */
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		if (!plane->dma_addr[0])
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			break;

		DRM_ERROR("pixel format for vp is wrong [%d].\n",
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				plane->pixel_format);
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		return;
	}

	/* scaling feature: (src << 16) / dst */
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	x_ratio = (plane->src_width << 16) / plane->crtc_width;
	y_ratio = (plane->src_height << 16) / plane->crtc_height;
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	if (buf_num == 2) {
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		luma_addr[0] = plane->dma_addr[0];
		chroma_addr[0] = plane->dma_addr[1];
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	} else {
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		luma_addr[0] = plane->dma_addr[0];
		chroma_addr[0] = plane->dma_addr[0]
			+ (plane->pitch * plane->fb_height);
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	}

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	if (plane->scan_flag & DRM_MODE_FLAG_INTERLACE) {
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		ctx->interlace = true;
		if (tiled_mode) {
			luma_addr[1] = luma_addr[0] + 0x40;
			chroma_addr[1] = chroma_addr[0] + 0x40;
		} else {
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			luma_addr[1] = luma_addr[0] + plane->pitch;
			chroma_addr[1] = chroma_addr[0] + plane->pitch;
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		}
	} else {
		ctx->interlace = false;
		luma_addr[1] = 0;
		chroma_addr[1] = 0;
	}

	spin_lock_irqsave(&res->reg_slock, flags);
	mixer_vsync_set_update(ctx, false);

	/* interlace or progressive scan mode */
	val = (ctx->interlace ? ~0 : 0);
	vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);

	/* setup format */
	val = (crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12);
	val |= (tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
	vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);

	/* setting size of input image */
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	vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(plane->pitch) |
		VP_IMG_VSIZE(plane->fb_height));
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	/* chroma height has to reduced by 2 to avoid chroma distorions */
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	vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(plane->pitch) |
		VP_IMG_VSIZE(plane->fb_height / 2));
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	vp_reg_write(res, VP_SRC_WIDTH, plane->src_width);
	vp_reg_write(res, VP_SRC_HEIGHT, plane->src_height);
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	vp_reg_write(res, VP_SRC_H_POSITION,
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			VP_SRC_H_POSITION_VAL(plane->fb_x));
	vp_reg_write(res, VP_SRC_V_POSITION, plane->fb_y);
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	vp_reg_write(res, VP_DST_WIDTH, plane->crtc_width);
	vp_reg_write(res, VP_DST_H_POSITION, plane->crtc_x);
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	if (ctx->interlace) {
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		vp_reg_write(res, VP_DST_HEIGHT, plane->crtc_height / 2);
		vp_reg_write(res, VP_DST_V_POSITION, plane->crtc_y / 2);
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	} else {
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		vp_reg_write(res, VP_DST_HEIGHT, plane->crtc_height);
		vp_reg_write(res, VP_DST_V_POSITION, plane->crtc_y);
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	}

	vp_reg_write(res, VP_H_RATIO, x_ratio);
	vp_reg_write(res, VP_V_RATIO, y_ratio);

	vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);

	/* set buffer address to vp */
	vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]);
	vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]);
	vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]);
	vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]);

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	mixer_cfg_scan(ctx, plane->mode_height);
	mixer_cfg_rgb_fmt(ctx, plane->mode_height);
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	mixer_cfg_layer(ctx, win, true);
	mixer_run(ctx);

	mixer_vsync_set_update(ctx, true);
	spin_unlock_irqrestore(&res->reg_slock, flags);

	vp_regs_dump(ctx);
}

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static void mixer_layer_update(struct mixer_context *ctx)
{
	struct mixer_resources *res = &ctx->mixer_res;

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	mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
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}

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static void mixer_graph_buffer(struct mixer_context *ctx, int win)
{
	struct mixer_resources *res = &ctx->mixer_res;
	unsigned long flags;
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	struct exynos_drm_plane *plane;
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	unsigned int x_ratio, y_ratio;
	unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
	dma_addr_t dma_addr;
	unsigned int fmt;
	u32 val;

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	plane = &ctx->planes[win];
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	#define RGB565 4
	#define ARGB1555 5
	#define ARGB4444 6
	#define ARGB8888 7

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	switch (plane->bpp) {
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	case 16:
		fmt = ARGB4444;
		break;
	case 32:
		fmt = ARGB8888;
		break;
	default:
		fmt = ARGB8888;
	}

	/* 2x scaling feature */
	x_ratio = 0;
	y_ratio = 0;

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	dst_x_offset = plane->crtc_x;
	dst_y_offset = plane->crtc_y;
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	/* converting dma address base and source offset */
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	dma_addr = plane->dma_addr[0]
		+ (plane->fb_x * plane->bpp >> 3)
		+ (plane->fb_y * plane->pitch);
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	src_x_offset = 0;
	src_y_offset = 0;

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	if (plane->scan_flag & DRM_MODE_FLAG_INTERLACE)
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		ctx->interlace = true;
	else
		ctx->interlace = false;

	spin_lock_irqsave(&res->reg_slock, flags);
	mixer_vsync_set_update(ctx, false);

	/* setup format */
	mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
		MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK);

	/* setup geometry */
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	mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
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			plane->pitch / (plane->bpp >> 3));
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	/* setup display size */
	if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
		win == MIXER_DEFAULT_WIN) {
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		val  = MXR_MXR_RES_HEIGHT(plane->mode_height);
		val |= MXR_MXR_RES_WIDTH(plane->mode_width);
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		mixer_reg_write(res, MXR_RESOLUTION, val);
	}

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	val  = MXR_GRP_WH_WIDTH(plane->crtc_width);
	val |= MXR_GRP_WH_HEIGHT(plane->crtc_height);
571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587
	val |= MXR_GRP_WH_H_SCALE(x_ratio);
	val |= MXR_GRP_WH_V_SCALE(y_ratio);
	mixer_reg_write(res, MXR_GRAPHIC_WH(win), val);

	/* setup offsets in source image */
	val  = MXR_GRP_SXY_SX(src_x_offset);
	val |= MXR_GRP_SXY_SY(src_y_offset);
	mixer_reg_write(res, MXR_GRAPHIC_SXY(win), val);

	/* setup offsets in display image */
	val  = MXR_GRP_DXY_DX(dst_x_offset);
	val |= MXR_GRP_DXY_DY(dst_y_offset);
	mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val);

	/* set buffer address to mixer */
	mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr);

588 589
	mixer_cfg_scan(ctx, plane->mode_height);
	mixer_cfg_rgb_fmt(ctx, plane->mode_height);
590
	mixer_cfg_layer(ctx, win, true);
591 592

	/* layer update mandatory for mixer 16.0.33.0 */
593 594
	if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
		ctx->mxr_ver == MXR_VER_128_0_0_184)
595 596
		mixer_layer_update(ctx);

597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612
	mixer_run(ctx);

	mixer_vsync_set_update(ctx, true);
	spin_unlock_irqrestore(&res->reg_slock, flags);
}

static void vp_win_reset(struct mixer_context *ctx)
{
	struct mixer_resources *res = &ctx->mixer_res;
	int tries = 100;

	vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING);
	for (tries = 100; tries; --tries) {
		/* waiting until VP_SRESET_PROCESSING is 0 */
		if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING)
			break;
613
		usleep_range(10000, 12000);
614 615 616 617
	}
	WARN(tries == 0, "failed to reset Video Processor\n");
}

618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643
static void mixer_win_reset(struct mixer_context *ctx)
{
	struct mixer_resources *res = &ctx->mixer_res;
	unsigned long flags;
	u32 val; /* value stored to register */

	spin_lock_irqsave(&res->reg_slock, flags);
	mixer_vsync_set_update(ctx, false);

	mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);

	/* set output in RGB888 mode */
	mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);

	/* 16 beat burst in DMA */
	mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST,
		MXR_STATUS_BURST_MASK);

	/* setting default layer priority: layer1 > layer0 > video
	 * because typical usage scenario would be
	 * layer1 - OSD
	 * layer0 - framebuffer
	 * video - video overlay
	 */
	val = MXR_LAYER_CFG_GRP1_VAL(3);
	val |= MXR_LAYER_CFG_GRP0_VAL(2);
644 645
	if (ctx->vp_enabled)
		val |= MXR_LAYER_CFG_VP_VAL(1);
646 647 648 649 650 651 652 653 654 655 656 657
	mixer_reg_write(res, MXR_LAYER_CFG, val);

	/* setting background color */
	mixer_reg_write(res, MXR_BG_COLOR0, 0x008080);
	mixer_reg_write(res, MXR_BG_COLOR1, 0x008080);
	mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);

	/* setting graphical layers */
	val  = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
	val |= MXR_GRP_CFG_WIN_BLEND_EN;
	val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */

658
	/* Don't blend layer 0 onto the mixer background */
659
	mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
660 661 662 663

	/* Blend layer 1 into layer 0 */
	val |= MXR_GRP_CFG_BLEND_PRE_MUL;
	val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
664 665
	mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);

666 667 668 669
	/* setting video layers */
	val = MXR_GRP_CFG_ALPHA_VAL(0);
	mixer_reg_write(res, MXR_VIDEO_CFG, val);

670 671 672 673 674
	if (ctx->vp_enabled) {
		/* configuration of Video Processor Registers */
		vp_win_reset(ctx);
		vp_default_filter(res);
	}
675 676 677 678

	/* disable all layers */
	mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
	mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
679 680
	if (ctx->vp_enabled)
		mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
681 682 683 684 685

	mixer_vsync_set_update(ctx, true);
	spin_unlock_irqrestore(&res->reg_slock, flags);
}

686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750
static irqreturn_t mixer_irq_handler(int irq, void *arg)
{
	struct mixer_context *ctx = arg;
	struct mixer_resources *res = &ctx->mixer_res;
	u32 val, base, shadow;

	spin_lock(&res->reg_slock);

	/* read interrupt status for handling and clearing flags for VSYNC */
	val = mixer_reg_read(res, MXR_INT_STATUS);

	/* handling VSYNC */
	if (val & MXR_INT_STATUS_VSYNC) {
		/* interlace scan need to check shadow register */
		if (ctx->interlace) {
			base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
			shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
			if (base != shadow)
				goto out;

			base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1));
			shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));
			if (base != shadow)
				goto out;
		}

		drm_handle_vblank(ctx->drm_dev, ctx->pipe);
		exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);

		/* set wait vsync event to zero and wake up queue. */
		if (atomic_read(&ctx->wait_vsync_event)) {
			atomic_set(&ctx->wait_vsync_event, 0);
			wake_up(&ctx->wait_vsync_queue);
		}
	}

out:
	/* clear interrupts */
	if (~val & MXR_INT_EN_VSYNC) {
		/* vsync interrupt use different bit for read and clear */
		val &= ~MXR_INT_EN_VSYNC;
		val |= MXR_INT_CLEAR_VSYNC;
	}
	mixer_reg_write(res, MXR_INT_STATUS, val);

	spin_unlock(&res->reg_slock);

	return IRQ_HANDLED;
}

static int mixer_resources_init(struct mixer_context *mixer_ctx)
{
	struct device *dev = &mixer_ctx->pdev->dev;
	struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
	struct resource *res;
	int ret;

	spin_lock_init(&mixer_res->reg_slock);

	mixer_res->mixer = devm_clk_get(dev, "mixer");
	if (IS_ERR(mixer_res->mixer)) {
		dev_err(dev, "failed to get clock 'mixer'\n");
		return -ENODEV;
	}

751 752 753 754 755 756
	mixer_res->hdmi = devm_clk_get(dev, "hdmi");
	if (IS_ERR(mixer_res->hdmi)) {
		dev_err(dev, "failed to get clock 'hdmi'\n");
		return PTR_ERR(mixer_res->hdmi);
	}

757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803
	mixer_res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
	if (IS_ERR(mixer_res->sclk_hdmi)) {
		dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
		return -ENODEV;
	}
	res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		dev_err(dev, "get memory resource failed.\n");
		return -ENXIO;
	}

	mixer_res->mixer_regs = devm_ioremap(dev, res->start,
							resource_size(res));
	if (mixer_res->mixer_regs == NULL) {
		dev_err(dev, "register mapping failed.\n");
		return -ENXIO;
	}

	res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_IRQ, 0);
	if (res == NULL) {
		dev_err(dev, "get interrupt resource failed.\n");
		return -ENXIO;
	}

	ret = devm_request_irq(dev, res->start, mixer_irq_handler,
						0, "drm_mixer", mixer_ctx);
	if (ret) {
		dev_err(dev, "request interrupt failed.\n");
		return ret;
	}
	mixer_res->irq = res->start;

	return 0;
}

static int vp_resources_init(struct mixer_context *mixer_ctx)
{
	struct device *dev = &mixer_ctx->pdev->dev;
	struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
	struct resource *res;

	mixer_res->vp = devm_clk_get(dev, "vp");
	if (IS_ERR(mixer_res->vp)) {
		dev_err(dev, "failed to get clock 'vp'\n");
		return -ENODEV;
	}

804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819
	if (mixer_ctx->has_sclk) {
		mixer_res->sclk_mixer = devm_clk_get(dev, "sclk_mixer");
		if (IS_ERR(mixer_res->sclk_mixer)) {
			dev_err(dev, "failed to get clock 'sclk_mixer'\n");
			return -ENODEV;
		}
		mixer_res->mout_mixer = devm_clk_get(dev, "mout_mixer");
		if (IS_ERR(mixer_res->mout_mixer)) {
			dev_err(dev, "failed to get clock 'mout_mixer'\n");
			return -ENODEV;
		}

		if (mixer_res->sclk_hdmi && mixer_res->mout_mixer)
			clk_set_parent(mixer_res->mout_mixer,
				       mixer_res->sclk_hdmi);
	}
820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836

	res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1);
	if (res == NULL) {
		dev_err(dev, "get memory resource failed.\n");
		return -ENXIO;
	}

	mixer_res->vp_regs = devm_ioremap(dev, res->start,
							resource_size(res));
	if (mixer_res->vp_regs == NULL) {
		dev_err(dev, "register mapping failed.\n");
		return -ENXIO;
	}

	return 0;
}

837
static int mixer_initialize(struct mixer_context *mixer_ctx,
838
			struct drm_device *drm_dev)
839 840
{
	int ret;
841 842
	struct exynos_drm_private *priv;
	priv = drm_dev->dev_private;
843

844
	mixer_ctx->drm_dev = drm_dev;
845
	mixer_ctx->pipe = priv->pipe++;
846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862

	/* acquire resources: regs, irqs, clocks */
	ret = mixer_resources_init(mixer_ctx);
	if (ret) {
		DRM_ERROR("mixer_resources_init failed ret=%d\n", ret);
		return ret;
	}

	if (mixer_ctx->vp_enabled) {
		/* acquire vp resources: regs, irqs, clocks */
		ret = vp_resources_init(mixer_ctx);
		if (ret) {
			DRM_ERROR("vp_resources_init failed ret=%d\n", ret);
			return ret;
		}
	}

863 864 865 866
	if (!is_drm_iommu_supported(mixer_ctx->drm_dev))
		return 0;

	return drm_iommu_attach_device(mixer_ctx->drm_dev, mixer_ctx->dev);
867 868
}

869
static void mixer_ctx_remove(struct mixer_context *mixer_ctx)
870
{
871 872
	if (is_drm_iommu_supported(mixer_ctx->drm_dev))
		drm_iommu_detach_device(mixer_ctx->drm_dev, mixer_ctx->dev);
873 874
}

875
static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
876
{
877
	struct mixer_context *mixer_ctx = crtc->ctx;
878 879
	struct mixer_resources *res = &mixer_ctx->mixer_res;

880 881 882 883
	if (!mixer_ctx->powered) {
		mixer_ctx->int_en |= MXR_INT_EN_VSYNC;
		return 0;
	}
884 885 886 887 888 889 890 891

	/* enable vsync interrupt */
	mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
			MXR_INT_EN_VSYNC);

	return 0;
}

892
static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
893
{
894
	struct mixer_context *mixer_ctx = crtc->ctx;
895 896 897 898 899 900
	struct mixer_resources *res = &mixer_ctx->mixer_res;

	/* disable vsync interrupt */
	mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
}

901
static void mixer_win_commit(struct exynos_drm_crtc *crtc, int zpos)
902
{
903
	struct mixer_context *mixer_ctx = crtc->ctx;
904
	int win = zpos == DEFAULT_ZPOS ? MIXER_DEFAULT_WIN : zpos;
905

906
	DRM_DEBUG_KMS("win: %d\n", win);
907

908 909 910 911 912 913 914
	mutex_lock(&mixer_ctx->mixer_mutex);
	if (!mixer_ctx->powered) {
		mutex_unlock(&mixer_ctx->mixer_mutex);
		return;
	}
	mutex_unlock(&mixer_ctx->mixer_mutex);

915
	if (win > 1 && mixer_ctx->vp_enabled)
916 917 918
		vp_video_buffer(mixer_ctx, win);
	else
		mixer_graph_buffer(mixer_ctx, win);
919

920
	mixer_ctx->planes[win].enabled = true;
921 922
}

923
static void mixer_win_disable(struct exynos_drm_crtc *crtc, int zpos)
924
{
925
	struct mixer_context *mixer_ctx = crtc->ctx;
926
	struct mixer_resources *res = &mixer_ctx->mixer_res;
927
	int win = zpos == DEFAULT_ZPOS ? MIXER_DEFAULT_WIN : zpos;
928 929
	unsigned long flags;

930
	DRM_DEBUG_KMS("win: %d\n", win);
931

932 933 934
	mutex_lock(&mixer_ctx->mixer_mutex);
	if (!mixer_ctx->powered) {
		mutex_unlock(&mixer_ctx->mixer_mutex);
935
		mixer_ctx->planes[win].resume = false;
936 937 938 939
		return;
	}
	mutex_unlock(&mixer_ctx->mixer_mutex);

940 941 942 943 944 945 946
	spin_lock_irqsave(&res->reg_slock, flags);
	mixer_vsync_set_update(mixer_ctx, false);

	mixer_cfg_layer(mixer_ctx, win, false);

	mixer_vsync_set_update(mixer_ctx, true);
	spin_unlock_irqrestore(&res->reg_slock, flags);
947

948
	mixer_ctx->planes[win].enabled = false;
949 950
}

951
static void mixer_wait_for_vblank(struct exynos_drm_crtc *crtc)
952
{
953
	struct mixer_context *mixer_ctx = crtc->ctx;
954
	int err;
955

956 957 958 959 960 961 962
	mutex_lock(&mixer_ctx->mixer_mutex);
	if (!mixer_ctx->powered) {
		mutex_unlock(&mixer_ctx->mixer_mutex);
		return;
	}
	mutex_unlock(&mixer_ctx->mixer_mutex);

963
	err = drm_vblank_get(mixer_ctx->drm_dev, mixer_ctx->pipe);
964 965 966 967
	if (err < 0) {
		DRM_DEBUG_KMS("failed to acquire vblank counter\n");
		return;
	}
968

969 970 971 972 973 974 975 976
	atomic_set(&mixer_ctx->wait_vsync_event, 1);

	/*
	 * wait for MIXER to signal VSYNC interrupt or return after
	 * timeout which is set to 50ms (refresh rate of 20).
	 */
	if (!wait_event_timeout(mixer_ctx->wait_vsync_queue,
				!atomic_read(&mixer_ctx->wait_vsync_event),
D
Daniel Vetter 已提交
977
				HZ/20))
978
		DRM_DEBUG_KMS("vblank wait timed out.\n");
979

980
	drm_vblank_put(mixer_ctx->drm_dev, mixer_ctx->pipe);
981 982
}

983
static void mixer_window_suspend(struct mixer_context *ctx)
984
{
985
	struct exynos_drm_plane *plane;
986 987 988
	int i;

	for (i = 0; i < MIXER_WIN_NR; i++) {
989 990
		plane = &ctx->planes[i];
		plane->resume = plane->enabled;
991
		mixer_win_disable(ctx->crtc, i);
992
	}
993
	mixer_wait_for_vblank(ctx->crtc);
994 995
}

996
static void mixer_window_resume(struct mixer_context *ctx)
997
{
998
	struct exynos_drm_plane *plane;
999 1000 1001
	int i;

	for (i = 0; i < MIXER_WIN_NR; i++) {
1002 1003 1004 1005
		plane = &ctx->planes[i];
		plane->enabled = plane->resume;
		plane->resume = false;
		if (plane->enabled)
1006
			mixer_win_commit(ctx->crtc, i);
1007 1008 1009
	}
}

1010
static void mixer_poweron(struct mixer_context *ctx)
1011 1012 1013 1014 1015 1016 1017 1018
{
	struct mixer_resources *res = &ctx->mixer_res;

	mutex_lock(&ctx->mixer_mutex);
	if (ctx->powered) {
		mutex_unlock(&ctx->mixer_mutex);
		return;
	}
1019

1020 1021
	mutex_unlock(&ctx->mixer_mutex);

1022 1023
	pm_runtime_get_sync(ctx->dev);

1024
	clk_prepare_enable(res->mixer);
1025
	clk_prepare_enable(res->hdmi);
1026
	if (ctx->vp_enabled) {
1027
		clk_prepare_enable(res->vp);
1028 1029
		if (ctx->has_sclk)
			clk_prepare_enable(res->sclk_mixer);
1030 1031
	}

1032 1033 1034 1035
	mutex_lock(&ctx->mixer_mutex);
	ctx->powered = true;
	mutex_unlock(&ctx->mixer_mutex);

1036 1037
	mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);

1038 1039 1040
	mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
	mixer_win_reset(ctx);

1041
	mixer_window_resume(ctx);
1042 1043
}

1044
static void mixer_poweroff(struct mixer_context *ctx)
1045 1046 1047 1048
{
	struct mixer_resources *res = &ctx->mixer_res;

	mutex_lock(&ctx->mixer_mutex);
1049 1050 1051 1052
	if (!ctx->powered) {
		mutex_unlock(&ctx->mixer_mutex);
		return;
	}
1053 1054
	mutex_unlock(&ctx->mixer_mutex);

1055
	mixer_stop(ctx);
1056
	mixer_window_suspend(ctx);
1057 1058 1059

	ctx->int_en = mixer_reg_read(res, MXR_INT_EN);

1060 1061 1062 1063
	mutex_lock(&ctx->mixer_mutex);
	ctx->powered = false;
	mutex_unlock(&ctx->mixer_mutex);

1064
	clk_disable_unprepare(res->hdmi);
1065
	clk_disable_unprepare(res->mixer);
1066
	if (ctx->vp_enabled) {
1067
		clk_disable_unprepare(res->vp);
1068 1069
		if (ctx->has_sclk)
			clk_disable_unprepare(res->sclk_mixer);
1070 1071
	}

1072
	pm_runtime_put_sync(ctx->dev);
1073 1074
}

1075
static void mixer_dpms(struct exynos_drm_crtc *crtc, int mode)
1076 1077 1078
{
	switch (mode) {
	case DRM_MODE_DPMS_ON:
1079
		mixer_poweron(crtc->ctx);
1080 1081 1082 1083
		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
1084
		mixer_poweroff(crtc->ctx);
1085 1086 1087 1088 1089 1090 1091
		break;
	default:
		DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
		break;
	}
}

1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111
/* Only valid for Mixer version 16.0.33.0 */
int mixer_check_mode(struct drm_display_mode *mode)
{
	u32 w, h;

	w = mode->hdisplay;
	h = mode->vdisplay;

	DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n",
		mode->hdisplay, mode->vdisplay, mode->vrefresh,
		(mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);

	if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) ||
		(w >= 1024 && w <= 1280 && h >= 576 && h <= 720) ||
		(w >= 1664 && w <= 1920 && h >= 936 && h <= 1080))
		return 0;

	return -EINVAL;
}

1112
static struct exynos_drm_crtc_ops mixer_crtc_ops = {
1113
	.dpms			= mixer_dpms,
1114 1115
	.enable_vblank		= mixer_enable_vblank,
	.disable_vblank		= mixer_disable_vblank,
1116
	.wait_for_vblank	= mixer_wait_for_vblank,
1117 1118
	.win_commit		= mixer_win_commit,
	.win_disable		= mixer_win_disable,
1119
};
1120

1121 1122 1123 1124 1125
static struct mixer_drv_data exynos5420_mxr_drv_data = {
	.version = MXR_VER_128_0_0_184,
	.is_vp_enabled = 0,
};

1126
static struct mixer_drv_data exynos5250_mxr_drv_data = {
1127 1128 1129 1130
	.version = MXR_VER_16_0_33_0,
	.is_vp_enabled = 0,
};

1131 1132 1133 1134 1135
static struct mixer_drv_data exynos4212_mxr_drv_data = {
	.version = MXR_VER_0_0_0_16,
	.is_vp_enabled = 1,
};

1136
static struct mixer_drv_data exynos4210_mxr_drv_data = {
1137
	.version = MXR_VER_0_0_0_16,
1138
	.is_vp_enabled = 1,
1139
	.has_sclk = 1,
1140 1141 1142 1143 1144
};

static struct platform_device_id mixer_driver_types[] = {
	{
		.name		= "s5p-mixer",
1145
		.driver_data	= (unsigned long)&exynos4210_mxr_drv_data,
1146 1147
	}, {
		.name		= "exynos5-mixer",
1148
		.driver_data	= (unsigned long)&exynos5250_mxr_drv_data,
1149 1150 1151 1152 1153 1154 1155
	}, {
		/* end node */
	}
};

static struct of_device_id mixer_match_types[] = {
	{
1156 1157 1158 1159 1160 1161
		.compatible = "samsung,exynos4210-mixer",
		.data	= &exynos4210_mxr_drv_data,
	}, {
		.compatible = "samsung,exynos4212-mixer",
		.data	= &exynos4212_mxr_drv_data,
	}, {
1162
		.compatible = "samsung,exynos5-mixer",
1163 1164 1165 1166
		.data	= &exynos5250_mxr_drv_data,
	}, {
		.compatible = "samsung,exynos5250-mixer",
		.data	= &exynos5250_mxr_drv_data,
1167 1168 1169
	}, {
		.compatible = "samsung,exynos5420-mixer",
		.data	= &exynos5420_mxr_drv_data,
1170 1171 1172 1173
	}, {
		/* end node */
	}
};
1174
MODULE_DEVICE_TABLE(of, mixer_match_types);
1175

1176
static int mixer_bind(struct device *dev, struct device *manager, void *data)
1177
{
1178
	struct mixer_context *ctx = dev_get_drvdata(dev);
1179
	struct drm_device *drm_dev = data;
1180 1181 1182
	struct exynos_drm_plane *exynos_plane;
	enum drm_plane_type type;
	int zpos, ret;
1183

1184 1185 1186 1187
	ret = mixer_initialize(ctx, drm_dev);
	if (ret)
		return ret;

1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200
	for (zpos = 0; zpos < MIXER_WIN_NR; zpos++) {
		type = (zpos == MIXER_DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY :
						DRM_PLANE_TYPE_OVERLAY;
		ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
					1 << ctx->pipe, type);
		if (ret)
			return ret;
	}

	exynos_plane = &ctx->planes[MIXER_DEFAULT_WIN];
	ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
					   ctx->pipe, EXYNOS_DISPLAY_TYPE_HDMI,
					   &mixer_crtc_ops, ctx);
1201
	if (IS_ERR(ctx->crtc)) {
1202
		mixer_ctx_remove(ctx);
1203 1204
		ret = PTR_ERR(ctx->crtc);
		goto free_ctx;
1205
	}
1206 1207

	return 0;
1208 1209 1210 1211

free_ctx:
	devm_kfree(dev, ctx);
	return ret;
1212 1213
}

1214
static void mixer_unbind(struct device *dev, struct device *master, void *data)
1215
{
1216
	struct mixer_context *ctx = dev_get_drvdata(dev);
1217

1218
	mixer_ctx_remove(ctx);
1219 1220 1221 1222 1223 1224 1225 1226 1227
}

static const struct component_ops mixer_component_ops = {
	.bind	= mixer_bind,
	.unbind	= mixer_unbind,
};

static int mixer_probe(struct platform_device *pdev)
{
1228 1229 1230
	struct device *dev = &pdev->dev;
	struct mixer_drv_data *drv;
	struct mixer_context *ctx;
1231 1232
	int ret;

1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260
	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
	if (!ctx) {
		DRM_ERROR("failed to alloc mixer context.\n");
		return -ENOMEM;
	}

	mutex_init(&ctx->mixer_mutex);

	if (dev->of_node) {
		const struct of_device_id *match;

		match = of_match_node(mixer_match_types, dev->of_node);
		drv = (struct mixer_drv_data *)match->data;
	} else {
		drv = (struct mixer_drv_data *)
			platform_get_device_id(pdev)->driver_data;
	}

	ctx->pdev = pdev;
	ctx->dev = dev;
	ctx->vp_enabled = drv->is_vp_enabled;
	ctx->has_sclk = drv->has_sclk;
	ctx->mxr_ver = drv->version;
	init_waitqueue_head(&ctx->wait_vsync_queue);
	atomic_set(&ctx->wait_vsync_event, 0);

	platform_set_drvdata(pdev, ctx);

1261
	ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC,
1262
					EXYNOS_DISPLAY_TYPE_HDMI);
1263 1264 1265 1266
	if (ret)
		return ret;

	ret = component_add(&pdev->dev, &mixer_component_ops);
1267
	if (ret) {
1268
		exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1269 1270 1271 1272
		return ret;
	}

	pm_runtime_enable(dev);
1273 1274

	return ret;
1275 1276 1277 1278
}

static int mixer_remove(struct platform_device *pdev)
{
1279 1280
	pm_runtime_disable(&pdev->dev);

1281 1282 1283
	component_del(&pdev->dev, &mixer_component_ops);
	exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);

1284 1285 1286 1287 1288
	return 0;
}

struct platform_driver mixer_driver = {
	.driver = {
1289
		.name = "exynos-mixer",
1290
		.owner = THIS_MODULE,
1291
		.of_match_table = mixer_match_types,
1292 1293
	},
	.probe = mixer_probe,
1294
	.remove = mixer_remove,
1295
	.id_table	= mixer_driver_types,
1296
};
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