omap_hsmmc.c 54.5 KB
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/*
 * drivers/mmc/host/omap_hsmmc.c
 *
 * Driver for OMAP2430/3430 MMC controller.
 *
 * Copyright (C) 2007 Texas Instruments.
 *
 * Authors:
 *	Syed Mohammed Khasim	<x0khasim@ti.com>
 *	Madhusudhan		<madhu.cr@ti.com>
 *	Mohit Jalori		<mjalori@ti.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/module.h>
#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/debugfs.h>
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#include <linux/dmaengine.h>
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#include <linux/seq_file.h>
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#include <linux/sizes.h>
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#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/timer.h>
#include <linux/clk.h>
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#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_device.h>
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#include <linux/omap-dma.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/core.h>
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#include <linux/mmc/mmc.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/platform_data/mmc-omap.h>
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/* OMAP HSMMC Host Controller Registers */
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#define OMAP_HSMMC_SYSSTATUS	0x0014
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#define OMAP_HSMMC_CON		0x002C
#define OMAP_HSMMC_BLK		0x0104
#define OMAP_HSMMC_ARG		0x0108
#define OMAP_HSMMC_CMD		0x010C
#define OMAP_HSMMC_RSP10	0x0110
#define OMAP_HSMMC_RSP32	0x0114
#define OMAP_HSMMC_RSP54	0x0118
#define OMAP_HSMMC_RSP76	0x011C
#define OMAP_HSMMC_DATA		0x0120
#define OMAP_HSMMC_HCTL		0x0128
#define OMAP_HSMMC_SYSCTL	0x012C
#define OMAP_HSMMC_STAT		0x0130
#define OMAP_HSMMC_IE		0x0134
#define OMAP_HSMMC_ISE		0x0138
#define OMAP_HSMMC_CAPA		0x0140

#define VS18			(1 << 26)
#define VS30			(1 << 25)
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#define HSS			(1 << 21)
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#define SDVS18			(0x5 << 9)
#define SDVS30			(0x6 << 9)
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#define SDVS33			(0x7 << 9)
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#define SDVS_MASK		0x00000E00
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#define SDVSCLR			0xFFFFF1FF
#define SDVSDET			0x00000400
#define AUTOIDLE		0x1
#define SDBP			(1 << 8)
#define DTO			0xe
#define ICE			0x1
#define ICS			0x2
#define CEN			(1 << 2)
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#define CLKD_MAX		0x3FF		/* max clock divisor: 1023 */
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#define CLKD_MASK		0x0000FFC0
#define CLKD_SHIFT		6
#define DTO_MASK		0x000F0000
#define DTO_SHIFT		16
#define INIT_STREAM		(1 << 1)
#define DP_SELECT		(1 << 21)
#define DDIR			(1 << 4)
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#define DMAE			0x1
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#define MSBS			(1 << 5)
#define BCE			(1 << 1)
#define FOUR_BIT		(1 << 1)
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#define HSPE			(1 << 2)
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#define DDR			(1 << 19)
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#define DW8			(1 << 5)
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#define OD			0x1
#define STAT_CLEAR		0xFFFFFFFF
#define INIT_STREAM_CMD		0x00000000
#define DUAL_VOLT_OCR_BIT	7
#define SRC			(1 << 25)
#define SRD			(1 << 26)
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#define SOFTRESET		(1 << 1)
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/* Interrupt masks for IE and ISE register */
#define CC_EN			(1 << 0)
#define TC_EN			(1 << 1)
#define BWR_EN			(1 << 4)
#define BRR_EN			(1 << 5)
#define ERR_EN			(1 << 15)
#define CTO_EN			(1 << 16)
#define CCRC_EN			(1 << 17)
#define CEB_EN			(1 << 18)
#define CIE_EN			(1 << 19)
#define DTO_EN			(1 << 20)
#define DCRC_EN			(1 << 21)
#define DEB_EN			(1 << 22)
#define CERR_EN			(1 << 28)
#define BADA_EN			(1 << 29)

#define INT_EN_MASK		(BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\
		DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
		BRR_EN | BWR_EN | TC_EN | CC_EN)

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#define MMC_AUTOSUSPEND_DELAY	100
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#define MMC_TIMEOUT_MS		20		/* 20 mSec */
#define MMC_TIMEOUT_US		20000		/* 20000 micro Sec */
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#define OMAP_MMC_MIN_CLOCK	400000
#define OMAP_MMC_MAX_CLOCK	52000000
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#define DRIVER_NAME		"omap_hsmmc"
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#define VDD_1V8			1800000		/* 180000 uV */
#define VDD_3V0			3000000		/* 300000 uV */
#define VDD_165_195		(ffs(MMC_VDD_165_195) - 1)

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/*
 * One controller can have multiple slots, like on some omap boards using
 * omap.c controller driver. Luckily this is not currently done on any known
 * omap_hsmmc.c device.
 */
#define mmc_slot(host)		(host->pdata->slots[host->slot_id])

/*
 * MMC Host controller read/write API's
 */
#define OMAP_HSMMC_READ(base, reg)	\
	__raw_readl((base) + OMAP_HSMMC_##reg)

#define OMAP_HSMMC_WRITE(base, reg, val) \
	__raw_writel((val), (base) + OMAP_HSMMC_##reg)

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struct omap_hsmmc_next {
	unsigned int	dma_len;
	s32		cookie;
};

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struct omap_hsmmc_host {
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	struct	device		*dev;
	struct	mmc_host	*mmc;
	struct	mmc_request	*mrq;
	struct	mmc_command	*cmd;
	struct	mmc_data	*data;
	struct	clk		*fclk;
	struct	clk		*dbclk;
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	/*
	 * vcc == configured supply
	 * vcc_aux == optional
	 *   -	MMC1, supply for DAT4..DAT7
	 *   -	MMC2/MMC2, external level shifter voltage supply, for
	 *	chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
	 */
	struct	regulator	*vcc;
	struct	regulator	*vcc_aux;
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	struct	regulator	*pbias;
	bool			pbias_enabled;
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	void	__iomem		*base;
	resource_size_t		mapbase;
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	spinlock_t		irq_lock; /* Prevent races with irq handler */
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	unsigned int		dma_len;
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	unsigned int		dma_sg_idx;
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	unsigned char		bus_mode;
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	unsigned char		power_mode;
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	int			suspended;
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	u32			con;
	u32			hctl;
	u32			sysctl;
	u32			capa;
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	int			irq;
	int			use_dma, dma_ch;
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	struct dma_chan		*tx_chan;
	struct dma_chan		*rx_chan;
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	int			slot_id;
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	int			response_busy;
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	int			context_loss;
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	int			protect_card;
	int			reqs_blocked;
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	int			use_reg;
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	int			req_in_progress;
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	unsigned long		clk_rate;
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	struct omap_hsmmc_next	next_data;
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	struct	omap_mmc_platform_data	*pdata;
};

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struct omap_mmc_of_data {
	u32 reg_offset;
	u8 controller_flags;
};

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static int omap_hsmmc_card_detect(struct device *dev, int slot)
{
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	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
	struct omap_mmc_platform_data *mmc = host->pdata;
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	/* NOTE: assumes card detect signal is active-low */
	return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
}

static int omap_hsmmc_get_wp(struct device *dev, int slot)
{
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	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
	struct omap_mmc_platform_data *mmc = host->pdata;
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	/* NOTE: assumes write protect signal is active-high */
	return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
}

static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
{
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	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
	struct omap_mmc_platform_data *mmc = host->pdata;
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	/* NOTE: assumes card detect signal is active-low */
	return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
}

#ifdef CONFIG_PM

static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
{
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	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
	struct omap_mmc_platform_data *mmc = host->pdata;
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	disable_irq(mmc->slots[0].card_detect_irq);
	return 0;
}

static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
{
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	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
	struct omap_mmc_platform_data *mmc = host->pdata;
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	enable_irq(mmc->slots[0].card_detect_irq);
	return 0;
}

#else

#define omap_hsmmc_suspend_cdirq	NULL
#define omap_hsmmc_resume_cdirq		NULL

#endif

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#ifdef CONFIG_REGULATOR

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static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
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				   int vdd)
{
	struct omap_hsmmc_host *host =
		platform_get_drvdata(to_platform_device(dev));
	int ret = 0;

	/*
	 * If we don't see a Vcc regulator, assume it's a fixed
	 * voltage always-on regulator.
	 */
	if (!host->vcc)
		return 0;

	if (mmc_slot(host).before_set_reg)
		mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);

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	if (host->pbias) {
		if (host->pbias_enabled == 1) {
			ret = regulator_disable(host->pbias);
			if (!ret)
				host->pbias_enabled = 0;
		}
		regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
	}

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	/*
	 * Assume Vcc regulator is used only to power the card ... OMAP
	 * VDDS is used to power the pins, optionally with a transceiver to
	 * support cards using voltages other than VDDS (1.8V nominal).  When a
	 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
	 *
	 * In some cases this regulator won't support enable/disable;
	 * e.g. it's a fixed rail for a WLAN chip.
	 *
	 * In other cases vcc_aux switches interface power.  Example, for
	 * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
	 * chips/cards need an interface voltage rail too.
	 */
	if (power_on) {
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		if (host->vcc)
			ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
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		/* Enable interface voltage rail, if needed */
		if (ret == 0 && host->vcc_aux) {
			ret = regulator_enable(host->vcc_aux);
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			if (ret < 0 && host->vcc)
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				ret = mmc_regulator_set_ocr(host->mmc,
							host->vcc, 0);
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		}
	} else {
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		/* Shut down the rail */
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		if (host->vcc_aux)
			ret = regulator_disable(host->vcc_aux);
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		if (host->vcc) {
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			/* Then proceed to shut down the local regulator */
			ret = mmc_regulator_set_ocr(host->mmc,
						host->vcc, 0);
		}
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	}

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	if (host->pbias) {
		if (vdd <= VDD_165_195)
			ret = regulator_set_voltage(host->pbias, VDD_1V8,
								VDD_1V8);
		else
			ret = regulator_set_voltage(host->pbias, VDD_3V0,
								VDD_3V0);
		if (ret < 0)
			goto error_set_power;

		if (host->pbias_enabled == 0) {
			ret = regulator_enable(host->pbias);
			if (!ret)
				host->pbias_enabled = 1;
		}
	}

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	if (mmc_slot(host).after_set_reg)
		mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);

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error_set_power:
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	return ret;
}

static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
{
	struct regulator *reg;
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	int ocr_value = 0;
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	reg = devm_regulator_get(host->dev, "vmmc");
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	if (IS_ERR(reg)) {
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		dev_err(host->dev, "unable to get vmmc regulator %ld\n",
			PTR_ERR(reg));
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		return PTR_ERR(reg);
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	} else {
		host->vcc = reg;
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		ocr_value = mmc_regulator_get_ocrmask(reg);
		if (!mmc_slot(host).ocr_mask) {
			mmc_slot(host).ocr_mask = ocr_value;
		} else {
			if (!(mmc_slot(host).ocr_mask & ocr_value)) {
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				dev_err(host->dev, "ocrmask %x is not supported\n",
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					mmc_slot(host).ocr_mask);
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				mmc_slot(host).ocr_mask = 0;
				return -EINVAL;
			}
		}
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	}
	mmc_slot(host).set_power = omap_hsmmc_set_power;
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	/* Allow an aux regulator */
	reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
	host->vcc_aux = IS_ERR(reg) ? NULL : reg;

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	reg = devm_regulator_get_optional(host->dev, "pbias");
	host->pbias = IS_ERR(reg) ? NULL : reg;

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	/* For eMMC do not power off when not in sleep state */
	if (mmc_slot(host).no_regulator_off_init)
		return 0;
	/*
	 * To disable boot_on regulator, enable regulator
	 * to increase usecount and then disable it.
	 */
	if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
	    (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
		int vdd = ffs(mmc_slot(host).ocr_mask) - 1;

		mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
		mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
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	}

	return 0;
}

static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
{
	mmc_slot(host).set_power = NULL;
}

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static inline int omap_hsmmc_have_reg(void)
{
	return 1;
}

#else

static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
{
	return -EINVAL;
}

static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
{
}

static inline int omap_hsmmc_have_reg(void)
{
	return 0;
}

#endif

static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
{
	int ret;

	if (gpio_is_valid(pdata->slots[0].switch_pin)) {
		if (pdata->slots[0].cover)
			pdata->slots[0].get_cover_state =
					omap_hsmmc_get_cover_state;
		else
			pdata->slots[0].card_detect = omap_hsmmc_card_detect;
		pdata->slots[0].card_detect_irq =
				gpio_to_irq(pdata->slots[0].switch_pin);
		ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
		if (ret)
			return ret;
		ret = gpio_direction_input(pdata->slots[0].switch_pin);
		if (ret)
			goto err_free_sp;
	} else
		pdata->slots[0].switch_pin = -EINVAL;

	if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
		pdata->slots[0].get_ro = omap_hsmmc_get_wp;
		ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
		if (ret)
			goto err_free_cd;
		ret = gpio_direction_input(pdata->slots[0].gpio_wp);
		if (ret)
			goto err_free_wp;
	} else
		pdata->slots[0].gpio_wp = -EINVAL;

	return 0;

err_free_wp:
	gpio_free(pdata->slots[0].gpio_wp);
err_free_cd:
	if (gpio_is_valid(pdata->slots[0].switch_pin))
err_free_sp:
		gpio_free(pdata->slots[0].switch_pin);
	return ret;
}

static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
{
	if (gpio_is_valid(pdata->slots[0].gpio_wp))
		gpio_free(pdata->slots[0].gpio_wp);
	if (gpio_is_valid(pdata->slots[0].switch_pin))
		gpio_free(pdata->slots[0].switch_pin);
}

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/*
 * Start clock to the card
 */
static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
{
	OMAP_HSMMC_WRITE(host->base, SYSCTL,
		OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
}

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/*
 * Stop clock to the card
 */
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static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
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{
	OMAP_HSMMC_WRITE(host->base, SYSCTL,
		OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
	if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
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		dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
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}

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static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
				  struct mmc_command *cmd)
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{
	unsigned int irq_mask;

	if (host->use_dma)
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		irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN);
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	else
		irq_mask = INT_EN_MASK;

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	/* Disable timeout for erases */
	if (cmd->opcode == MMC_ERASE)
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		irq_mask &= ~DTO_EN;
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	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
	OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
	OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
}

static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
{
	OMAP_HSMMC_WRITE(host->base, ISE, 0);
	OMAP_HSMMC_WRITE(host->base, IE, 0);
	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
}

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/* Calculate divisor for the given clock frequency */
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static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
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{
	u16 dsor = 0;

	if (ios->clock) {
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		dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
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		if (dsor > CLKD_MAX)
			dsor = CLKD_MAX;
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	}

	return dsor;
}

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static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
{
	struct mmc_ios *ios = &host->mmc->ios;
	unsigned long regval;
	unsigned long timeout;
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	unsigned long clkdiv;
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	dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
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	omap_hsmmc_stop_clock(host);

	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
	regval = regval & ~(CLKD_MASK | DTO_MASK);
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	clkdiv = calc_divisor(host, ios);
	regval = regval | (clkdiv << 6) | (DTO << 16);
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	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
	OMAP_HSMMC_WRITE(host->base, SYSCTL,
		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);

	/* Wait till the ICS bit is set */
	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
		&& time_before(jiffies, timeout))
		cpu_relax();

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	/*
	 * Enable High-Speed Support
	 * Pre-Requisites
	 *	- Controller should support High-Speed-Enable Bit
	 *	- Controller should not be using DDR Mode
	 *	- Controller should advertise that it supports High Speed
	 *	  in capabilities register
	 *	- MMC/SD clock coming out of controller > 25MHz
	 */
	if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
	    (ios->timing != MMC_TIMING_UHS_DDR50) &&
	    ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
		regval = OMAP_HSMMC_READ(host->base, HCTL);
		if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
			regval |= HSPE;
		else
			regval &= ~HSPE;

		OMAP_HSMMC_WRITE(host->base, HCTL, regval);
	}

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	omap_hsmmc_start_clock(host);
}

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static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
{
	struct mmc_ios *ios = &host->mmc->ios;
	u32 con;

	con = OMAP_HSMMC_READ(host->base, CON);
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	if (ios->timing == MMC_TIMING_UHS_DDR50)
		con |= DDR;	/* configure in DDR mode */
	else
		con &= ~DDR;
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	switch (ios->bus_width) {
	case MMC_BUS_WIDTH_8:
		OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
		break;
	case MMC_BUS_WIDTH_4:
		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
		OMAP_HSMMC_WRITE(host->base, HCTL,
			OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
		break;
	case MMC_BUS_WIDTH_1:
		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
		OMAP_HSMMC_WRITE(host->base, HCTL,
			OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
		break;
	}
}

static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
{
	struct mmc_ios *ios = &host->mmc->ios;
	u32 con;

	con = OMAP_HSMMC_READ(host->base, CON);
	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
		OMAP_HSMMC_WRITE(host->base, CON, con | OD);
	else
		OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
}

623 624 625 626 627 628
#ifdef CONFIG_PM

/*
 * Restore the MMC host context, if it was lost as result of a
 * power state change.
 */
629
static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
630 631
{
	struct mmc_ios *ios = &host->mmc->ios;
632
	u32 hctl, capa;
633 634
	unsigned long timeout;

635 636 637 638 639 640 641 642
	if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
	    host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
	    host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
	    host->capa == OMAP_HSMMC_READ(host->base, CAPA))
		return 0;

	host->context_loss++;

643
	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668
		if (host->power_mode != MMC_POWER_OFF &&
		    (1 << ios->vdd) <= MMC_VDD_23_24)
			hctl = SDVS18;
		else
			hctl = SDVS30;
		capa = VS30 | VS18;
	} else {
		hctl = SDVS18;
		capa = VS18;
	}

	OMAP_HSMMC_WRITE(host->base, HCTL,
			OMAP_HSMMC_READ(host->base, HCTL) | hctl);

	OMAP_HSMMC_WRITE(host->base, CAPA,
			OMAP_HSMMC_READ(host->base, CAPA) | capa);

	OMAP_HSMMC_WRITE(host->base, HCTL,
			OMAP_HSMMC_READ(host->base, HCTL) | SDBP);

	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
	while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
		&& time_before(jiffies, timeout))
		;

669
	omap_hsmmc_disable_irq(host);
670 671 672 673 674

	/* Do not initialize card-specific things if the power is off */
	if (host->power_mode == MMC_POWER_OFF)
		goto out;

675
	omap_hsmmc_set_bus_width(host);
676

677
	omap_hsmmc_set_clock(host);
678

679 680
	omap_hsmmc_set_bus_mode(host);

681
out:
682 683
	dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
		host->context_loss);
684 685 686 687 688 689
	return 0;
}

/*
 * Save the MMC host context (store the number of power state changes so far).
 */
690
static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
691
{
692 693 694 695
	host->con =  OMAP_HSMMC_READ(host->base, CON);
	host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
	host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
	host->capa = OMAP_HSMMC_READ(host->base, CAPA);
696 697 698 699
}

#else

700
static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
701 702 703 704
{
	return 0;
}

705
static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
706 707 708 709 710
{
}

#endif

711 712 713 714
/*
 * Send init stream sequence to card
 * before sending IDLE command
 */
715
static void send_init_stream(struct omap_hsmmc_host *host)
716 717 718 719
{
	int reg = 0;
	unsigned long timeout;

720 721 722
	if (host->protect_card)
		return;

723
	disable_irq(host->irq);
724 725

	OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
726 727 728 729 730
	OMAP_HSMMC_WRITE(host->base, CON,
		OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
	OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);

	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
731 732
	while ((reg != CC_EN) && time_before(jiffies, timeout))
		reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
733 734 735

	OMAP_HSMMC_WRITE(host->base, CON,
		OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
736 737 738 739

	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
	OMAP_HSMMC_READ(host->base, STAT);

740 741 742 743
	enable_irq(host->irq);
}

static inline
744
int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
745 746 747
{
	int r = 1;

748 749
	if (mmc_slot(host).get_cover_state)
		r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
750 751 752 753
	return r;
}

static ssize_t
754
omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
755 756 757
			   char *buf)
{
	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
758
	struct omap_hsmmc_host *host = mmc_priv(mmc);
759

760 761
	return sprintf(buf, "%s\n",
			omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
762 763
}

764
static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
765 766

static ssize_t
767
omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
768 769 770
			char *buf)
{
	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
771
	struct omap_hsmmc_host *host = mmc_priv(mmc);
772

773
	return sprintf(buf, "%s\n", mmc_slot(host).name);
774 775
}

776
static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
777 778 779 780 781

/*
 * Configure the response type and send the cmd.
 */
static void
782
omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
783 784 785 786
	struct mmc_data *data)
{
	int cmdreg = 0, resptype = 0, cmdtype = 0;

787
	dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
788 789 790
		mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
	host->cmd = cmd;

791
	omap_hsmmc_enable_irq(host, cmd);
792

793
	host->response_busy = 0;
794 795 796
	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136)
			resptype = 1;
797 798 799 800
		else if (cmd->flags & MMC_RSP_BUSY) {
			resptype = 3;
			host->response_busy = 1;
		} else
801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822
			resptype = 2;
	}

	/*
	 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
	 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
	 * a val of 0x3, rest 0x0.
	 */
	if (cmd == host->mrq->stop)
		cmdtype = 0x3;

	cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);

	if (data) {
		cmdreg |= DP_SELECT | MSBS | BCE;
		if (data->flags & MMC_DATA_READ)
			cmdreg |= DDIR;
		else
			cmdreg &= ~(DDIR);
	}

	if (host->use_dma)
823
		cmdreg |= DMAE;
824

825
	host->req_in_progress = 1;
826

827 828 829 830
	OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
	OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
}

831
static int
832
omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
833 834 835 836 837 838 839
{
	if (data->flags & MMC_DATA_WRITE)
		return DMA_TO_DEVICE;
	else
		return DMA_FROM_DEVICE;
}

840 841 842 843 844 845
static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
	struct mmc_data *data)
{
	return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
}

846 847 848
static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
{
	int dma_ch;
849
	unsigned long flags;
850

851
	spin_lock_irqsave(&host->irq_lock, flags);
852 853
	host->req_in_progress = 0;
	dma_ch = host->dma_ch;
854
	spin_unlock_irqrestore(&host->irq_lock, flags);
855 856 857 858 859 860 861 862 863

	omap_hsmmc_disable_irq(host);
	/* Do not complete the request if DMA is still in progress */
	if (mrq->data && host->use_dma && dma_ch != -1)
		return;
	host->mrq = NULL;
	mmc_request_done(host->mmc, mrq);
}

864 865 866 867
/*
 * Notify the transfer complete to MMC core
 */
static void
868
omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
869
{
870 871 872
	if (!data) {
		struct mmc_request *mrq = host->mrq;

873 874 875 876 877 878 879
		/* TC before CC from CMD6 - don't know why, but it happens */
		if (host->cmd && host->cmd->opcode == 6 &&
		    host->response_busy) {
			host->response_busy = 0;
			return;
		}

880
		omap_hsmmc_request_done(host, mrq);
881 882 883
		return;
	}

884 885 886 887 888 889 890
	host->data = NULL;

	if (!data->error)
		data->bytes_xfered += data->blocks * (data->blksz);
	else
		data->bytes_xfered = 0;

891
	if (!data->stop) {
892
		omap_hsmmc_request_done(host, data->mrq);
893
		return;
894
	}
895
	omap_hsmmc_start_command(host, data->stop, NULL);
896 897 898 899 900 901
}

/*
 * Notify the core about command completion
 */
static void
902
omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
903 904 905 906 907 908 909 910 911 912 913 914 915 916 917
{
	host->cmd = NULL;

	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136) {
			/* response type 2 */
			cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
			cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
			cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
		} else {
			/* response types 1, 1b, 3, 4, 5, 6 */
			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
		}
	}
918 919
	if ((host->data == NULL && !host->response_busy) || cmd->error)
		omap_hsmmc_request_done(host, cmd->mrq);
920 921 922 923 924
}

/*
 * DMA clean up for command errors
 */
925
static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
926
{
927
	int dma_ch;
928
	unsigned long flags;
929

930
	host->data->error = errno;
931

932
	spin_lock_irqsave(&host->irq_lock, flags);
933 934
	dma_ch = host->dma_ch;
	host->dma_ch = -1;
935
	spin_unlock_irqrestore(&host->irq_lock, flags);
936 937

	if (host->use_dma && dma_ch != -1) {
938 939 940 941 942
		struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);

		dmaengine_terminate_all(chan);
		dma_unmap_sg(chan->device->dev,
			host->data->sg, host->data->sg_len,
943
			omap_hsmmc_get_dma_dir(host, host->data));
944

945
		host->data->host_cookie = 0;
946 947 948 949 950 951 952 953
	}
	host->data = NULL;
}

/*
 * Readable error output
 */
#ifdef CONFIG_MMC_DEBUG
954
static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
955 956
{
	/* --- means reserved bit without definition at documentation */
957
	static const char *omap_hsmmc_status_bits[] = {
958 959 960 961
		"CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
		"CIRQ",	"OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
		"CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
		"ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
962 963 964 965 966 967 968 969
	};
	char res[256];
	char *buf = res;
	int len, i;

	len = sprintf(buf, "MMC IRQ 0x%x :", status);
	buf += len;

970
	for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
971
		if (status & (1 << i)) {
972
			len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
973 974 975
			buf += len;
		}

976
	dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
977
}
978 979 980 981 982
#else
static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
					     u32 status)
{
}
983 984
#endif  /* CONFIG_MMC_DEBUG */

985 986 987 988 989 990 991
/*
 * MMC controller internal state machines reset
 *
 * Used to reset command or data internal state machines, using respectively
 *  SRC or SRD bit of SYSCTL register
 * Can be called from interrupt context
 */
992 993
static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
						   unsigned long bit)
994 995
{
	unsigned long i = 0;
996
	unsigned long limit = MMC_TIMEOUT_US;
997 998 999 1000

	OMAP_HSMMC_WRITE(host->base, SYSCTL,
			 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);

1001 1002 1003 1004 1005
	/*
	 * OMAP4 ES2 and greater has an updated reset logic.
	 * Monitor a 0->1 transition first
	 */
	if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1006
		while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1007
					&& (i++ < limit))
1008
			udelay(1);
1009 1010 1011
	}
	i = 0;

1012 1013
	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
		(i++ < limit))
1014
		udelay(1);
1015 1016 1017 1018 1019 1020

	if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
		dev_err(mmc_dev(host->mmc),
			"Timeout waiting on controller reset in %s\n",
			__func__);
}
1021

1022 1023
static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
					int err, int end_cmd)
1024
{
1025
	if (end_cmd) {
1026
		omap_hsmmc_reset_controller_fsm(host, SRC);
1027 1028 1029
		if (host->cmd)
			host->cmd->error = err;
	}
1030 1031 1032 1033

	if (host->data) {
		omap_hsmmc_reset_controller_fsm(host, SRD);
		omap_hsmmc_dma_cleanup(host, err);
1034 1035
	} else if (host->mrq && host->mrq->cmd)
		host->mrq->cmd->error = err;
1036 1037
}

1038
static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1039 1040
{
	struct mmc_data *data;
1041 1042
	int end_cmd = 0, end_trans = 0;

1043
	data = host->data;
1044
	dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1045

1046
	if (status & ERR_EN) {
1047
		omap_hsmmc_dbg_report_irq(host, status);
1048

1049
		if (status & (CTO_EN | CCRC_EN))
1050
			end_cmd = 1;
1051
		if (status & (CTO_EN | DTO_EN))
1052
			hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1053
		else if (status & (CCRC_EN | DCRC_EN))
1054
			hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1055 1056

		if (host->data || host->response_busy) {
1057
			end_trans = !end_cmd;
1058
			host->response_busy = 0;
1059 1060 1061
		}
	}

1062
	OMAP_HSMMC_WRITE(host->base, STAT, status);
1063
	if (end_cmd || ((status & CC_EN) && host->cmd))
1064
		omap_hsmmc_cmd_done(host, host->cmd);
1065
	if ((end_trans || (status & TC_EN)) && host->mrq)
1066
		omap_hsmmc_xfer_done(host, data);
1067
}
1068

1069 1070 1071 1072 1073 1074 1075 1076 1077
/*
 * MMC controller IRQ handler
 */
static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
{
	struct omap_hsmmc_host *host = dev_id;
	int status;

	status = OMAP_HSMMC_READ(host->base, STAT);
1078
	while (status & INT_EN_MASK && host->req_in_progress) {
1079
		omap_hsmmc_do_irq(host, status);
1080

1081 1082
		/* Flush posted write */
		status = OMAP_HSMMC_READ(host->base, STAT);
1083
	}
1084

1085 1086 1087
	return IRQ_HANDLED;
}

1088
static void set_sd_bus_power(struct omap_hsmmc_host *host)
A
Adrian Hunter 已提交
1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100
{
	unsigned long i;

	OMAP_HSMMC_WRITE(host->base, HCTL,
			 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
	for (i = 0; i < loops_per_jiffy; i++) {
		if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
			break;
		cpu_relax();
	}
}

1101
/*
1102 1103 1104 1105 1106
 * Switch MMC interface voltage ... only relevant for MMC1.
 *
 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 * Some chips, like eMMC ones, use internal transceivers.
1107
 */
1108
static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1109 1110 1111 1112 1113
{
	u32 reg_val = 0;
	int ret;

	/* Disable the clocks */
1114
	pm_runtime_put_sync(host->dev);
1115
	if (host->dbclk)
1116
		clk_disable_unprepare(host->dbclk);
1117 1118 1119 1120 1121

	/* Turn the power off */
	ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);

	/* Turn the power ON with given VDD 1.8 or 3.0v */
1122 1123 1124
	if (!ret)
		ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
					       vdd);
1125
	pm_runtime_get_sync(host->dev);
1126
	if (host->dbclk)
1127
		clk_prepare_enable(host->dbclk);
1128

1129 1130 1131 1132 1133 1134
	if (ret != 0)
		goto err;

	OMAP_HSMMC_WRITE(host->base, HCTL,
		OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
	reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1135

1136 1137 1138
	/*
	 * If a MMC dual voltage card is detected, the set_ios fn calls
	 * this fn with VDD bit set for 1.8V. Upon card removal from the
1139
	 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1140
	 *
1141 1142 1143 1144 1145 1146 1147 1148 1149
	 * Cope with a bit of slop in the range ... per data sheets:
	 *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
	 *    but recommended values are 1.71V to 1.89V
	 *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
	 *    but recommended values are 2.7V to 3.3V
	 *
	 * Board setup code shouldn't permit anything very out-of-range.
	 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
	 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1150
	 */
1151
	if ((1 << vdd) <= MMC_VDD_23_24)
1152
		reg_val |= SDVS18;
1153 1154
	else
		reg_val |= SDVS30;
1155 1156

	OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
A
Adrian Hunter 已提交
1157
	set_sd_bus_power(host);
1158 1159 1160

	return 0;
err:
1161
	dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1162 1163 1164
	return ret;
}

1165 1166 1167 1168 1169 1170 1171 1172 1173
/* Protect the card while the cover is open */
static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
{
	if (!mmc_slot(host).get_cover_state)
		return;

	host->reqs_blocked = 0;
	if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
		if (host->protect_card) {
1174
			dev_info(host->dev, "%s: cover is closed, "
1175 1176 1177 1178 1179 1180
					 "card is now accessible\n",
					 mmc_hostname(host->mmc));
			host->protect_card = 0;
		}
	} else {
		if (!host->protect_card) {
1181
			dev_info(host->dev, "%s: cover is open, "
1182 1183 1184 1185 1186 1187 1188
					 "card is now inaccessible\n",
					 mmc_hostname(host->mmc));
			host->protect_card = 1;
		}
	}
}

1189
/*
1190
 * irq handler to notify the core about card insertion/removal
1191
 */
1192
static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1193
{
1194
	struct omap_hsmmc_host *host = dev_id;
1195
	struct omap_mmc_slot_data *slot = &mmc_slot(host);
1196 1197 1198
	int carddetect;

	sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1199

1200
	if (slot->card_detect)
1201
		carddetect = slot->card_detect(host->dev, host->slot_id);
1202 1203
	else {
		omap_hsmmc_protect_card(host);
1204
		carddetect = -ENOSYS;
1205
	}
1206

1207
	if (carddetect)
1208
		mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1209
	else
1210 1211 1212 1213
		mmc_detect_change(host->mmc, (HZ * 50) / 1000);
	return IRQ_HANDLED;
}

1214
static void omap_hsmmc_dma_callback(void *param)
1215
{
1216 1217
	struct omap_hsmmc_host *host = param;
	struct dma_chan *chan;
1218
	struct mmc_data *data;
1219
	int req_in_progress;
1220

1221
	spin_lock_irq(&host->irq_lock);
1222
	if (host->dma_ch < 0) {
1223
		spin_unlock_irq(&host->irq_lock);
1224
		return;
1225
	}
1226

1227
	data = host->mrq->data;
1228
	chan = omap_hsmmc_get_dma_chan(host, data);
1229
	if (!data->host_cookie)
1230 1231
		dma_unmap_sg(chan->device->dev,
			     data->sg, data->sg_len,
1232
			     omap_hsmmc_get_dma_dir(host, data));
1233 1234

	req_in_progress = host->req_in_progress;
1235
	host->dma_ch = -1;
1236
	spin_unlock_irq(&host->irq_lock);
1237 1238 1239 1240 1241 1242 1243 1244

	/* If DMA has finished after TC, complete the request */
	if (!req_in_progress) {
		struct mmc_request *mrq = host->mrq;

		host->mrq = NULL;
		mmc_request_done(host->mmc, mrq);
	}
1245 1246
}

1247 1248
static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
				       struct mmc_data *data,
1249
				       struct omap_hsmmc_next *next,
1250
				       struct dma_chan *chan)
1251 1252 1253 1254 1255
{
	int dma_len;

	if (!next && data->host_cookie &&
	    data->host_cookie != host->next_data.cookie) {
1256
		dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1257 1258 1259 1260 1261 1262
		       " host->next_data.cookie %d\n",
		       __func__, data->host_cookie, host->next_data.cookie);
		data->host_cookie = 0;
	}

	/* Check if next job is already prepared */
1263
	if (next || data->host_cookie != host->next_data.cookie) {
1264
		dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
				     omap_hsmmc_get_dma_dir(host, data));

	} else {
		dma_len = host->next_data.dma_len;
		host->next_data.dma_len = 0;
	}


	if (dma_len == 0)
		return -EINVAL;

	if (next) {
		next->dma_len = dma_len;
		data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
	} else
		host->dma_len = dma_len;

	return 0;
}

1285 1286 1287
/*
 * Routine to configure and start DMA for the MMC card
 */
1288 1289
static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
					struct mmc_request *req)
1290
{
1291 1292 1293
	struct dma_slave_config cfg;
	struct dma_async_tx_descriptor *tx;
	int ret = 0, i;
1294
	struct mmc_data *data = req->data;
1295
	struct dma_chan *chan;
1296

1297
	/* Sanity check: all the SG entries must be aligned by block size. */
1298
	for (i = 0; i < data->sg_len; i++) {
1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310
		struct scatterlist *sgl;

		sgl = data->sg + i;
		if (sgl->length % data->blksz)
			return -EINVAL;
	}
	if ((data->blksz % 4) != 0)
		/* REVISIT: The MMC buffer increments only when MSB is written.
		 * Return error for blksz which is non multiple of four.
		 */
		return -EINVAL;

1311
	BUG_ON(host->dma_ch != -1);
1312

1313 1314
	chan = omap_hsmmc_get_dma_chan(host, data);

1315 1316 1317 1318 1319 1320
	cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
	cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	cfg.src_maxburst = data->blksz / 4;
	cfg.dst_maxburst = data->blksz / 4;
1321

1322 1323
	ret = dmaengine_slave_config(chan, &cfg);
	if (ret)
1324
		return ret;
1325

1326
	ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1327 1328
	if (ret)
		return ret;
1329

1330 1331 1332 1333 1334 1335 1336 1337
	tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
		data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
		DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!tx) {
		dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
		/* FIXME: cleanup */
		return -1;
	}
1338

1339 1340
	tx->callback = omap_hsmmc_dma_callback;
	tx->callback_param = host;
1341

1342 1343
	/* Does not fail */
	dmaengine_submit(tx);
1344

1345
	host->dma_ch = 1;
1346

1347
	dma_async_issue_pending(chan);
1348 1349 1350 1351

	return 0;
}

1352
static void set_data_timeout(struct omap_hsmmc_host *host,
1353 1354
			     unsigned int timeout_ns,
			     unsigned int timeout_clks)
1355 1356 1357 1358 1359 1360 1361 1362 1363
{
	unsigned int timeout, cycle_ns;
	uint32_t reg, clkd, dto = 0;

	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
	clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
	if (clkd == 0)
		clkd = 1;

1364
	cycle_ns = 1000000000 / (host->clk_rate / clkd);
1365 1366
	timeout = timeout_ns / cycle_ns;
	timeout += timeout_clks;
1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392
	if (timeout) {
		while ((timeout & 0x80000000) == 0) {
			dto += 1;
			timeout <<= 1;
		}
		dto = 31 - dto;
		timeout <<= 1;
		if (timeout && dto)
			dto += 1;
		if (dto >= 13)
			dto -= 13;
		else
			dto = 0;
		if (dto > 14)
			dto = 14;
	}

	reg &= ~DTO_MASK;
	reg |= dto << DTO_SHIFT;
	OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
}

/*
 * Configure block length for MMC/SD cards and initiate the transfer.
 */
static int
1393
omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1394 1395 1396 1397 1398 1399
{
	int ret;
	host->data = req->data;

	if (req->data == NULL) {
		OMAP_HSMMC_WRITE(host->base, BLK, 0);
1400 1401 1402 1403 1404 1405
		/*
		 * Set an arbitrary 100ms data timeout for commands with
		 * busy signal.
		 */
		if (req->cmd->flags & MMC_RSP_BUSY)
			set_data_timeout(host, 100000000U, 0);
1406 1407 1408 1409 1410
		return 0;
	}

	OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
					| (req->data->blocks << 16));
1411
	set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1412 1413

	if (host->use_dma) {
1414
		ret = omap_hsmmc_start_dma_transfer(host, req);
1415
		if (ret != 0) {
1416
			dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1417 1418 1419 1420 1421 1422
			return ret;
		}
	}
	return 0;
}

1423 1424 1425 1426 1427 1428
static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
				int err)
{
	struct omap_hsmmc_host *host = mmc_priv(mmc);
	struct mmc_data *data = mrq->data;

1429
	if (host->use_dma && data->host_cookie) {
1430 1431
		struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);

1432 1433
		dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
			     omap_hsmmc_get_dma_dir(host, data));
1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447
		data->host_cookie = 0;
	}
}

static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
			       bool is_first_req)
{
	struct omap_hsmmc_host *host = mmc_priv(mmc);

	if (mrq->data->host_cookie) {
		mrq->data->host_cookie = 0;
		return ;
	}

1448 1449 1450
	if (host->use_dma) {
		struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);

1451
		if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1452
						&host->next_data, c))
1453
			mrq->data->host_cookie = 0;
1454
	}
1455 1456
}

1457 1458 1459
/*
 * Request function. for read/write operation
 */
1460
static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1461
{
1462
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1463
	int err;
1464

1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485
	BUG_ON(host->req_in_progress);
	BUG_ON(host->dma_ch != -1);
	if (host->protect_card) {
		if (host->reqs_blocked < 3) {
			/*
			 * Ensure the controller is left in a consistent
			 * state by resetting the command and data state
			 * machines.
			 */
			omap_hsmmc_reset_controller_fsm(host, SRD);
			omap_hsmmc_reset_controller_fsm(host, SRC);
			host->reqs_blocked += 1;
		}
		req->cmd->error = -EBADF;
		if (req->data)
			req->data->error = -EBADF;
		req->cmd->retries = 0;
		mmc_request_done(mmc, req);
		return;
	} else if (host->reqs_blocked)
		host->reqs_blocked = 0;
1486 1487
	WARN_ON(host->mrq != NULL);
	host->mrq = req;
1488
	host->clk_rate = clk_get_rate(host->fclk);
1489
	err = omap_hsmmc_prepare_data(host, req);
1490 1491 1492 1493 1494 1495 1496 1497 1498
	if (err) {
		req->cmd->error = err;
		if (req->data)
			req->data->error = err;
		host->mrq = NULL;
		mmc_request_done(mmc, req);
		return;
	}

1499
	omap_hsmmc_start_command(host, req->cmd, req->data);
1500 1501 1502
}

/* Routine to configure clock values. Exposed API to core */
1503
static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1504
{
1505
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1506
	int do_send_init_stream = 0;
1507

1508
	pm_runtime_get_sync(host->dev);
1509

1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524
	if (ios->power_mode != host->power_mode) {
		switch (ios->power_mode) {
		case MMC_POWER_OFF:
			mmc_slot(host).set_power(host->dev, host->slot_id,
						 0, 0);
			break;
		case MMC_POWER_UP:
			mmc_slot(host).set_power(host->dev, host->slot_id,
						 1, ios->vdd);
			break;
		case MMC_POWER_ON:
			do_send_init_stream = 1;
			break;
		}
		host->power_mode = ios->power_mode;
1525 1526
	}

1527 1528
	/* FIXME: set registers based only on changes to ios */

1529
	omap_hsmmc_set_bus_width(host);
1530

1531
	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1532 1533 1534
		/* Only MMC1 can interface at 3V without some flavor
		 * of external transceiver; but they all handle 1.8V.
		 */
1535
		if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1536
			(ios->vdd == DUAL_VOLT_OCR_BIT)) {
1537 1538 1539 1540 1541 1542
				/*
				 * The mmc_select_voltage fn of the core does
				 * not seem to set the power_mode to
				 * MMC_POWER_UP upon recalculating the voltage.
				 * vdd 1.8v.
				 */
1543 1544
			if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
				dev_dbg(mmc_dev(host->mmc),
1545 1546 1547 1548
						"Switch operation failed\n");
		}
	}

1549
	omap_hsmmc_set_clock(host);
1550

1551
	if (do_send_init_stream)
1552 1553
		send_init_stream(host);

1554
	omap_hsmmc_set_bus_mode(host);
1555

1556
	pm_runtime_put_autosuspend(host->dev);
1557 1558 1559 1560
}

static int omap_hsmmc_get_cd(struct mmc_host *mmc)
{
1561
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1562

1563
	if (!mmc_slot(host).card_detect)
1564
		return -ENOSYS;
1565
	return mmc_slot(host).card_detect(host->dev, host->slot_id);
1566 1567 1568 1569
}

static int omap_hsmmc_get_ro(struct mmc_host *mmc)
{
1570
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1571

1572
	if (!mmc_slot(host).get_ro)
1573
		return -ENOSYS;
1574
	return mmc_slot(host).get_ro(host->dev, 0);
1575 1576
}

1577 1578 1579 1580 1581 1582 1583 1584
static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
{
	struct omap_hsmmc_host *host = mmc_priv(mmc);

	if (mmc_slot(host).init_card)
		mmc_slot(host).init_card(card);
}

1585
static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1586 1587 1588 1589
{
	u32 hctl, capa, value;

	/* Only MMC1 supports 3.0V */
1590
	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604
		hctl = SDVS30;
		capa = VS30 | VS18;
	} else {
		hctl = SDVS18;
		capa = VS18;
	}

	value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
	OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);

	value = OMAP_HSMMC_READ(host->base, CAPA);
	OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);

	/* Set SD bus power bit */
A
Adrian Hunter 已提交
1605
	set_sd_bus_power(host);
1606 1607
}

1608
static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1609
{
1610
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1611

1612 1613
	pm_runtime_get_sync(host->dev);

1614 1615 1616
	return 0;
}

1617
static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1618
{
1619
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1620

1621 1622 1623
	pm_runtime_mark_last_busy(host->dev);
	pm_runtime_put_autosuspend(host->dev);

1624 1625 1626
	return 0;
}

1627 1628 1629
static const struct mmc_host_ops omap_hsmmc_ops = {
	.enable = omap_hsmmc_enable_fclk,
	.disable = omap_hsmmc_disable_fclk,
1630 1631
	.post_req = omap_hsmmc_post_req,
	.pre_req = omap_hsmmc_pre_req,
1632 1633
	.request = omap_hsmmc_request,
	.set_ios = omap_hsmmc_set_ios,
1634 1635
	.get_cd = omap_hsmmc_get_cd,
	.get_ro = omap_hsmmc_get_ro,
1636
	.init_card = omap_hsmmc_init_card,
1637 1638 1639
	/* NYET -- enable_sdio_irq */
};

1640 1641
#ifdef CONFIG_DEBUG_FS

1642
static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1643 1644
{
	struct mmc_host *mmc = s->private;
1645
	struct omap_hsmmc_host *host = mmc_priv(mmc);
1646

1647 1648
	seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n",
			mmc->index, host->context_loss);
1649

1650
	pm_runtime_get_sync(host->dev);
1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663

	seq_printf(s, "CON:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, CON));
	seq_printf(s, "HCTL:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, HCTL));
	seq_printf(s, "SYSCTL:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, SYSCTL));
	seq_printf(s, "IE:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, IE));
	seq_printf(s, "ISE:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, ISE));
	seq_printf(s, "CAPA:\t\t0x%08x\n",
			OMAP_HSMMC_READ(host->base, CAPA));
1664

1665 1666
	pm_runtime_mark_last_busy(host->dev);
	pm_runtime_put_autosuspend(host->dev);
1667

1668 1669 1670
	return 0;
}

1671
static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1672
{
1673
	return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1674 1675 1676
}

static const struct file_operations mmc_regs_fops = {
1677
	.open           = omap_hsmmc_regs_open,
1678 1679 1680 1681 1682
	.read           = seq_read,
	.llseek         = seq_lseek,
	.release        = single_release,
};

1683
static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1684 1685 1686 1687 1688 1689 1690 1691
{
	if (mmc->debugfs_root)
		debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
			mmc, &mmc_regs_fops);
}

#else

1692
static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1693 1694 1695 1696 1697
{
}

#endif

1698
#ifdef CONFIG_OF
1699 1700 1701 1702 1703 1704 1705 1706
static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
	/* See 35xx errata 2.1.1.128 in SPRZ278F */
	.controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
};

static const struct omap_mmc_of_data omap4_mmc_of_data = {
	.reg_offset = 0x100,
};
1707 1708 1709 1710 1711

static const struct of_device_id omap_mmc_of_match[] = {
	{
		.compatible = "ti,omap2-hsmmc",
	},
1712 1713 1714 1715
	{
		.compatible = "ti,omap3-pre-es3-hsmmc",
		.data = &omap3_pre_es3_mmc_of_data,
	},
1716 1717 1718 1719 1720
	{
		.compatible = "ti,omap3-hsmmc",
	},
	{
		.compatible = "ti,omap4-hsmmc",
1721
		.data = &omap4_mmc_of_data,
1722 1723
	},
	{},
1724
};
1725 1726 1727 1728 1729 1730
MODULE_DEVICE_TABLE(of, omap_mmc_of_match);

static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
{
	struct omap_mmc_platform_data *pdata;
	struct device_node *np = dev->of_node;
1731
	u32 bus_width, max_freq;
1732 1733 1734 1735 1736 1737
	int cd_gpio, wp_gpio;

	cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
	wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
	if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
		return ERR_PTR(-EPROBE_DEFER);
1738 1739 1740

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
1741
		return ERR_PTR(-ENOMEM); /* out of memory */
1742 1743 1744 1745 1746 1747

	if (of_find_property(np, "ti,dual-volt", NULL))
		pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;

	/* This driver only supports 1 slot */
	pdata->nr_slots = 1;
1748 1749
	pdata->slots[0].switch_pin = cd_gpio;
	pdata->slots[0].gpio_wp = wp_gpio;
1750 1751 1752 1753 1754

	if (of_find_property(np, "ti,non-removable", NULL)) {
		pdata->slots[0].nonremovable = true;
		pdata->slots[0].no_regulator_off_init = true;
	}
1755
	of_property_read_u32(np, "bus-width", &bus_width);
1756 1757 1758 1759 1760 1761 1762 1763
	if (bus_width == 4)
		pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
	else if (bus_width == 8)
		pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;

	if (of_find_property(np, "ti,needs-special-reset", NULL))
		pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;

1764 1765 1766
	if (!of_property_read_u32(np, "max-frequency", &max_freq))
		pdata->max_freq = max_freq;

1767 1768 1769
	if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
		pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;

1770 1771 1772 1773 1774 1775
	if (of_find_property(np, "keep-power-in-suspend", NULL))
		pdata->slots[0].pm_caps |= MMC_PM_KEEP_POWER;

	if (of_find_property(np, "enable-sdio-wakeup", NULL))
		pdata->slots[0].pm_caps |= MMC_PM_WAKE_SDIO_IRQ;

1776 1777 1778 1779 1780 1781
	return pdata;
}
#else
static inline struct omap_mmc_platform_data
			*of_get_hsmmc_pdata(struct device *dev)
{
1782
	return ERR_PTR(-EINVAL);
1783 1784 1785
}
#endif

1786
static int omap_hsmmc_probe(struct platform_device *pdev)
1787 1788 1789
{
	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
	struct mmc_host *mmc;
1790
	struct omap_hsmmc_host *host = NULL;
1791
	struct resource *res;
1792
	int ret, irq;
1793
	const struct of_device_id *match;
1794 1795
	dma_cap_mask_t mask;
	unsigned tx_req, rx_req;
1796
	struct pinctrl *pinctrl;
1797
	const struct omap_mmc_of_data *data;
1798 1799 1800 1801

	match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
	if (match) {
		pdata = of_get_hsmmc_pdata(&pdev->dev);
1802 1803 1804 1805

		if (IS_ERR(pdata))
			return PTR_ERR(pdata);

1806
		if (match->data) {
1807 1808 1809
			data = match->data;
			pdata->reg_offset = data->reg_offset;
			pdata->controller_flags |= data->controller_flags;
1810 1811
		}
	}
1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827

	if (pdata == NULL) {
		dev_err(&pdev->dev, "Platform Data is missing\n");
		return -ENXIO;
	}

	if (pdata->nr_slots == 0) {
		dev_err(&pdev->dev, "No Slots\n");
		return -ENXIO;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_irq(pdev, 0);
	if (res == NULL || irq < 0)
		return -ENXIO;

1828
	res = request_mem_region(res->start, resource_size(res), pdev->name);
1829 1830 1831
	if (res == NULL)
		return -EBUSY;

1832 1833 1834 1835
	ret = omap_hsmmc_gpio_init(pdata);
	if (ret)
		goto err;

1836
	mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1837 1838
	if (!mmc) {
		ret = -ENOMEM;
1839
		goto err_alloc;
1840 1841 1842 1843 1844 1845 1846 1847 1848 1849
	}

	host		= mmc_priv(mmc);
	host->mmc	= mmc;
	host->pdata	= pdata;
	host->dev	= &pdev->dev;
	host->use_dma	= 1;
	host->dma_ch	= -1;
	host->irq	= irq;
	host->slot_id	= 0;
1850
	host->mapbase	= res->start + pdata->reg_offset;
1851
	host->base	= ioremap(host->mapbase, SZ_4K);
1852
	host->power_mode = MMC_POWER_OFF;
1853
	host->next_data.cookie = 1;
1854
	host->pbias_enabled = 0;
1855 1856 1857

	platform_set_drvdata(pdev, host);

1858
	mmc->ops	= &omap_hsmmc_ops;
1859

1860 1861 1862 1863 1864 1865
	mmc->f_min = OMAP_MMC_MIN_CLOCK;

	if (pdata->max_freq > 0)
		mmc->f_max = pdata->max_freq;
	else
		mmc->f_max = OMAP_MMC_MAX_CLOCK;
1866

1867
	spin_lock_init(&host->irq_lock);
1868

1869
	host->fclk = clk_get(&pdev->dev, "fck");
1870 1871 1872 1873 1874 1875
	if (IS_ERR(host->fclk)) {
		ret = PTR_ERR(host->fclk);
		host->fclk = NULL;
		goto err1;
	}

1876 1877 1878 1879
	if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
		dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
		mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
	}
1880

1881 1882 1883 1884
	pm_runtime_enable(host->dev);
	pm_runtime_get_sync(host->dev);
	pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
	pm_runtime_use_autosuspend(host->dev);
1885

1886 1887
	omap_hsmmc_context_save(host);

1888 1889 1890 1891 1892 1893
	host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
	/*
	 * MMC can still work without debounce clock.
	 */
	if (IS_ERR(host->dbclk)) {
		host->dbclk = NULL;
1894
	} else if (clk_prepare_enable(host->dbclk) != 0) {
1895 1896 1897
		dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
		clk_put(host->dbclk);
		host->dbclk = NULL;
1898
	}
1899

1900 1901
	/* Since we do only SG emulation, we can have as many segs
	 * as we want. */
1902
	mmc->max_segs = 1024;
1903

1904 1905 1906 1907 1908
	mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
	mmc->max_seg_size = mmc->max_req_size;

1909
	mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1910
		     MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1911

1912 1913
	mmc->caps |= mmc_slot(host).caps;
	if (mmc->caps & MMC_CAP_8_BIT_DATA)
1914 1915
		mmc->caps |= MMC_CAP_4_BIT_DATA;

1916
	if (mmc_slot(host).nonremovable)
1917 1918
		mmc->caps |= MMC_CAP_NONREMOVABLE;

1919 1920
	mmc->pm_caps = mmc_slot(host).pm_caps;

1921
	omap_hsmmc_conf_bus_power(host);
1922

1923 1924 1925 1926 1927 1928 1929 1930
	if (!pdev->dev.of_node) {
		res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
		if (!res) {
			dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
			ret = -ENXIO;
			goto err_irq;
		}
		tx_req = res->start;
1931

1932 1933 1934 1935 1936 1937 1938
		res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
		if (!res) {
			dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
			ret = -ENXIO;
			goto err_irq;
		}
		rx_req = res->start;
1939
	}
1940

1941 1942 1943
	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

1944 1945 1946 1947
	host->rx_chan =
		dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
						 &rx_req, &pdev->dev, "rx");

1948 1949
	if (!host->rx_chan) {
		dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
1950
		ret = -ENXIO;
1951 1952 1953
		goto err_irq;
	}

1954 1955 1956 1957
	host->tx_chan =
		dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
						 &tx_req, &pdev->dev, "tx");

1958 1959
	if (!host->tx_chan) {
		dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
1960
		ret = -ENXIO;
1961
		goto err_irq;
1962
	}
1963 1964

	/* Request IRQ for MMC operations */
1965
	ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1966 1967
			mmc_hostname(mmc), host);
	if (ret) {
1968
		dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1969 1970 1971 1972 1973
		goto err_irq;
	}

	if (pdata->init != NULL) {
		if (pdata->init(&pdev->dev) != 0) {
1974
			dev_err(mmc_dev(host->mmc),
1975
				"Unable to configure MMC IRQs\n");
1976 1977 1978
			goto err_irq_cd_init;
		}
	}
1979

1980
	if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1981 1982 1983 1984 1985 1986
		ret = omap_hsmmc_reg_get(host);
		if (ret)
			goto err_reg;
		host->use_reg = 1;
	}

1987
	mmc->ocr_avail = mmc_slot(host).ocr_mask;
1988 1989

	/* Request IRQ for card detect */
1990
	if ((mmc_slot(host).card_detect_irq)) {
1991 1992 1993
		ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
					   NULL,
					   omap_hsmmc_detect,
1994
					   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1995
					   mmc_hostname(mmc), host);
1996
		if (ret) {
1997
			dev_err(mmc_dev(host->mmc),
1998 1999 2000
				"Unable to grab MMC CD IRQ\n");
			goto err_irq_cd;
		}
2001 2002
		pdata->suspend = omap_hsmmc_suspend_cdirq;
		pdata->resume = omap_hsmmc_resume_cdirq;
2003 2004
	}

2005
	omap_hsmmc_disable_irq(host);
2006

2007 2008 2009 2010 2011
	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
	if (IS_ERR(pinctrl))
		dev_warn(&pdev->dev,
			"pins are not configured from the driver\n");

2012 2013
	omap_hsmmc_protect_card(host);

2014 2015
	mmc_add_host(mmc);

2016
	if (mmc_slot(host).name != NULL) {
2017 2018 2019 2020
		ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
		if (ret < 0)
			goto err_slot_name;
	}
2021
	if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2022 2023 2024
		ret = device_create_file(&mmc->class_dev,
					&dev_attr_cover_switch);
		if (ret < 0)
2025
			goto err_slot_name;
2026 2027
	}

2028
	omap_hsmmc_debugfs(mmc);
2029 2030
	pm_runtime_mark_last_busy(host->dev);
	pm_runtime_put_autosuspend(host->dev);
2031

2032 2033 2034 2035 2036
	return 0;

err_slot_name:
	mmc_remove_host(mmc);
	free_irq(mmc_slot(host).card_detect_irq, host);
2037 2038 2039 2040 2041 2042
err_irq_cd:
	if (host->use_reg)
		omap_hsmmc_reg_put(host);
err_reg:
	if (host->pdata->cleanup)
		host->pdata->cleanup(&pdev->dev);
2043 2044 2045
err_irq_cd_init:
	free_irq(host->irq, host);
err_irq:
2046 2047 2048 2049
	if (host->tx_chan)
		dma_release_channel(host->tx_chan);
	if (host->rx_chan)
		dma_release_channel(host->rx_chan);
2050
	pm_runtime_put_sync(host->dev);
2051
	pm_runtime_disable(host->dev);
2052
	clk_put(host->fclk);
2053
	if (host->dbclk) {
2054
		clk_disable_unprepare(host->dbclk);
2055 2056 2057 2058
		clk_put(host->dbclk);
	}
err1:
	iounmap(host->base);
2059 2060 2061
	mmc_free_host(mmc);
err_alloc:
	omap_hsmmc_gpio_free(pdata);
2062
err:
2063 2064 2065
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res)
		release_mem_region(res->start, resource_size(res));
2066 2067 2068
	return ret;
}

2069
static int omap_hsmmc_remove(struct platform_device *pdev)
2070
{
2071
	struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2072 2073
	struct resource *res;

2074 2075 2076 2077 2078 2079 2080 2081 2082
	pm_runtime_get_sync(host->dev);
	mmc_remove_host(host->mmc);
	if (host->use_reg)
		omap_hsmmc_reg_put(host);
	if (host->pdata->cleanup)
		host->pdata->cleanup(&pdev->dev);
	free_irq(host->irq, host);
	if (mmc_slot(host).card_detect_irq)
		free_irq(mmc_slot(host).card_detect_irq, host);
2083

2084 2085 2086 2087 2088
	if (host->tx_chan)
		dma_release_channel(host->tx_chan);
	if (host->rx_chan)
		dma_release_channel(host->rx_chan);

2089 2090 2091
	pm_runtime_put_sync(host->dev);
	pm_runtime_disable(host->dev);
	clk_put(host->fclk);
2092
	if (host->dbclk) {
2093
		clk_disable_unprepare(host->dbclk);
2094
		clk_put(host->dbclk);
2095 2096
	}

2097
	omap_hsmmc_gpio_free(host->pdata);
2098
	iounmap(host->base);
2099
	mmc_free_host(host->mmc);
2100

2101 2102
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res)
2103
		release_mem_region(res->start, resource_size(res));
2104 2105 2106 2107 2108

	return 0;
}

#ifdef CONFIG_PM
2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127
static int omap_hsmmc_prepare(struct device *dev)
{
	struct omap_hsmmc_host *host = dev_get_drvdata(dev);

	if (host->pdata->suspend)
		return host->pdata->suspend(dev, host->slot_id);

	return 0;
}

static void omap_hsmmc_complete(struct device *dev)
{
	struct omap_hsmmc_host *host = dev_get_drvdata(dev);

	if (host->pdata->resume)
		host->pdata->resume(dev, host->slot_id);

}

2128
static int omap_hsmmc_suspend(struct device *dev)
2129
{
2130
	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2131

2132
	if (!host)
2133 2134
		return 0;

2135
	pm_runtime_get_sync(host->dev);
2136

2137 2138 2139 2140
	if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
		omap_hsmmc_disable_irq(host);
		OMAP_HSMMC_WRITE(host->base, HCTL,
				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2141
	}
2142

2143
	if (host->dbclk)
2144
		clk_disable_unprepare(host->dbclk);
2145

2146
	pm_runtime_put_sync(host->dev);
2147
	return 0;
2148 2149 2150
}

/* Routine to resume the MMC device */
2151
static int omap_hsmmc_resume(struct device *dev)
2152
{
2153 2154 2155 2156
	struct omap_hsmmc_host *host = dev_get_drvdata(dev);

	if (!host)
		return 0;
2157

2158
	pm_runtime_get_sync(host->dev);
2159

2160
	if (host->dbclk)
2161
		clk_prepare_enable(host->dbclk);
2162

2163 2164
	if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
		omap_hsmmc_conf_bus_power(host);
2165

2166
	omap_hsmmc_protect_card(host);
2167

2168 2169
	pm_runtime_mark_last_busy(host->dev);
	pm_runtime_put_autosuspend(host->dev);
2170
	return 0;
2171 2172 2173
}

#else
2174 2175
#define omap_hsmmc_prepare	NULL
#define omap_hsmmc_complete	NULL
2176
#define omap_hsmmc_suspend	NULL
2177
#define omap_hsmmc_resume	NULL
2178 2179
#endif

2180 2181 2182 2183 2184 2185
static int omap_hsmmc_runtime_suspend(struct device *dev)
{
	struct omap_hsmmc_host *host;

	host = platform_get_drvdata(to_platform_device(dev));
	omap_hsmmc_context_save(host);
2186
	dev_dbg(dev, "disabled\n");
2187 2188 2189 2190 2191 2192 2193 2194 2195 2196

	return 0;
}

static int omap_hsmmc_runtime_resume(struct device *dev)
{
	struct omap_hsmmc_host *host;

	host = platform_get_drvdata(to_platform_device(dev));
	omap_hsmmc_context_restore(host);
2197
	dev_dbg(dev, "enabled\n");
2198 2199 2200 2201

	return 0;
}

2202
static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2203 2204
	.suspend	= omap_hsmmc_suspend,
	.resume		= omap_hsmmc_resume,
2205 2206
	.prepare	= omap_hsmmc_prepare,
	.complete	= omap_hsmmc_complete,
2207 2208
	.runtime_suspend = omap_hsmmc_runtime_suspend,
	.runtime_resume = omap_hsmmc_runtime_resume,
2209 2210 2211
};

static struct platform_driver omap_hsmmc_driver = {
2212
	.probe		= omap_hsmmc_probe,
2213
	.remove		= omap_hsmmc_remove,
2214 2215 2216
	.driver		= {
		.name = DRIVER_NAME,
		.owner = THIS_MODULE,
2217
		.pm = &omap_hsmmc_dev_pm_ops,
2218
		.of_match_table = of_match_ptr(omap_mmc_of_match),
2219 2220 2221
	},
};

2222
module_platform_driver(omap_hsmmc_driver);
2223 2224 2225 2226
MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_AUTHOR("Texas Instruments Inc");
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