hda_intel.c 86.9 KB
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/*
 *
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 *  hda_intel.c - Implementation of primary alsa driver code base
 *                for Intel HD Audio.
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 *
 *  Copyright(c) 2004 Intel Corporation. All rights reserved.
 *
 *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
 *                     PeiSen Hou <pshou@realtek.com.tw>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the Free
 *  Software Foundation; either version 2 of the License, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *
 *  You should have received a copy of the GNU General Public License along with
 *  this program; if not, write to the Free Software Foundation, Inc., 59
 *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 *  CONTACTS:
 *
 *  Matt Jared		matt.jared@intel.com
 *  Andy Kopp		andy.kopp@intel.com
 *  Dan Kogan		dan.d.kogan@intel.com
 *
 *  CHANGES:
 *
 *  2004.12.01	Major rewrite by tiwai, merged the work of pshou
 * 
 */

#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/pci.h>
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#include <linux/mutex.h>
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#include <linux/reboot.h>
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#include <linux/io.h>
#ifdef CONFIG_X86
/* for snoop control */
#include <asm/pgtable.h>
#include <asm/cacheflush.h>
#endif
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#include <sound/core.h>
#include <sound/initval.h>
#include "hda_codec.h"


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static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
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static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
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static char *model[SNDRV_CARDS];
static int position_fix[SNDRV_CARDS];
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static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
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static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
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static int probe_only[SNDRV_CARDS];
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static bool single_cmd;
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static int enable_msi = -1;
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#ifdef CONFIG_SND_HDA_PATCH_LOADER
static char *patch[SNDRV_CARDS];
#endif
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#ifdef CONFIG_SND_HDA_INPUT_BEEP
static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
					CONFIG_SND_HDA_INPUT_BEEP_MODE};
#endif
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module_param_array(index, int, NULL, 0444);
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MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
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module_param_array(id, charp, NULL, 0444);
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MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
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module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
module_param_array(model, charp, NULL, 0444);
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MODULE_PARM_DESC(model, "Use the given board model.");
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module_param_array(position_fix, int, NULL, 0444);
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MODULE_PARM_DESC(position_fix, "DMA pointer read method."
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		 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
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module_param_array(bdl_pos_adj, int, NULL, 0644);
MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
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module_param_array(probe_mask, int, NULL, 0444);
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MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
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module_param_array(probe_only, int, NULL, 0444);
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MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
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module_param(single_cmd, bool, 0444);
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MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
		 "(for debugging only).");
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module_param(enable_msi, bint, 0444);
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MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
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#ifdef CONFIG_SND_HDA_PATCH_LOADER
module_param_array(patch, charp, NULL, 0444);
MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
#endif
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#ifdef CONFIG_SND_HDA_INPUT_BEEP
module_param_array(beep_mode, int, NULL, 0444);
MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
			    "(0=off, 1=on, 2=mute switch on/off) (default=1).");
#endif
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#ifdef CONFIG_SND_HDA_POWER_SAVE
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static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
module_param(power_save, int, 0644);
MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
		 "(in second, 0 = disable).");
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/* reset the HD-audio controller in power save mode.
 * this may give more power-saving, but will take longer time to
 * wake up.
 */
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static bool power_save_controller = 1;
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module_param(power_save_controller, bool, 0644);
MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
#endif

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static int align_buffer_size = -1;
module_param(align_buffer_size, bint, 0644);
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MODULE_PARM_DESC(align_buffer_size,
		"Force buffer and period sizes to be multiple of 128 bytes.");

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#ifdef CONFIG_X86
static bool hda_snoop = true;
module_param_named(snoop, hda_snoop, bool, 0444);
MODULE_PARM_DESC(snoop, "Enable/disable snooping");
#define azx_snoop(chip)		(chip)->snoop
#else
#define hda_snoop		true
#define azx_snoop(chip)		true
#endif


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MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
			 "{Intel, ICH6M},"
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			 "{Intel, ICH7},"
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			 "{Intel, ESB2},"
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			 "{Intel, ICH8},"
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			 "{Intel, ICH9},"
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			 "{Intel, ICH10},"
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			 "{Intel, PCH},"
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			 "{Intel, CPT},"
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			 "{Intel, PPT},"
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			 "{Intel, LPT},"
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			 "{Intel, PBG},"
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			 "{Intel, SCH},"
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			 "{ATI, SB450},"
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			 "{ATI, SB600},"
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			 "{ATI, RS600},"
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			 "{ATI, RS690},"
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			 "{ATI, RS780},"
			 "{ATI, R600},"
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			 "{ATI, RV630},"
			 "{ATI, RV610},"
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			 "{ATI, RV670},"
			 "{ATI, RV635},"
			 "{ATI, RV620},"
			 "{ATI, RV770},"
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			 "{VIA, VT8251},"
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			 "{VIA, VT8237A},"
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			 "{SiS, SIS966},"
			 "{ULI, M5461}}");
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MODULE_DESCRIPTION("Intel HDA driver");

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#ifdef CONFIG_SND_VERBOSE_PRINTK
#define SFX	/* nop */
#else
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#define SFX	"hda-intel: "
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#endif
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/*
 * registers
 */
#define ICH6_REG_GCAP			0x00
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#define   ICH6_GCAP_64OK	(1 << 0)   /* 64bit address support */
#define   ICH6_GCAP_NSDO	(3 << 1)   /* # of serial data out signals */
#define   ICH6_GCAP_BSS		(31 << 3)  /* # of bidirectional streams */
#define   ICH6_GCAP_ISS		(15 << 8)  /* # of input streams */
#define   ICH6_GCAP_OSS		(15 << 12) /* # of output streams */
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#define ICH6_REG_VMIN			0x02
#define ICH6_REG_VMAJ			0x03
#define ICH6_REG_OUTPAY			0x04
#define ICH6_REG_INPAY			0x06
#define ICH6_REG_GCTL			0x08
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#define   ICH6_GCTL_RESET	(1 << 0)   /* controller reset */
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#define   ICH6_GCTL_FCNTRL	(1 << 1)   /* flush control */
#define   ICH6_GCTL_UNSOL	(1 << 8)   /* accept unsol. response enable */
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#define ICH6_REG_WAKEEN			0x0c
#define ICH6_REG_STATESTS		0x0e
#define ICH6_REG_GSTS			0x10
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#define   ICH6_GSTS_FSTS	(1 << 1)   /* flush status */
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#define ICH6_REG_INTCTL			0x20
#define ICH6_REG_INTSTS			0x24
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#define ICH6_REG_WALLCLK		0x30	/* 24Mhz source */
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#define ICH6_REG_OLD_SSYNC		0x34	/* SSYNC for old ICH */
#define ICH6_REG_SSYNC			0x38
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#define ICH6_REG_CORBLBASE		0x40
#define ICH6_REG_CORBUBASE		0x44
#define ICH6_REG_CORBWP			0x48
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#define ICH6_REG_CORBRP			0x4a
#define   ICH6_CORBRP_RST	(1 << 15)  /* read pointer reset */
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#define ICH6_REG_CORBCTL		0x4c
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#define   ICH6_CORBCTL_RUN	(1 << 1)   /* enable DMA */
#define   ICH6_CORBCTL_CMEIE	(1 << 0)   /* enable memory error irq */
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#define ICH6_REG_CORBSTS		0x4d
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#define   ICH6_CORBSTS_CMEI	(1 << 0)   /* memory error indication */
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#define ICH6_REG_CORBSIZE		0x4e

#define ICH6_REG_RIRBLBASE		0x50
#define ICH6_REG_RIRBUBASE		0x54
#define ICH6_REG_RIRBWP			0x58
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#define   ICH6_RIRBWP_RST	(1 << 15)  /* write pointer reset */
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#define ICH6_REG_RINTCNT		0x5a
#define ICH6_REG_RIRBCTL		0x5c
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#define   ICH6_RBCTL_IRQ_EN	(1 << 0)   /* enable IRQ */
#define   ICH6_RBCTL_DMA_EN	(1 << 1)   /* enable DMA */
#define   ICH6_RBCTL_OVERRUN_EN	(1 << 2)   /* enable overrun irq */
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#define ICH6_REG_RIRBSTS		0x5d
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#define   ICH6_RBSTS_IRQ	(1 << 0)   /* response irq */
#define   ICH6_RBSTS_OVERRUN	(1 << 2)   /* overrun irq */
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#define ICH6_REG_RIRBSIZE		0x5e

#define ICH6_REG_IC			0x60
#define ICH6_REG_IR			0x64
#define ICH6_REG_IRS			0x68
#define   ICH6_IRS_VALID	(1<<1)
#define   ICH6_IRS_BUSY		(1<<0)

#define ICH6_REG_DPLBASE		0x70
#define ICH6_REG_DPUBASE		0x74
#define   ICH6_DPLBASE_ENABLE	0x1	/* Enable position buffer */

/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

/* stream register offsets from stream base */
#define ICH6_REG_SD_CTL			0x00
#define ICH6_REG_SD_STS			0x03
#define ICH6_REG_SD_LPIB		0x04
#define ICH6_REG_SD_CBL			0x08
#define ICH6_REG_SD_LVI			0x0c
#define ICH6_REG_SD_FIFOW		0x0e
#define ICH6_REG_SD_FIFOSIZE		0x10
#define ICH6_REG_SD_FORMAT		0x12
#define ICH6_REG_SD_BDLPL		0x18
#define ICH6_REG_SD_BDLPU		0x1c

/* PCI space */
#define ICH6_PCIREG_TCSEL	0x44

/*
 * other constants
 */

/* max number of SDs */
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/* ICH, ATI and VIA have 4 playback and 4 capture */
#define ICH6_NUM_CAPTURE	4
#define ICH6_NUM_PLAYBACK	4

/* ULI has 6 playback and 5 capture */
#define ULI_NUM_CAPTURE		5
#define ULI_NUM_PLAYBACK	6

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/* ATI HDMI has 1 playback and 0 capture */
#define ATIHDMI_NUM_CAPTURE	0
#define ATIHDMI_NUM_PLAYBACK	1

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/* TERA has 4 playback and 3 capture */
#define TERA_NUM_CAPTURE	3
#define TERA_NUM_PLAYBACK	4

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/* this number is statically defined for simplicity */
#define MAX_AZX_DEV		16

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/* max number of fragments - we may use more if allocating more pages for BDL */
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#define BDL_SIZE		4096
#define AZX_MAX_BDL_ENTRIES	(BDL_SIZE / 16)
#define AZX_MAX_FRAG		32
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/* max buffer size - no h/w limit, you can increase as you like */
#define AZX_MAX_BUF_SIZE	(1024*1024*1024)

/* RIRB int mask: overrun[2], response[0] */
#define RIRB_INT_RESPONSE	0x01
#define RIRB_INT_OVERRUN	0x04
#define RIRB_INT_MASK		0x05

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/* STATESTS int mask: S3,SD2,SD1,SD0 */
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#define AZX_MAX_CODECS		8
#define AZX_DEFAULT_CODECS	4
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#define STATESTS_INT_MASK	((1 << AZX_MAX_CODECS) - 1)
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/* SD_CTL bits */
#define SD_CTL_STREAM_RESET	0x01	/* stream reset bit */
#define SD_CTL_DMA_START	0x02	/* stream DMA start bit */
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#define SD_CTL_STRIPE		(3 << 16)	/* stripe control */
#define SD_CTL_TRAFFIC_PRIO	(1 << 18)	/* traffic priority */
#define SD_CTL_DIR		(1 << 19)	/* bi-directional stream */
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#define SD_CTL_STREAM_TAG_MASK	(0xf << 20)
#define SD_CTL_STREAM_TAG_SHIFT	20

/* SD_CTL and SD_STS */
#define SD_INT_DESC_ERR		0x10	/* descriptor error interrupt */
#define SD_INT_FIFO_ERR		0x08	/* FIFO error interrupt */
#define SD_INT_COMPLETE		0x04	/* completion interrupt */
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#define SD_INT_MASK		(SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
				 SD_INT_COMPLETE)
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/* SD_STS */
#define SD_STS_FIFO_READY	0x20	/* FIFO ready */

/* INTCTL and INTSTS */
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#define ICH6_INT_ALL_STREAM	0xff	   /* all stream interrupts */
#define ICH6_INT_CTRL_EN	0x40000000 /* controller interrupt enable bit */
#define ICH6_INT_GLOBAL_EN	0x80000000 /* global interrupt enable bit */
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/* below are so far hardcoded - should read registers in future */
#define ICH6_MAX_CORB_ENTRIES	256
#define ICH6_MAX_RIRB_ENTRIES	256

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/* position fix mode */
enum {
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	POS_FIX_AUTO,
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	POS_FIX_LPIB,
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	POS_FIX_POSBUF,
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	POS_FIX_VIACOMBO,
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	POS_FIX_COMBO,
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};
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/* Defines for ATI HD Audio support in SB450 south bridge */
#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
#define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02

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/* Defines for Nvidia HDA support */
#define NVIDIA_HDA_TRANSREG_ADDR      0x4e
#define NVIDIA_HDA_ENABLE_COHBITS     0x0f
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#define NVIDIA_HDA_ISTRM_COH          0x4d
#define NVIDIA_HDA_OSTRM_COH          0x4c
#define NVIDIA_HDA_ENABLE_COHBIT      0x01
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/* Defines for Intel SCH HDA snoop control */
#define INTEL_SCH_HDA_DEVC      0x78
#define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)

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/* Define IN stream 0 FIFO size offset in VIA controller */
#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET	0x90
/* Define VIA HD Audio Device ID*/
#define VIA_HDAC_DEVICE_ID		0x3288

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/* HD Audio class code */
#define PCI_CLASS_MULTIMEDIA_HD_AUDIO	0x0403
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/*
 */

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struct azx_dev {
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	struct snd_dma_buffer bdl; /* BDL buffer */
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	u32 *posbuf;		/* position buffer pointer */
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	unsigned int bufsize;	/* size of the play buffer in bytes */
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	unsigned int period_bytes; /* size of the period in bytes */
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	unsigned int frags;	/* number for period in the play buffer */
	unsigned int fifo_size;	/* FIFO size */
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	unsigned long start_wallclk;	/* start + minimum wallclk */
	unsigned long period_wallclk;	/* wallclk for period */
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	void __iomem *sd_addr;	/* stream descriptor pointer */
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	u32 sd_int_sta_mask;	/* stream int status mask */
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	/* pcm support */
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	struct snd_pcm_substream *substream;	/* assigned substream,
						 * set in PCM open
						 */
	unsigned int format_val;	/* format value to be set in the
					 * controller and the codec
					 */
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	unsigned char stream_tag;	/* assigned stream */
	unsigned char index;		/* stream index */
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	int assigned_key;		/* last device# key assigned to */
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	unsigned int opened :1;
	unsigned int running :1;
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	unsigned int irq_pending :1;
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	/*
	 * For VIA:
	 *  A flag to ensure DMA position is 0
	 *  when link position is not greater than FIFO size
	 */
	unsigned int insufficient :1;
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	unsigned int wc_marked:1;
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};

/* CORB/RIRB */
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struct azx_rb {
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	u32 *buf;		/* CORB/RIRB buffer
				 * Each CORB entry is 4byte, RIRB is 8byte
				 */
	dma_addr_t addr;	/* physical address of CORB/RIRB buffer */
	/* for RIRB */
	unsigned short rp, wp;	/* read/write pointers */
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	int cmds[AZX_MAX_CODECS];	/* number of pending requests */
	u32 res[AZX_MAX_CODECS];	/* last read value */
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};

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struct azx_pcm {
	struct azx *chip;
	struct snd_pcm *pcm;
	struct hda_codec *codec;
	struct hda_pcm_stream *hinfo[2];
	struct list_head list;
};

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struct azx {
	struct snd_card *card;
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	struct pci_dev *pci;
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	int dev_index;
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	/* chip type specific */
	int driver_type;
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	unsigned int driver_caps;
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	int playback_streams;
	int playback_index_offset;
	int capture_streams;
	int capture_index_offset;
	int num_streams;

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	/* pci resources */
	unsigned long addr;
	void __iomem *remap_addr;
	int irq;

	/* locks */
	spinlock_t reg_lock;
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	struct mutex open_mutex;
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	/* streams (x num_streams) */
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	struct azx_dev *azx_dev;
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	/* PCM */
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	struct list_head pcm_list; /* azx_pcm list */
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	/* HD codec */
	unsigned short codec_mask;
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	int  codec_probe_mask; /* copied from probe_mask option */
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	struct hda_bus *bus;
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	unsigned int beep_mode;
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	/* CORB/RIRB */
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	struct azx_rb corb;
	struct azx_rb rirb;
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	/* CORB/RIRB and position buffers */
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	struct snd_dma_buffer rb;
	struct snd_dma_buffer posbuf;
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	/* flags */
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	int position_fix[2]; /* for both playback/capture streams */
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	int poll_count;
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	unsigned int running :1;
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	unsigned int initialized :1;
	unsigned int single_cmd :1;
	unsigned int polling_mode :1;
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	unsigned int msi :1;
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	unsigned int irq_pending_warned :1;
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	unsigned int probing :1; /* codec probing phase */
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	unsigned int snoop:1;
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	unsigned int align_buffer_size:1;
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	/* for debugging */
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	unsigned int last_cmd[AZX_MAX_CODECS];
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	/* for pending irqs */
	struct work_struct irq_pending_work;
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	/* reboot notifier (for mysterious hangup problem at power-down) */
	struct notifier_block reboot_notifier;
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};

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/* driver types */
enum {
	AZX_DRIVER_ICH,
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	AZX_DRIVER_PCH,
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	AZX_DRIVER_SCH,
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	AZX_DRIVER_ATI,
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	AZX_DRIVER_ATIHDMI,
493
	AZX_DRIVER_ATIHDMI_NS,
494 495 496
	AZX_DRIVER_VIA,
	AZX_DRIVER_SIS,
	AZX_DRIVER_ULI,
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	AZX_DRIVER_NVIDIA,
498
	AZX_DRIVER_TERA,
499
	AZX_DRIVER_CTX,
500
	AZX_DRIVER_CTHDA,
501
	AZX_DRIVER_GENERIC,
502
	AZX_NUM_DRIVERS, /* keep this as last entry */
503 504
};

505 506 507 508 509 510 511 512 513 514 515 516 517 518
/* driver quirks (capabilities) */
/* bits 0-7 are used for indicating driver type */
#define AZX_DCAPS_NO_TCSEL	(1 << 8)	/* No Intel TCSEL bit */
#define AZX_DCAPS_NO_MSI	(1 << 9)	/* No MSI support */
#define AZX_DCAPS_ATI_SNOOP	(1 << 10)	/* ATI snoop enable */
#define AZX_DCAPS_NVIDIA_SNOOP	(1 << 11)	/* Nvidia snoop enable */
#define AZX_DCAPS_SCH_SNOOP	(1 << 12)	/* SCH/PCH snoop enable */
#define AZX_DCAPS_RIRB_DELAY	(1 << 13)	/* Long delay in read loop */
#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)	/* Put a delay before read */
#define AZX_DCAPS_CTX_WORKAROUND (1 << 15)	/* X-Fi workaround */
#define AZX_DCAPS_POSFIX_LPIB	(1 << 16)	/* Use LPIB as default */
#define AZX_DCAPS_POSFIX_VIA	(1 << 17)	/* Use VIACOMBO as default */
#define AZX_DCAPS_NO_64BIT	(1 << 18)	/* No 64bit address */
#define AZX_DCAPS_SYNC_WRITE	(1 << 19)	/* sync each cmd write */
519
#define AZX_DCAPS_OLD_SSYNC	(1 << 20)	/* Old SSYNC reg for ICH */
520
#define AZX_DCAPS_BUFSIZE	(1 << 21)	/* no buffer size alignment */
521
#define AZX_DCAPS_ALIGN_BUFSIZE	(1 << 22)	/* buffer size alignment */
522
#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)	/* BDLE in 4k boundary */
523 524 525 526 527 528 529 530 531 532 533 534

/* quirks for ATI SB / AMD Hudson */
#define AZX_DCAPS_PRESET_ATI_SB \
	(AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
	 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)

/* quirks for ATI/AMD HDMI */
#define AZX_DCAPS_PRESET_ATI_HDMI \
	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)

/* quirks for Nvidia */
#define AZX_DCAPS_PRESET_NVIDIA \
535 536
	(AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
	 AZX_DCAPS_ALIGN_BUFSIZE)
537

538 539 540
#define AZX_DCAPS_PRESET_CTHDA \
	(AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)

541 542
static char *driver_short_names[] __devinitdata = {
	[AZX_DRIVER_ICH] = "HDA Intel",
543
	[AZX_DRIVER_PCH] = "HDA Intel PCH",
544
	[AZX_DRIVER_SCH] = "HDA Intel MID",
545
	[AZX_DRIVER_ATI] = "HDA ATI SB",
546
	[AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
547
	[AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
548 549
	[AZX_DRIVER_VIA] = "HDA VIA VT82xx",
	[AZX_DRIVER_SIS] = "HDA SIS966",
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	[AZX_DRIVER_ULI] = "HDA ULI M5461",
	[AZX_DRIVER_NVIDIA] = "HDA NVidia",
552
	[AZX_DRIVER_TERA] = "HDA Teradici", 
553
	[AZX_DRIVER_CTX] = "HDA Creative", 
554
	[AZX_DRIVER_CTHDA] = "HDA Creative",
555
	[AZX_DRIVER_GENERIC] = "HD-Audio Generic",
556 557
};

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/*
 * macros for easy use
 */
#define azx_writel(chip,reg,value) \
	writel(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readl(chip,reg) \
	readl((chip)->remap_addr + ICH6_REG_##reg)
#define azx_writew(chip,reg,value) \
	writew(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readw(chip,reg) \
	readw((chip)->remap_addr + ICH6_REG_##reg)
#define azx_writeb(chip,reg,value) \
	writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readb(chip,reg) \
	readb((chip)->remap_addr + ICH6_REG_##reg)

#define azx_sd_writel(dev,reg,value) \
	writel(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readl(dev,reg) \
	readl((dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_writew(dev,reg,value) \
	writew(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readw(dev,reg) \
	readw((dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_writeb(dev,reg,value) \
	writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readb(dev,reg) \
	readb((dev)->sd_addr + ICH6_REG_##reg)

/* for pcm support */
588
#define get_azx_dev(substream) (substream->runtime->private_data)
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#ifdef CONFIG_X86
static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
{
	if (azx_snoop(chip))
		return;
	if (addr && size) {
		int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
		if (on)
			set_memory_wc((unsigned long)addr, pages);
		else
			set_memory_wb((unsigned long)addr, pages);
	}
}

static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
				 bool on)
{
	__mark_pages_wc(chip, buf->area, buf->bytes, on);
}
static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
				   struct snd_pcm_runtime *runtime, bool on)
{
	if (azx_dev->wc_marked != on) {
		__mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
		azx_dev->wc_marked = on;
	}
}
#else
/* NOP for other archs */
static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
				 bool on)
{
}
static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
				   struct snd_pcm_runtime *runtime, bool on)
{
}
#endif

629
static int azx_acquire_irq(struct azx *chip, int do_disconnect);
630
static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
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/*
 * Interface for HD codec
 */

/*
 * CORB / RIRB interface
 */
638
static int azx_alloc_cmd_io(struct azx *chip)
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{
	int err;

	/* single page (at least 4096 bytes) must suffice for both ringbuffes */
643 644
	err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
				  snd_dma_pci_data(chip->pci),
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				  PAGE_SIZE, &chip->rb);
	if (err < 0) {
		snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
		return err;
	}
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	mark_pages_wc(chip, &chip->rb, true);
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	return 0;
}

654
static void azx_init_cmd_io(struct azx *chip)
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{
656
	spin_lock_irq(&chip->reg_lock);
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	/* CORB set up */
	chip->corb.addr = chip->rb.addr;
	chip->corb.buf = (u32 *)chip->rb.area;
	azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
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	azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
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663 664
	/* set the corb size to 256 entries (ULI requires explicitly) */
	azx_writeb(chip, CORBSIZE, 0x02);
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	/* set the corb write pointer to 0 */
	azx_writew(chip, CORBWP, 0);
	/* reset the corb hw read pointer */
668
	azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
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	/* enable corb dma */
670
	azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
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	/* RIRB set up */
	chip->rirb.addr = chip->rb.addr + 2048;
	chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
675 676
	chip->rirb.wp = chip->rirb.rp = 0;
	memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
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	azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
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	azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
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680 681
	/* set the rirb size to 256 entries (ULI requires explicitly) */
	azx_writeb(chip, RIRBSIZE, 0x02);
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	/* reset the rirb hw write pointer */
683
	azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
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	/* set N=1, get RIRB response interrupt for new entry */
685
	if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
686 687 688
		azx_writew(chip, RINTCNT, 0xc0);
	else
		azx_writew(chip, RINTCNT, 1);
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	/* enable rirb dma and response irq */
	azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
691
	spin_unlock_irq(&chip->reg_lock);
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}

694
static void azx_free_cmd_io(struct azx *chip)
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{
696
	spin_lock_irq(&chip->reg_lock);
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	/* disable ringbuffer DMAs */
	azx_writeb(chip, RIRBCTL, 0);
	azx_writeb(chip, CORBCTL, 0);
700
	spin_unlock_irq(&chip->reg_lock);
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}

703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724
static unsigned int azx_command_addr(u32 cmd)
{
	unsigned int addr = cmd >> 28;

	if (addr >= AZX_MAX_CODECS) {
		snd_BUG();
		addr = 0;
	}

	return addr;
}

static unsigned int azx_response_addr(u32 res)
{
	unsigned int addr = res & 0xf;

	if (addr >= AZX_MAX_CODECS) {
		snd_BUG();
		addr = 0;
	}

	return addr;
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}

/* send a command */
728
static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
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{
730
	struct azx *chip = bus->private_data;
731
	unsigned int addr = azx_command_addr(val);
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	unsigned int wp;

734 735
	spin_lock_irq(&chip->reg_lock);

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	/* add command to corb */
	wp = azx_readb(chip, CORBWP);
	wp++;
	wp %= ICH6_MAX_CORB_ENTRIES;

741
	chip->rirb.cmds[addr]++;
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	chip->corb.buf[wp] = cpu_to_le32(val);
	azx_writel(chip, CORBWP, wp);
744

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	spin_unlock_irq(&chip->reg_lock);

	return 0;
}

#define ICH6_RIRB_EX_UNSOL_EV	(1<<4)

/* retrieve RIRB entry - called from interrupt handler */
753
static void azx_update_rirb(struct azx *chip)
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{
	unsigned int rp, wp;
756
	unsigned int addr;
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	u32 res, res_ex;

	wp = azx_readb(chip, RIRBWP);
	if (wp == chip->rirb.wp)
		return;
	chip->rirb.wp = wp;
763

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	while (chip->rirb.rp != wp) {
		chip->rirb.rp++;
		chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;

		rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
		res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
		res = le32_to_cpu(chip->rirb.buf[rp]);
771
		addr = azx_response_addr(res_ex);
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		if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
			snd_hda_queue_unsol_event(chip->bus, res, res_ex);
774 775
		else if (chip->rirb.cmds[addr]) {
			chip->rirb.res[addr] = res;
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			smp_wmb();
777
			chip->rirb.cmds[addr]--;
778 779 780 781 782
		} else
			snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
				   "last cmd=%#08x\n",
				   res, res_ex,
				   chip->last_cmd[addr]);
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	}
}

/* receive a response */
787 788
static unsigned int azx_rirb_get_response(struct hda_bus *bus,
					  unsigned int addr)
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{
790
	struct azx *chip = bus->private_data;
791
	unsigned long timeout;
792
	unsigned long loopcounter;
793
	int do_poll = 0;
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795 796
 again:
	timeout = jiffies + msecs_to_jiffies(1000);
797 798

	for (loopcounter = 0;; loopcounter++) {
799
		if (chip->polling_mode || do_poll) {
800 801 802 803
			spin_lock_irq(&chip->reg_lock);
			azx_update_rirb(chip);
			spin_unlock_irq(&chip->reg_lock);
		}
804
		if (!chip->rirb.cmds[addr]) {
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			smp_rmb();
806
			bus->rirb_error = 0;
807 808 809

			if (!do_poll)
				chip->poll_count = 0;
810
			return chip->rirb.res[addr]; /* the last value */
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		}
812 813
		if (time_after(jiffies, timeout))
			break;
814
		if (bus->needs_damn_long_delay || loopcounter > 3000)
815 816 817 818 819
			msleep(2); /* temporary workaround */
		else {
			udelay(10);
			cond_resched();
		}
820
	}
821

822 823 824 825 826 827 828 829 830 831
	if (!chip->polling_mode && chip->poll_count < 2) {
		snd_printdd(SFX "azx_get_response timeout, "
			   "polling the codec once: last cmd=0x%08x\n",
			   chip->last_cmd[addr]);
		do_poll = 1;
		chip->poll_count++;
		goto again;
	}


832 833 834 835 836 837 838 839
	if (!chip->polling_mode) {
		snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
			   "switching to polling mode: last cmd=0x%08x\n",
			   chip->last_cmd[addr]);
		chip->polling_mode = 1;
		goto again;
	}

840
	if (chip->msi) {
841
		snd_printk(KERN_WARNING SFX "No response from codec, "
842 843
			   "disabling MSI: last cmd=0x%08x\n",
			   chip->last_cmd[addr]);
844 845 846 847
		free_irq(chip->irq, chip);
		chip->irq = -1;
		pci_disable_msi(chip->pci);
		chip->msi = 0;
848 849
		if (azx_acquire_irq(chip, 1) < 0) {
			bus->rirb_error = 1;
850
			return -1;
851
		}
852 853 854
		goto again;
	}

855 856 857 858 859 860 861 862
	if (chip->probing) {
		/* If this critical timeout happens during the codec probing
		 * phase, this is likely an access to a non-existing codec
		 * slot.  Better to return an error and reset the system.
		 */
		return -1;
	}

863 864 865
	/* a fatal communication error; need either to reset or to fallback
	 * to the single_cmd mode
	 */
866
	bus->rirb_error = 1;
867
	if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
868 869 870 871 872 873
		bus->response_reset = 1;
		return -1; /* give a chance to retry */
	}

	snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
		   "switching to single_cmd mode: last cmd=0x%08x\n",
874
		   chip->last_cmd[addr]);
875 876
	chip->single_cmd = 1;
	bus->response_reset = 0;
877
	/* release CORB/RIRB */
878
	azx_free_cmd_io(chip);
879 880
	/* disable unsolicited responses */
	azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
881
	return -1;
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}

/*
 * Use the single immediate command instead of CORB/RIRB for simplicity
 *
 * Note: according to Intel, this is not preferred use.  The command was
 *       intended for the BIOS only, and may get confused with unsolicited
 *       responses.  So, we shouldn't use it for normal operation from the
 *       driver.
 *       I left the codes, however, for debugging/testing purposes.
 */

894
/* receive a response */
895
static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
896 897 898 899 900 901 902
{
	int timeout = 50;

	while (timeout--) {
		/* check IRV busy bit */
		if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
			/* reuse rirb.res as the response return value */
903
			chip->rirb.res[addr] = azx_readl(chip, IR);
904 905 906 907 908 909 910
			return 0;
		}
		udelay(1);
	}
	if (printk_ratelimit())
		snd_printd(SFX "get_response timeout: IRS=0x%x\n",
			   azx_readw(chip, IRS));
911
	chip->rirb.res[addr] = -1;
912 913 914
	return -EIO;
}

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/* send a command */
916
static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
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{
918
	struct azx *chip = bus->private_data;
919
	unsigned int addr = azx_command_addr(val);
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	int timeout = 50;

922
	bus->rirb_error = 0;
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	while (timeout--) {
		/* check ICB busy bit */
925
		if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
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			/* Clear IRV valid bit */
927 928
			azx_writew(chip, IRS, azx_readw(chip, IRS) |
				   ICH6_IRS_VALID);
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			azx_writel(chip, IC, val);
930 931
			azx_writew(chip, IRS, azx_readw(chip, IRS) |
				   ICH6_IRS_BUSY);
932
			return azx_single_wait_for_response(chip, addr);
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		}
		udelay(1);
	}
936 937 938
	if (printk_ratelimit())
		snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
			   azx_readw(chip, IRS), val);
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	return -EIO;
}

/* receive a response */
943 944
static unsigned int azx_single_get_response(struct hda_bus *bus,
					    unsigned int addr)
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{
946
	struct azx *chip = bus->private_data;
947
	return chip->rirb.res[addr];
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}

950 951 952 953 954 955 956 957
/*
 * The below are the main callbacks from hda_codec.
 *
 * They are just the skeleton to call sub-callbacks according to the
 * current setting of chip->single_cmd.
 */

/* send a command */
958
static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
959
{
960
	struct azx *chip = bus->private_data;
961

962
	chip->last_cmd[azx_command_addr(val)] = val;
963
	if (chip->single_cmd)
964
		return azx_single_send_cmd(bus, val);
965
	else
966
		return azx_corb_send_cmd(bus, val);
967 968 969
}

/* get a response */
970 971
static unsigned int azx_get_response(struct hda_bus *bus,
				     unsigned int addr)
972
{
973
	struct azx *chip = bus->private_data;
974
	if (chip->single_cmd)
975
		return azx_single_get_response(bus, addr);
976
	else
977
		return azx_rirb_get_response(bus, addr);
978 979
}

980
#ifdef CONFIG_SND_HDA_POWER_SAVE
981
static void azx_power_notify(struct hda_bus *bus);
982
#endif
983

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/* reset codec link */
985
static int azx_reset(struct azx *chip, int full_reset)
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{
	int count;

989 990 991
	if (!full_reset)
		goto __skip;

992 993 994
	/* clear STATESTS */
	azx_writeb(chip, STATESTS, STATESTS_INT_MASK);

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	/* reset controller */
	azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);

	count = 50;
	while (azx_readb(chip, GCTL) && --count)
		msleep(1);

	/* delay for >= 100us for codec PLL to settle per spec
	 * Rev 0.9 section 5.5.1
	 */
	msleep(1);

	/* Bring controller out of reset */
	azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);

	count = 50;
1011
	while (!azx_readb(chip, GCTL) && --count)
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		msleep(1);

1014
	/* Brent Chartrand said to wait >= 540us for codecs to initialize */
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1015 1016
	msleep(1);

1017
      __skip:
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	/* check to see if controller is ready */
1019
	if (!azx_readb(chip, GCTL)) {
1020
		snd_printd(SFX "azx_reset: controller not ready!\n");
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		return -EBUSY;
	}

M
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	/* Accept unsolicited responses */
1025 1026 1027
	if (!chip->single_cmd)
		azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
			   ICH6_GCTL_UNSOL);
M
Matt 已提交
1028

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1029
	/* detect codecs */
1030
	if (!chip->codec_mask) {
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		chip->codec_mask = azx_readw(chip, STATESTS);
1032
		snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
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	}

	return 0;
}


/*
 * Lowlevel interface
 */  

/* enable interrupts */
1044
static void azx_int_enable(struct azx *chip)
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{
	/* enable controller CIE and GIE */
	azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
		   ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
}

/* disable interrupts */
1052
static void azx_int_disable(struct azx *chip)
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{
	int i;

	/* disable interrupts in stream descriptor */
1057
	for (i = 0; i < chip->num_streams; i++) {
1058
		struct azx_dev *azx_dev = &chip->azx_dev[i];
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		azx_sd_writeb(azx_dev, SD_CTL,
			      azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
	}

	/* disable SIE for all streams */
	azx_writeb(chip, INTCTL, 0);

	/* disable controller CIE and GIE */
	azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
		   ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
}

/* clear interrupts */
1072
static void azx_int_clear(struct azx *chip)
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{
	int i;

	/* clear stream status */
1077
	for (i = 0; i < chip->num_streams; i++) {
1078
		struct azx_dev *azx_dev = &chip->azx_dev[i];
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		azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
	}

	/* clear STATESTS */
	azx_writeb(chip, STATESTS, STATESTS_INT_MASK);

	/* clear rirb status */
	azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);

	/* clear int status */
	azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
}

/* start a stream */
1093
static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
L
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{
1095 1096 1097 1098 1099
	/*
	 * Before stream start, initialize parameter
	 */
	azx_dev->insufficient = 1;

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	/* enable SIE */
1101 1102
	azx_writel(chip, INTCTL,
		   azx_readl(chip, INTCTL) | (1 << azx_dev->index));
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	/* set DMA start and interrupt mask */
	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
		      SD_CTL_DMA_START | SD_INT_MASK);
}

1108 1109
/* stop DMA */
static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
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1110 1111 1112 1113
{
	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
		      ~(SD_CTL_DMA_START | SD_INT_MASK));
	azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1114 1115 1116 1117 1118 1119
}

/* stop a stream */
static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
{
	azx_stream_clear(chip, azx_dev);
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	/* disable SIE */
1121 1122
	azx_writel(chip, INTCTL,
		   azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
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}


/*
1127
 * reset and start the controller registers
L
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1128
 */
1129
static void azx_init_chip(struct azx *chip, int full_reset)
L
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1130
{
1131 1132
	if (chip->initialized)
		return;
L
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1133 1134

	/* reset controller */
1135
	azx_reset(chip, full_reset);
L
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1136 1137 1138 1139 1140 1141

	/* initialize interrupts */
	azx_int_clear(chip);
	azx_int_enable(chip);

	/* initialize the codec command I/O */
1142 1143
	if (!chip->single_cmd)
		azx_init_cmd_io(chip);
L
Linus Torvalds 已提交
1144

1145 1146
	/* program the position buffer */
	azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
T
Takashi Iwai 已提交
1147
	azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1148

1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171
	chip->initialized = 1;
}

/*
 * initialize the PCI registers
 */
/* update bits in a PCI register byte */
static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
			    unsigned char mask, unsigned char val)
{
	unsigned char data;

	pci_read_config_byte(pci, reg, &data);
	data &= ~mask;
	data |= (val & mask);
	pci_write_config_byte(pci, reg, data);
}

static void azx_init_pci(struct azx *chip)
{
	/* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
	 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
	 * Ensuring these bits are 0 clears playback static on some HD Audio
1172 1173
	 * codecs.
	 * The PCI register TCSEL is defined in the Intel manuals.
1174
	 */
1175
	if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1176
		snd_printdd(SFX "Clearing TCSEL\n");
1177
		update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1178
	}
1179

1180 1181 1182 1183
	/* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
	 * we need to enable snoop.
	 */
	if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
T
Takashi Iwai 已提交
1184
		snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1185
		update_pci_byte(chip->pci,
T
Takashi Iwai 已提交
1186 1187
				ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
				azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1188 1189 1190 1191
	}

	/* For NVIDIA HDA, enable snoop */
	if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
T
Takashi Iwai 已提交
1192
		snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1193 1194 1195
		update_pci_byte(chip->pci,
				NVIDIA_HDA_TRANSREG_ADDR,
				0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1196 1197 1198 1199 1200 1201
		update_pci_byte(chip->pci,
				NVIDIA_HDA_ISTRM_COH,
				0x01, NVIDIA_HDA_ENABLE_COHBIT);
		update_pci_byte(chip->pci,
				NVIDIA_HDA_OSTRM_COH,
				0x01, NVIDIA_HDA_ENABLE_COHBIT);
1202 1203 1204 1205
	}

	/* Enable SCH/PCH snoop if needed */
	if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
T
Takashi Iwai 已提交
1206
		unsigned short snoop;
T
Takashi Iwai 已提交
1207
		pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
T
Takashi Iwai 已提交
1208 1209 1210 1211 1212 1213
		if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
		    (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
			snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
			if (!azx_snoop(chip))
				snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
			pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
T
Takashi Iwai 已提交
1214 1215 1216
			pci_read_config_word(chip->pci,
				INTEL_SCH_HDA_DEVC, &snoop);
		}
T
Takashi Iwai 已提交
1217 1218 1219
		snd_printdd(SFX "SCH snoop: %s\n",
				(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
				? "Disabled" : "Enabled");
V
Vinod G 已提交
1220
        }
L
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1221 1222 1223
}


1224 1225
static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);

L
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1226 1227 1228
/*
 * interrupt handler
 */
1229
static irqreturn_t azx_interrupt(int irq, void *dev_id)
L
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1230
{
1231 1232
	struct azx *chip = dev_id;
	struct azx_dev *azx_dev;
L
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1233
	u32 status;
1234
	u8 sd_status;
1235
	int i, ok;
L
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1236 1237 1238 1239 1240 1241 1242 1243 1244

	spin_lock(&chip->reg_lock);

	status = azx_readl(chip, INTSTS);
	if (status == 0) {
		spin_unlock(&chip->reg_lock);
		return IRQ_NONE;
	}
	
1245
	for (i = 0; i < chip->num_streams; i++) {
L
Linus Torvalds 已提交
1246 1247
		azx_dev = &chip->azx_dev[i];
		if (status & azx_dev->sd_int_sta_mask) {
1248
			sd_status = azx_sd_readb(azx_dev, SD_STS);
L
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1249
			azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1250 1251
			if (!azx_dev->substream || !azx_dev->running ||
			    !(sd_status & SD_INT_COMPLETE))
1252 1253
				continue;
			/* check whether this IRQ is really acceptable */
1254 1255
			ok = azx_position_ok(chip, azx_dev);
			if (ok == 1) {
1256
				azx_dev->irq_pending = 0;
L
Linus Torvalds 已提交
1257 1258 1259
				spin_unlock(&chip->reg_lock);
				snd_pcm_period_elapsed(azx_dev->substream);
				spin_lock(&chip->reg_lock);
1260
			} else if (ok == 0 && chip->bus && chip->bus->workq) {
1261 1262
				/* bogus IRQ, process it later */
				azx_dev->irq_pending = 1;
T
Takashi Iwai 已提交
1263 1264
				queue_work(chip->bus->workq,
					   &chip->irq_pending_work);
L
Linus Torvalds 已提交
1265 1266 1267 1268 1269 1270 1271
			}
		}
	}

	/* clear rirb int */
	status = azx_readb(chip, RIRBSTS);
	if (status & RIRB_INT_MASK) {
1272
		if (status & RIRB_INT_RESPONSE) {
1273
			if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1274
				udelay(80);
L
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1275
			azx_update_rirb(chip);
1276
		}
L
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1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290
		azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
	}

#if 0
	/* clear state status int */
	if (azx_readb(chip, STATESTS) & 0x04)
		azx_writeb(chip, STATESTS, 0x04);
#endif
	spin_unlock(&chip->reg_lock);
	
	return IRQ_HANDLED;
}


1291 1292 1293
/*
 * set up a BDL entry
 */
1294 1295
static int setup_bdle(struct azx *chip,
		      struct snd_pcm_substream *substream,
1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307
		      struct azx_dev *azx_dev, u32 **bdlp,
		      int ofs, int size, int with_ioc)
{
	u32 *bdl = *bdlp;

	while (size > 0) {
		dma_addr_t addr;
		int chunk;

		if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
			return -EINVAL;

1308
		addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1309 1310
		/* program the address field of the BDL entry */
		bdl[0] = cpu_to_le32((u32)addr);
T
Takashi Iwai 已提交
1311
		bdl[1] = cpu_to_le32(upper_32_bits(addr));
1312
		/* program the size field of the BDL entry */
T
Takashi Iwai 已提交
1313
		chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1314 1315 1316 1317 1318 1319
		/* one BDLE cannot cross 4K boundary on CTHDA chips */
		if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
			u32 remain = 0x1000 - (ofs & 0xfff);
			if (chunk > remain)
				chunk = remain;
		}
1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333
		bdl[2] = cpu_to_le32(chunk);
		/* program the IOC to enable interrupt
		 * only when the whole fragment is processed
		 */
		size -= chunk;
		bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
		bdl += 4;
		azx_dev->frags++;
		ofs += chunk;
	}
	*bdlp = bdl;
	return ofs;
}

L
Linus Torvalds 已提交
1334 1335 1336
/*
 * set up BDL entries
 */
1337 1338
static int azx_setup_periods(struct azx *chip,
			     struct snd_pcm_substream *substream,
T
Takashi Iwai 已提交
1339
			     struct azx_dev *azx_dev)
L
Linus Torvalds 已提交
1340
{
T
Takashi Iwai 已提交
1341 1342
	u32 *bdl;
	int i, ofs, periods, period_bytes;
1343
	int pos_adj;
L
Linus Torvalds 已提交
1344 1345 1346 1347 1348

	/* reset BDL address */
	azx_sd_writel(azx_dev, SD_BDLPL, 0);
	azx_sd_writel(azx_dev, SD_BDLPU, 0);

1349
	period_bytes = azx_dev->period_bytes;
T
Takashi Iwai 已提交
1350 1351
	periods = azx_dev->bufsize / period_bytes;

L
Linus Torvalds 已提交
1352
	/* program the initial BDL entries */
T
Takashi Iwai 已提交
1353 1354 1355
	bdl = (u32 *)azx_dev->bdl.area;
	ofs = 0;
	azx_dev->frags = 0;
1356 1357
	pos_adj = bdl_pos_adj[chip->dev_index];
	if (pos_adj > 0) {
1358
		struct snd_pcm_runtime *runtime = substream->runtime;
1359
		int pos_align = pos_adj;
1360
		pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1361
		if (!pos_adj)
1362 1363 1364 1365
			pos_adj = pos_align;
		else
			pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
				pos_align;
1366 1367
		pos_adj = frames_to_bytes(runtime, pos_adj);
		if (pos_adj >= period_bytes) {
1368
			snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1369
				   bdl_pos_adj[chip->dev_index]);
1370 1371
			pos_adj = 0;
		} else {
1372
			ofs = setup_bdle(chip, substream, azx_dev,
1373 1374
					 &bdl, ofs, pos_adj,
					 !substream->runtime->no_period_wakeup);
1375 1376
			if (ofs < 0)
				goto error;
T
Takashi Iwai 已提交
1377
		}
1378 1379
	} else
		pos_adj = 0;
1380 1381
	for (i = 0; i < periods; i++) {
		if (i == periods - 1 && pos_adj)
1382
			ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1383 1384
					 period_bytes - pos_adj, 0);
		else
1385
			ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1386 1387
					 period_bytes,
					 !substream->runtime->no_period_wakeup);
1388 1389
		if (ofs < 0)
			goto error;
L
Linus Torvalds 已提交
1390
	}
T
Takashi Iwai 已提交
1391
	return 0;
1392 1393

 error:
1394
	snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1395 1396
		   azx_dev->bufsize, period_bytes);
	return -EINVAL;
L
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1397 1398
}

1399 1400
/* reset stream */
static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
L
Linus Torvalds 已提交
1401 1402 1403 1404
{
	unsigned char val;
	int timeout;

1405 1406
	azx_stream_clear(chip, azx_dev);

1407 1408
	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
		      SD_CTL_STREAM_RESET);
L
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1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422
	udelay(3);
	timeout = 300;
	while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
	       --timeout)
		;
	val &= ~SD_CTL_STREAM_RESET;
	azx_sd_writeb(azx_dev, SD_CTL, val);
	udelay(3);

	timeout = 300;
	/* waiting for hardware to report that the stream is out of reset */
	while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
	       --timeout)
		;
1423 1424 1425

	/* reset first position - may not be synced with hw at this time */
	*azx_dev->posbuf = 0;
1426
}
L
Linus Torvalds 已提交
1427

1428 1429 1430 1431 1432
/*
 * set up the SD for streaming
 */
static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
{
T
Takashi Iwai 已提交
1433
	unsigned int val;
1434 1435
	/* make sure the run bit is zero for SD */
	azx_stream_clear(chip, azx_dev);
L
Linus Torvalds 已提交
1436
	/* program the stream_tag */
T
Takashi Iwai 已提交
1437 1438 1439 1440 1441 1442
	val = azx_sd_readl(azx_dev, SD_CTL);
	val = (val & ~SD_CTL_STREAM_TAG_MASK) |
		(azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
	if (!azx_snoop(chip))
		val |= SD_CTL_TRAFFIC_PRIO;
	azx_sd_writel(azx_dev, SD_CTL, val);
L
Linus Torvalds 已提交
1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455

	/* program the length of samples in cyclic buffer */
	azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);

	/* program the stream format */
	/* this value needs to be the same as the one programmed */
	azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);

	/* program the stream LVI (last valid index) of the BDL */
	azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);

	/* program the BDL address */
	/* lower BDL address */
T
Takashi Iwai 已提交
1456
	azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
L
Linus Torvalds 已提交
1457
	/* upper BDL address */
T
Takashi Iwai 已提交
1458
	azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
L
Linus Torvalds 已提交
1459

1460
	/* enable the position buffer */
1461 1462
	if (chip->position_fix[0] != POS_FIX_LPIB ||
	    chip->position_fix[1] != POS_FIX_LPIB) {
1463 1464 1465 1466
		if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
			azx_writel(chip, DPLBASE,
				(u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
	}
1467

L
Linus Torvalds 已提交
1468
	/* set the interrupt enable bits in the descriptor control register */
1469 1470
	azx_sd_writel(azx_dev, SD_CTL,
		      azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
L
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	return 0;
}

1475 1476 1477 1478 1479 1480 1481 1482 1483
/*
 * Probe the given codec address
 */
static int probe_codec(struct azx *chip, int addr)
{
	unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
		(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
	unsigned int res;

1484
	mutex_lock(&chip->bus->cmd_mutex);
1485 1486
	chip->probing = 1;
	azx_send_cmd(chip->bus, cmd);
1487
	res = azx_get_response(chip->bus, addr);
1488
	chip->probing = 0;
1489
	mutex_unlock(&chip->bus->cmd_mutex);
1490 1491
	if (res == -1)
		return -EIO;
1492
	snd_printdd(SFX "codec #%d probed OK\n", addr);
1493 1494 1495
	return 0;
}

1496 1497
static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
				 struct hda_pcm *cpcm);
1498
static void azx_stop_chip(struct azx *chip);
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1500 1501 1502 1503 1504 1505
static void azx_bus_reset(struct hda_bus *bus)
{
	struct azx *chip = bus->private_data;

	bus->in_reset = 1;
	azx_stop_chip(chip);
1506
	azx_init_chip(chip, 1);
1507
#ifdef CONFIG_PM
1508
	if (chip->initialized) {
1509 1510 1511
		struct azx_pcm *p;
		list_for_each_entry(p, &chip->pcm_list, list)
			snd_pcm_suspend_all(p->pcm);
1512 1513 1514
		snd_hda_suspend(chip->bus);
		snd_hda_resume(chip->bus);
	}
1515
#endif
1516 1517 1518
	bus->in_reset = 0;
}

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/*
 * Codec initialization
 */

1523 1524
/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1525
	[AZX_DRIVER_NVIDIA] = 8,
1526
	[AZX_DRIVER_TERA] = 1,
1527 1528
};

1529
static int __devinit azx_codec_create(struct azx *chip, const char *model)
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{
	struct hda_bus_template bus_temp;
1532 1533
	int c, codecs, err;
	int max_slots;
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	memset(&bus_temp, 0, sizeof(bus_temp));
	bus_temp.private_data = chip;
	bus_temp.modelname = model;
	bus_temp.pci = chip->pci;
1539 1540
	bus_temp.ops.command = azx_send_cmd;
	bus_temp.ops.get_response = azx_get_response;
1541
	bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1542
	bus_temp.ops.bus_reset = azx_bus_reset;
1543
#ifdef CONFIG_SND_HDA_POWER_SAVE
1544
	bus_temp.power_save = &power_save;
1545 1546
	bus_temp.ops.pm_notify = azx_power_notify;
#endif
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1548 1549
	err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
	if (err < 0)
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		return err;

1552 1553
	if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
		snd_printd(SFX "Enable delay in RIRB handling\n");
1554
		chip->bus->needs_damn_long_delay = 1;
1555
	}
1556

1557
	codecs = 0;
1558 1559
	max_slots = azx_max_codecs[chip->driver_type];
	if (!max_slots)
1560
		max_slots = AZX_DEFAULT_CODECS;
1561 1562 1563

	/* First try to probe all given codec slots */
	for (c = 0; c < max_slots; c++) {
1564
		if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1565 1566 1567 1568
			if (probe_codec(chip, c) < 0) {
				/* Some BIOSen give you wrong codec addresses
				 * that don't exist
				 */
1569 1570
				snd_printk(KERN_WARNING SFX
					   "Codec #%d probe error; "
1571 1572 1573 1574
					   "disabling it...\n", c);
				chip->codec_mask &= ~(1 << c);
				/* More badly, accessing to a non-existing
				 * codec often screws up the controller chip,
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				 * and disturbs the further communications.
1576 1577 1578 1579 1580
				 * Thus if an error occurs during probing,
				 * better to reset the controller chip to
				 * get back to the sanity state.
				 */
				azx_stop_chip(chip);
1581
				azx_init_chip(chip, 1);
1582 1583 1584 1585
			}
		}
	}

1586 1587 1588 1589
	/* AMD chipsets often cause the communication stalls upon certain
	 * sequence like the pin-detection.  It seems that forcing the synced
	 * access works around the stall.  Grrr...
	 */
1590 1591
	if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
		snd_printd(SFX "Enable sync_write for stable communication\n");
1592 1593 1594 1595
		chip->bus->sync_write = 1;
		chip->bus->allow_bus_reset = 1;
	}

1596
	/* Then create codec instances */
1597
	for (c = 0; c < max_slots; c++) {
1598
		if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1599
			struct hda_codec *codec;
1600
			err = snd_hda_codec_new(chip->bus, c, &codec);
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			if (err < 0)
				continue;
1603
			codec->beep_mode = chip->beep_mode;
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			codecs++;
1605 1606 1607
		}
	}
	if (!codecs) {
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		snd_printk(KERN_ERR SFX "no codecs initialized\n");
		return -ENXIO;
	}
1611 1612
	return 0;
}
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1614 1615 1616 1617 1618 1619 1620
/* configure each codec instance */
static int __devinit azx_codec_configure(struct azx *chip)
{
	struct hda_codec *codec;
	list_for_each_entry(codec, &chip->bus->codec_list, list) {
		snd_hda_codec_configure(codec);
	}
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	return 0;
}


/*
 * PCM support
 */

/* assign a stream for the PCM */
1630 1631
static inline struct azx_dev *
azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
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{
1633
	int dev, i, nums;
1634
	struct azx_dev *res = NULL;
1635 1636 1637
	/* make a non-zero unique key for the substream */
	int key = (substream->pcm->device << 16) | (substream->number << 2) |
		(substream->stream + 1);
1638 1639

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1640 1641 1642 1643 1644 1645 1646
		dev = chip->playback_index_offset;
		nums = chip->playback_streams;
	} else {
		dev = chip->capture_index_offset;
		nums = chip->capture_streams;
	}
	for (i = 0; i < nums; i++, dev++)
1647
		if (!chip->azx_dev[dev].opened) {
1648
			res = &chip->azx_dev[dev];
1649
			if (res->assigned_key == key)
1650
				break;
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		}
1652 1653
	if (res) {
		res->opened = 1;
1654
		res->assigned_key = key;
1655 1656
	}
	return res;
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}

/* release the assigned stream */
1660
static inline void azx_release_device(struct azx_dev *azx_dev)
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{
	azx_dev->opened = 0;
}

1665
static struct snd_pcm_hardware azx_pcm_hw = {
1666 1667
	.info =			(SNDRV_PCM_INFO_MMAP |
				 SNDRV_PCM_INFO_INTERLEAVED |
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				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
				 SNDRV_PCM_INFO_MMAP_VALID |
1670 1671
				 /* No full-resume yet implemented */
				 /* SNDRV_PCM_INFO_RESUME |*/
1672
				 SNDRV_PCM_INFO_PAUSE |
1673 1674
				 SNDRV_PCM_INFO_SYNC_START |
				 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
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	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
	.rates =		SNDRV_PCM_RATE_48000,
	.rate_min =		48000,
	.rate_max =		48000,
	.channels_min =		2,
	.channels_max =		2,
	.buffer_bytes_max =	AZX_MAX_BUF_SIZE,
	.period_bytes_min =	128,
	.period_bytes_max =	AZX_MAX_BUF_SIZE / 2,
	.periods_min =		2,
	.periods_max =		AZX_MAX_FRAG,
	.fifo_size =		0,
};

1689
static int azx_pcm_open(struct snd_pcm_substream *substream)
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{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1693 1694 1695
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev;
	struct snd_pcm_runtime *runtime = substream->runtime;
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	unsigned long flags;
	int err;
1698
	int buff_step;
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1700
	mutex_lock(&chip->open_mutex);
1701
	azx_dev = azx_assign_device(chip, substream);
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	if (azx_dev == NULL) {
1703
		mutex_unlock(&chip->open_mutex);
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		return -EBUSY;
	}
	runtime->hw = azx_pcm_hw;
	runtime->hw.channels_min = hinfo->channels_min;
	runtime->hw.channels_max = hinfo->channels_max;
	runtime->hw.formats = hinfo->formats;
	runtime->hw.rates = hinfo->rates;
	snd_pcm_limit_hw_rates(runtime);
	snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1713
	if (chip->align_buffer_size)
1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727
		/* constrain buffer sizes to be multiple of 128
		   bytes. This is more efficient in terms of memory
		   access but isn't required by the HDA spec and
		   prevents users from specifying exact period/buffer
		   sizes. For example for 44.1kHz, a period size set
		   to 20ms will be rounded to 19.59ms. */
		buff_step = 128;
	else
		/* Don't enforce steps on buffer sizes, still need to
		   be multiple of 4 bytes (HDA spec). Tested on Intel
		   HDA controllers, may not work on all devices where
		   option needs to be disabled */
		buff_step = 4;

1728
	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1729
				   buff_step);
1730
	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1731
				   buff_step);
1732
	snd_hda_power_up(apcm->codec);
1733 1734
	err = hinfo->ops.open(hinfo, apcm->codec, substream);
	if (err < 0) {
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		azx_release_device(azx_dev);
1736
		snd_hda_power_down(apcm->codec);
1737
		mutex_unlock(&chip->open_mutex);
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1738 1739
		return err;
	}
1740
	snd_pcm_limit_hw_rates(runtime);
1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751
	/* sanity check */
	if (snd_BUG_ON(!runtime->hw.channels_min) ||
	    snd_BUG_ON(!runtime->hw.channels_max) ||
	    snd_BUG_ON(!runtime->hw.formats) ||
	    snd_BUG_ON(!runtime->hw.rates)) {
		azx_release_device(azx_dev);
		hinfo->ops.close(hinfo, apcm->codec, substream);
		snd_hda_power_down(apcm->codec);
		mutex_unlock(&chip->open_mutex);
		return -EINVAL;
	}
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	spin_lock_irqsave(&chip->reg_lock, flags);
	azx_dev->substream = substream;
	azx_dev->running = 0;
	spin_unlock_irqrestore(&chip->reg_lock, flags);

	runtime->private_data = azx_dev;
1758
	snd_pcm_set_sync(substream);
1759
	mutex_unlock(&chip->open_mutex);
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1760 1761 1762
	return 0;
}

1763
static int azx_pcm_close(struct snd_pcm_substream *substream)
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1764 1765 1766
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1767 1768
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);
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1769 1770
	unsigned long flags;

1771
	mutex_lock(&chip->open_mutex);
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	spin_lock_irqsave(&chip->reg_lock, flags);
	azx_dev->substream = NULL;
	azx_dev->running = 0;
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	azx_release_device(azx_dev);
	hinfo->ops.close(hinfo, apcm->codec, substream);
1778
	snd_hda_power_down(apcm->codec);
1779
	mutex_unlock(&chip->open_mutex);
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1780 1781 1782
	return 0;
}

1783 1784
static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
			     struct snd_pcm_hw_params *hw_params)
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1785
{
T
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1786 1787 1788
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
	struct snd_pcm_runtime *runtime = substream->runtime;
1789
	struct azx_dev *azx_dev = get_azx_dev(substream);
T
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1790
	int ret;
1791

T
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1792
	mark_runtime_wc(chip, azx_dev, runtime, false);
1793 1794 1795
	azx_dev->bufsize = 0;
	azx_dev->period_bytes = 0;
	azx_dev->format_val = 0;
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Takashi Iwai 已提交
1796
	ret = snd_pcm_lib_malloc_pages(substream,
1797
					params_buffer_bytes(hw_params));
T
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1798 1799 1800 1801
	if (ret < 0)
		return ret;
	mark_runtime_wc(chip, azx_dev, runtime, true);
	return ret;
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1802 1803
}

1804
static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
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1805 1806
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1807
	struct azx_dev *azx_dev = get_azx_dev(substream);
T
Takashi Iwai 已提交
1808 1809
	struct azx *chip = apcm->chip;
	struct snd_pcm_runtime *runtime = substream->runtime;
L
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1810 1811 1812 1813 1814 1815
	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];

	/* reset BDL address */
	azx_sd_writel(azx_dev, SD_BDLPL, 0);
	azx_sd_writel(azx_dev, SD_BDLPU, 0);
	azx_sd_writel(azx_dev, SD_CTL, 0);
1816 1817 1818
	azx_dev->bufsize = 0;
	azx_dev->period_bytes = 0;
	azx_dev->format_val = 0;
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1819

1820
	snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
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1821

T
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1822
	mark_runtime_wc(chip, azx_dev, runtime, false);
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1823 1824 1825
	return snd_pcm_lib_free_pages(substream);
}

1826
static int azx_pcm_prepare(struct snd_pcm_substream *substream)
L
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1827 1828
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1829 1830
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);
L
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1831
	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1832
	struct snd_pcm_runtime *runtime = substream->runtime;
1833
	unsigned int bufsize, period_bytes, format_val, stream_tag;
1834
	int err;
1835 1836 1837
	struct hda_spdif_out *spdif =
		snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
	unsigned short ctls = spdif ? spdif->ctls : 0;
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1838

1839
	azx_stream_reset(chip, azx_dev);
1840 1841 1842
	format_val = snd_hda_calc_stream_format(runtime->rate,
						runtime->channels,
						runtime->format,
1843
						hinfo->maxbps,
1844
						ctls);
1845
	if (!format_val) {
1846 1847
		snd_printk(KERN_ERR SFX
			   "invalid format_val, rate=%d, ch=%d, format=%d\n",
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1848 1849 1850 1851
			   runtime->rate, runtime->channels, runtime->format);
		return -EINVAL;
	}

1852 1853 1854
	bufsize = snd_pcm_lib_buffer_bytes(substream);
	period_bytes = snd_pcm_lib_period_bytes(substream);

1855
	snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868
		    bufsize, format_val);

	if (bufsize != azx_dev->bufsize ||
	    period_bytes != azx_dev->period_bytes ||
	    format_val != azx_dev->format_val) {
		azx_dev->bufsize = bufsize;
		azx_dev->period_bytes = period_bytes;
		azx_dev->format_val = format_val;
		err = azx_setup_periods(chip, substream, azx_dev);
		if (err < 0)
			return err;
	}

1869 1870 1871
	/* wallclk has 24Mhz clock source */
	azx_dev->period_wallclk = (((runtime->period_size * 24000) /
						runtime->rate) * 1000);
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1872 1873 1874 1875 1876 1877
	azx_setup_controller(chip, azx_dev);
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
	else
		azx_dev->fifo_size = 0;

1878 1879
	stream_tag = azx_dev->stream_tag;
	/* CA-IBG chips need the playback stream starting from 1 */
1880
	if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1881 1882 1883
	    stream_tag > chip->capture_streams)
		stream_tag -= chip->capture_streams;
	return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1884
				     azx_dev->format_val, substream);
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1885 1886
}

1887
static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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1888 1889
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1890
	struct azx *chip = apcm->chip;
1891 1892
	struct azx_dev *azx_dev;
	struct snd_pcm_substream *s;
1893
	int rstart = 0, start, nsync = 0, sbits = 0;
1894
	int nwait, timeout;
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1895 1896

	switch (cmd) {
1897 1898
	case SNDRV_PCM_TRIGGER_START:
		rstart = 1;
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1899 1900
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
1901
		start = 1;
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1902 1903
		break;
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1904
	case SNDRV_PCM_TRIGGER_SUSPEND:
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1905
	case SNDRV_PCM_TRIGGER_STOP:
1906
		start = 0;
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1907 1908
		break;
	default:
1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923
		return -EINVAL;
	}

	snd_pcm_group_for_each_entry(s, substream) {
		if (s->pcm->card != substream->pcm->card)
			continue;
		azx_dev = get_azx_dev(s);
		sbits |= 1 << azx_dev->index;
		nsync++;
		snd_pcm_trigger_done(s, substream);
	}

	spin_lock(&chip->reg_lock);
	if (nsync > 1) {
		/* first, set SYNC bits of corresponding streams */
1924 1925 1926 1927 1928
		if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
			azx_writel(chip, OLD_SSYNC,
				   azx_readl(chip, OLD_SSYNC) | sbits);
		else
			azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1929 1930 1931 1932 1933
	}
	snd_pcm_group_for_each_entry(s, substream) {
		if (s->pcm->card != substream->pcm->card)
			continue;
		azx_dev = get_azx_dev(s);
1934 1935 1936 1937 1938
		if (start) {
			azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
			if (!rstart)
				azx_dev->start_wallclk -=
						azx_dev->period_wallclk;
1939
			azx_stream_start(chip, azx_dev);
1940
		} else {
1941
			azx_stream_stop(chip, azx_dev);
1942
		}
1943
		azx_dev->running = start;
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1944 1945
	}
	spin_unlock(&chip->reg_lock);
1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979
	if (start) {
		if (nsync == 1)
			return 0;
		/* wait until all FIFOs get ready */
		for (timeout = 5000; timeout; timeout--) {
			nwait = 0;
			snd_pcm_group_for_each_entry(s, substream) {
				if (s->pcm->card != substream->pcm->card)
					continue;
				azx_dev = get_azx_dev(s);
				if (!(azx_sd_readb(azx_dev, SD_STS) &
				      SD_STS_FIFO_READY))
					nwait++;
			}
			if (!nwait)
				break;
			cpu_relax();
		}
	} else {
		/* wait until all RUN bits are cleared */
		for (timeout = 5000; timeout; timeout--) {
			nwait = 0;
			snd_pcm_group_for_each_entry(s, substream) {
				if (s->pcm->card != substream->pcm->card)
					continue;
				azx_dev = get_azx_dev(s);
				if (azx_sd_readb(azx_dev, SD_CTL) &
				    SD_CTL_DMA_START)
					nwait++;
			}
			if (!nwait)
				break;
			cpu_relax();
		}
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	}
1981 1982 1983
	if (nsync > 1) {
		spin_lock(&chip->reg_lock);
		/* reset SYNC bits */
1984 1985 1986 1987 1988
		if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
			azx_writel(chip, OLD_SSYNC,
				   azx_readl(chip, OLD_SSYNC) & ~sbits);
		else
			azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1989 1990 1991
		spin_unlock(&chip->reg_lock);
	}
	return 0;
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}

1994 1995 1996 1997 1998 1999 2000 2001 2002
/* get the current DMA position with correction on VIA chips */
static unsigned int azx_via_get_position(struct azx *chip,
					 struct azx_dev *azx_dev)
{
	unsigned int link_pos, mini_pos, bound_pos;
	unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
	unsigned int fifo_size;

	link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2003
	if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049
		/* Playback, no problem using link position */
		return link_pos;
	}

	/* Capture */
	/* For new chipset,
	 * use mod to get the DMA position just like old chipset
	 */
	mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
	mod_dma_pos %= azx_dev->period_bytes;

	/* azx_dev->fifo_size can't get FIFO size of in stream.
	 * Get from base address + offset.
	 */
	fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);

	if (azx_dev->insufficient) {
		/* Link position never gather than FIFO size */
		if (link_pos <= fifo_size)
			return 0;

		azx_dev->insufficient = 0;
	}

	if (link_pos <= fifo_size)
		mini_pos = azx_dev->bufsize + link_pos - fifo_size;
	else
		mini_pos = link_pos - fifo_size;

	/* Find nearest previous boudary */
	mod_mini_pos = mini_pos % azx_dev->period_bytes;
	mod_link_pos = link_pos % azx_dev->period_bytes;
	if (mod_link_pos >= fifo_size)
		bound_pos = link_pos - mod_link_pos;
	else if (mod_dma_pos >= mod_mini_pos)
		bound_pos = mini_pos - mod_mini_pos;
	else {
		bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
		if (bound_pos >= azx_dev->bufsize)
			bound_pos = 0;
	}

	/* Calculate real DMA position we want */
	return bound_pos + mod_dma_pos;
}

2050
static unsigned int azx_get_position(struct azx *chip,
2051 2052
				     struct azx_dev *azx_dev,
				     bool with_check)
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{
	unsigned int pos;
2055
	int stream = azx_dev->substream->stream;
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2057 2058 2059 2060 2061 2062
	switch (chip->position_fix[stream]) {
	case POS_FIX_LPIB:
		/* read LPIB */
		pos = azx_sd_readl(azx_dev, SD_LPIB);
		break;
	case POS_FIX_VIACOMBO:
2063
		pos = azx_via_get_position(chip, azx_dev);
2064 2065 2066 2067
		break;
	default:
		/* use the position buffer */
		pos = le32_to_cpu(*azx_dev->posbuf);
2068
		if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2069 2070 2071 2072 2073 2074 2075 2076 2077 2078
			if (!pos || pos == (u32)-1) {
				printk(KERN_WARNING
				       "hda-intel: Invalid position buffer, "
				       "using LPIB read method instead.\n");
				chip->position_fix[stream] = POS_FIX_LPIB;
				pos = azx_sd_readl(azx_dev, SD_LPIB);
			} else
				chip->position_fix[stream] = POS_FIX_POSBUF;
		}
		break;
2079
	}
2080

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	if (pos >= azx_dev->bufsize)
		pos = 0;
2083 2084 2085 2086 2087 2088 2089 2090 2091
	return pos;
}

static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);
	return bytes_to_frames(substream->runtime,
2092
			       azx_get_position(chip, azx_dev, false));
2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105
}

/*
 * Check whether the current DMA position is acceptable for updating
 * periods.  Returns non-zero if it's OK.
 *
 * Many HD-audio controllers appear pretty inaccurate about
 * the update-IRQ timing.  The IRQ is issued before actually the
 * data is processed.  So, we need to process it afterwords in a
 * workqueue.
 */
static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
{
2106
	u32 wallclk;
2107
	unsigned int pos;
2108
	int stream;
2109

2110 2111
	wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
	if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2112 2113
		return -1;	/* bogus (too early) interrupt */

2114
	stream = azx_dev->substream->stream;
2115
	pos = azx_get_position(chip, azx_dev, true);
2116

2117 2118
	if (WARN_ONCE(!azx_dev->period_bytes,
		      "hda-intel: zero azx_dev->period_bytes"))
2119
		return -1; /* this shouldn't happen! */
2120
	if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2121 2122 2123
	    pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
		/* NG - it's below the first next period boundary */
		return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2124
	azx_dev->start_wallclk += wallclk;
2125 2126 2127 2128 2129 2130 2131 2132 2133
	return 1; /* OK, it's fine */
}

/*
 * The work for pending PCM period updates.
 */
static void azx_irq_pending_work(struct work_struct *work)
{
	struct azx *chip = container_of(work, struct azx, irq_pending_work);
2134
	int i, pending, ok;
2135

2136 2137 2138 2139 2140 2141 2142 2143
	if (!chip->irq_pending_warned) {
		printk(KERN_WARNING
		       "hda-intel: IRQ timing workaround is activated "
		       "for card #%d. Suggest a bigger bdl_pos_adj.\n",
		       chip->card->number);
		chip->irq_pending_warned = 1;
	}

2144 2145 2146 2147 2148 2149 2150 2151 2152
	for (;;) {
		pending = 0;
		spin_lock_irq(&chip->reg_lock);
		for (i = 0; i < chip->num_streams; i++) {
			struct azx_dev *azx_dev = &chip->azx_dev[i];
			if (!azx_dev->irq_pending ||
			    !azx_dev->substream ||
			    !azx_dev->running)
				continue;
2153 2154
			ok = azx_position_ok(chip, azx_dev);
			if (ok > 0) {
2155 2156 2157 2158
				azx_dev->irq_pending = 0;
				spin_unlock(&chip->reg_lock);
				snd_pcm_period_elapsed(azx_dev->substream);
				spin_lock(&chip->reg_lock);
2159 2160
			} else if (ok < 0) {
				pending = 0;	/* too early */
2161 2162 2163 2164 2165 2166
			} else
				pending++;
		}
		spin_unlock_irq(&chip->reg_lock);
		if (!pending)
			return;
2167
		msleep(1);
2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179
	}
}

/* clear irq_pending flags and assure no on-going workq */
static void azx_clear_irq_pending(struct azx *chip)
{
	int i;

	spin_lock_irq(&chip->reg_lock);
	for (i = 0; i < chip->num_streams; i++)
		chip->azx_dev[i].irq_pending = 0;
	spin_unlock_irq(&chip->reg_lock);
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}

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#ifdef CONFIG_X86
static int azx_pcm_mmap(struct snd_pcm_substream *substream,
			struct vm_area_struct *area)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
	if (!azx_snoop(chip))
		area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
	return snd_pcm_lib_default_mmap(substream, area);
}
#else
#define azx_pcm_mmap	NULL
#endif

2196
static struct snd_pcm_ops azx_pcm_ops = {
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	.open = azx_pcm_open,
	.close = azx_pcm_close,
	.ioctl = snd_pcm_lib_ioctl,
	.hw_params = azx_pcm_hw_params,
	.hw_free = azx_pcm_hw_free,
	.prepare = azx_pcm_prepare,
	.trigger = azx_pcm_trigger,
	.pointer = azx_pcm_pointer,
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	.mmap = azx_pcm_mmap,
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	.page = snd_pcm_sgbuf_ops_page,
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};

2209
static void azx_pcm_free(struct snd_pcm *pcm)
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2210
{
2211 2212
	struct azx_pcm *apcm = pcm->private_data;
	if (apcm) {
2213
		list_del(&apcm->list);
2214 2215
		kfree(apcm);
	}
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}

2218 2219
#define MAX_PREALLOC_SIZE	(32 * 1024 * 1024)

2220
static int
2221 2222
azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
		      struct hda_pcm *cpcm)
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{
2224
	struct azx *chip = bus->private_data;
2225
	struct snd_pcm *pcm;
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	struct azx_pcm *apcm;
2227
	int pcm_dev = cpcm->device;
2228
	unsigned int size;
2229
	int s, err;
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2231 2232 2233 2234 2235
	list_for_each_entry(apcm, &chip->pcm_list, list) {
		if (apcm->pcm->device == pcm_dev) {
			snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
			return -EBUSY;
		}
2236 2237 2238 2239
	}
	err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
			  cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
			  cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
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2240 2241 2242
			  &pcm);
	if (err < 0)
		return err;
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	strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2244
	apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
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2245 2246 2247
	if (apcm == NULL)
		return -ENOMEM;
	apcm->chip = chip;
2248
	apcm->pcm = pcm;
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	apcm->codec = codec;
	pcm->private_data = apcm;
	pcm->private_free = azx_pcm_free;
2252 2253
	if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
		pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2254
	list_add_tail(&apcm->list, &chip->pcm_list);
2255 2256 2257 2258 2259 2260 2261
	cpcm->pcm = pcm;
	for (s = 0; s < 2; s++) {
		apcm->hinfo[s] = &cpcm->stream[s];
		if (cpcm->stream[s].substreams)
			snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
	}
	/* buffer pre-allocation */
2262 2263 2264
	size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
	if (size > MAX_PREALLOC_SIZE)
		size = MAX_PREALLOC_SIZE;
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	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
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					      snd_dma_pci_data(chip->pci),
2267
					      size, MAX_PREALLOC_SIZE);
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2268 2269 2270 2271 2272 2273
	return 0;
}

/*
 * mixer creation - all stuff is implemented in hda module
 */
2274
static int __devinit azx_mixer_create(struct azx *chip)
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2275 2276 2277 2278 2279 2280 2281 2282
{
	return snd_hda_build_controls(chip->bus);
}


/*
 * initialize SD streams
 */
2283
static int __devinit azx_init_stream(struct azx *chip)
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2284 2285 2286 2287
{
	int i;

	/* initialize each stream (aka device)
2288 2289
	 * assign the starting bdl address to each stream (device)
	 * and initialize
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	 */
2291
	for (i = 0; i < chip->num_streams; i++) {
2292
		struct azx_dev *azx_dev = &chip->azx_dev[i];
2293
		azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
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2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305
		/* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
		azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
		/* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
		azx_dev->sd_int_sta_mask = 1 << i;
		/* stream tag: must be non-zero and unique */
		azx_dev->index = i;
		azx_dev->stream_tag = i + 1;
	}

	return 0;
}

2306 2307
static int azx_acquire_irq(struct azx *chip, int do_disconnect)
{
2308 2309
	if (request_irq(chip->pci->irq, azx_interrupt,
			chip->msi ? 0 : IRQF_SHARED,
2310
			KBUILD_MODNAME, chip)) {
2311 2312 2313 2314 2315 2316 2317
		printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
		       "disabling device\n", chip->pci->irq);
		if (do_disconnect)
			snd_card_disconnect(chip->card);
		return -1;
	}
	chip->irq = chip->pci->irq;
2318
	pci_intx(chip->pci, !chip->msi);
2319 2320 2321
	return 0;
}

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2323 2324
static void azx_stop_chip(struct azx *chip)
{
2325
	if (!chip->initialized)
2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343
		return;

	/* disable interrupts */
	azx_int_disable(chip);
	azx_int_clear(chip);

	/* disable CORB/RIRB */
	azx_free_cmd_io(chip);

	/* disable position buffer */
	azx_writel(chip, DPLBASE, 0);
	azx_writel(chip, DPUBASE, 0);

	chip->initialized = 0;
}

#ifdef CONFIG_SND_HDA_POWER_SAVE
/* power-up/down the controller */
2344
static void azx_power_notify(struct hda_bus *bus)
2345
{
2346
	struct azx *chip = bus->private_data;
2347 2348 2349
	struct hda_codec *c;
	int power_on = 0;

2350
	list_for_each_entry(c, &bus->codec_list, list) {
2351 2352 2353 2354 2355 2356
		if (c->power_on) {
			power_on = 1;
			break;
		}
	}
	if (power_on)
2357
		azx_init_chip(chip, 1);
W
Wu Fengguang 已提交
2358 2359
	else if (chip->running && power_save_controller &&
		 !bus->power_keep_link_on)
2360 2361
		azx_stop_chip(chip);
}
2362 2363 2364 2365 2366 2367
#endif /* CONFIG_SND_HDA_POWER_SAVE */

#ifdef CONFIG_PM
/*
 * power management
 */
2368

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static int azx_suspend(struct pci_dev *pci, pm_message_t state)
L
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2370
{
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2371 2372
	struct snd_card *card = pci_get_drvdata(pci);
	struct azx *chip = card->private_data;
2373
	struct azx_pcm *p;
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2375
	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2376
	azx_clear_irq_pending(chip);
2377 2378
	list_for_each_entry(p, &chip->pcm_list, list)
		snd_pcm_suspend_all(p->pcm);
2379
	if (chip->initialized)
2380
		snd_hda_suspend(chip->bus);
2381
	azx_stop_chip(chip);
2382
	if (chip->irq >= 0) {
2383
		free_irq(chip->irq, chip);
2384 2385
		chip->irq = -1;
	}
2386
	if (chip->msi)
2387
		pci_disable_msi(chip->pci);
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	pci_disable_device(pci);
	pci_save_state(pci);
2390
	pci_set_power_state(pci, pci_choose_state(pci, state));
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2391 2392 2393
	return 0;
}

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static int azx_resume(struct pci_dev *pci)
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2395
{
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2396 2397
	struct snd_card *card = pci_get_drvdata(pci);
	struct azx *chip = card->private_data;
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2398

2399 2400
	pci_set_power_state(pci, PCI_D0);
	pci_restore_state(pci);
2401 2402 2403 2404 2405 2406 2407
	if (pci_enable_device(pci) < 0) {
		printk(KERN_ERR "hda-intel: pci_enable_device failed, "
		       "disabling device\n");
		snd_card_disconnect(card);
		return -EIO;
	}
	pci_set_master(pci);
2408 2409 2410 2411
	if (chip->msi)
		if (pci_enable_msi(pci) < 0)
			chip->msi = 0;
	if (azx_acquire_irq(chip, 1) < 0)
2412
		return -EIO;
2413
	azx_init_pci(chip);
2414

2415
	azx_init_chip(chip, 1);
2416

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2417
	snd_hda_resume(chip->bus);
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2418
	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
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2419 2420 2421 2422 2423
	return 0;
}
#endif /* CONFIG_PM */


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/*
 * reboot notifier for hang-up problem at power-down
 */
static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
{
	struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2430
	snd_hda_bus_reboot_notify(chip->bus);
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	azx_stop_chip(chip);
	return NOTIFY_OK;
}

static void azx_notifier_register(struct azx *chip)
{
	chip->reboot_notifier.notifier_call = azx_halt;
	register_reboot_notifier(&chip->reboot_notifier);
}

static void azx_notifier_unregister(struct azx *chip)
{
	if (chip->reboot_notifier.notifier_call)
		unregister_reboot_notifier(&chip->reboot_notifier);
}

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/*
 * destructor
 */
2450
static int azx_free(struct azx *chip)
L
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2451
{
T
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2452 2453
	int i;

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2454 2455
	azx_notifier_unregister(chip);

2456
	if (chip->initialized) {
2457
		azx_clear_irq_pending(chip);
2458
		for (i = 0; i < chip->num_streams; i++)
L
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			azx_stream_stop(chip, &chip->azx_dev[i]);
2460
		azx_stop_chip(chip);
L
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2461 2462
	}

2463
	if (chip->irq >= 0)
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2464
		free_irq(chip->irq, (void*)chip);
2465
	if (chip->msi)
2466
		pci_disable_msi(chip->pci);
2467 2468
	if (chip->remap_addr)
		iounmap(chip->remap_addr);
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2470 2471
	if (chip->azx_dev) {
		for (i = 0; i < chip->num_streams; i++)
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2472 2473
			if (chip->azx_dev[i].bdl.area) {
				mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
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Takashi Iwai 已提交
2474
				snd_dma_free_pages(&chip->azx_dev[i].bdl);
T
Takashi Iwai 已提交
2475
			}
T
Takashi Iwai 已提交
2476
	}
T
Takashi Iwai 已提交
2477 2478
	if (chip->rb.area) {
		mark_pages_wc(chip, &chip->rb, false);
L
Linus Torvalds 已提交
2479
		snd_dma_free_pages(&chip->rb);
T
Takashi Iwai 已提交
2480 2481 2482
	}
	if (chip->posbuf.area) {
		mark_pages_wc(chip, &chip->posbuf, false);
L
Linus Torvalds 已提交
2483
		snd_dma_free_pages(&chip->posbuf);
T
Takashi Iwai 已提交
2484
	}
L
Linus Torvalds 已提交
2485 2486
	pci_release_regions(chip->pci);
	pci_disable_device(chip->pci);
2487
	kfree(chip->azx_dev);
L
Linus Torvalds 已提交
2488 2489 2490 2491 2492
	kfree(chip);

	return 0;
}

2493
static int azx_dev_free(struct snd_device *device)
L
Linus Torvalds 已提交
2494 2495 2496 2497
{
	return azx_free(device->device_data);
}

2498 2499 2500
/*
 * white/black-listing for position_fix
 */
R
Ralf Baechle 已提交
2501
static struct snd_pci_quirk position_fix_list[] __devinitdata = {
T
Takashi Iwai 已提交
2502 2503
	SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
	SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2504
	SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
T
Takashi Iwai 已提交
2505
	SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2506
	SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
D
Daniel T Chen 已提交
2507
	SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2508
	SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2509
	SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2510
	SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2511
	SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2512
	SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2513
	SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2514
	SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2515
	SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2516 2517 2518 2519 2520 2521 2522
	{}
};

static int __devinit check_position_fix(struct azx *chip, int fix)
{
	const struct snd_pci_quirk *q;

2523 2524 2525
	switch (fix) {
	case POS_FIX_LPIB:
	case POS_FIX_POSBUF:
2526
	case POS_FIX_VIACOMBO:
2527
	case POS_FIX_COMBO:
2528 2529 2530 2531 2532 2533 2534 2535 2536 2537
		return fix;
	}

	q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
	if (q) {
		printk(KERN_INFO
		       "hda_intel: position_fix set to %d "
		       "for device %04x:%04x\n",
		       q->value, q->subvendor, q->subdevice);
		return q->value;
2538
	}
2539 2540

	/* Check VIA/ATI HD Audio Controller exist */
2541 2542
	if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
		snd_printd(SFX "Using VIACOMBO position fix\n");
2543
		return POS_FIX_VIACOMBO;
2544 2545 2546
	}
	if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
		snd_printd(SFX "Using LPIB position fix\n");
2547
		return POS_FIX_LPIB;
2548
	}
2549
	return POS_FIX_AUTO;
2550 2551
}

2552 2553 2554 2555 2556 2557 2558 2559 2560 2561
/*
 * black-lists for probe_mask
 */
static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
	/* Thinkpad often breaks the controller communication when accessing
	 * to the non-working (or non-existing) modem codec slot.
	 */
	SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
	SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
	SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2562 2563
	/* broken BIOS */
	SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2564 2565
	/* including bogus ALC268 in slot#2 that conflicts with ALC888 */
	SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2566
	/* forced codec slots */
2567
	SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2568
	SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2569 2570 2571
	{}
};

2572 2573
#define AZX_FORCE_CODEC_MASK	0x100

2574
static void __devinit check_probe_mask(struct azx *chip, int dev)
2575 2576 2577
{
	const struct snd_pci_quirk *q;

2578 2579
	chip->codec_probe_mask = probe_mask[dev];
	if (chip->codec_probe_mask == -1) {
2580 2581 2582 2583 2584 2585
		q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
		if (q) {
			printk(KERN_INFO
			       "hda_intel: probe_mask set to 0x%x "
			       "for device %04x:%04x\n",
			       q->value, q->subvendor, q->subdevice);
2586
			chip->codec_probe_mask = q->value;
2587 2588
		}
	}
2589 2590 2591 2592 2593 2594 2595 2596

	/* check forced option */
	if (chip->codec_probe_mask != -1 &&
	    (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
		chip->codec_mask = chip->codec_probe_mask & 0xff;
		printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
		       chip->codec_mask);
	}
2597 2598
}

2599
/*
T
Takashi Iwai 已提交
2600
 * white/black-list for enable_msi
2601
 */
T
Takashi Iwai 已提交
2602
static struct snd_pci_quirk msi_black_list[] __devinitdata = {
T
Takashi Iwai 已提交
2603
	SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2604
	SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2605
	SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2606
	SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2607
	SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2608 2609 2610 2611 2612 2613 2614
	{}
};

static void __devinit check_msi(struct azx *chip)
{
	const struct snd_pci_quirk *q;

T
Takashi Iwai 已提交
2615 2616
	if (enable_msi >= 0) {
		chip->msi = !!enable_msi;
2617
		return;
T
Takashi Iwai 已提交
2618 2619 2620
	}
	chip->msi = 1;	/* enable MSI as default */
	q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2621 2622 2623 2624 2625
	if (q) {
		printk(KERN_INFO
		       "hda_intel: msi for device %04x:%04x set to %d\n",
		       q->subvendor, q->subdevice, q->value);
		chip->msi = q->value;
2626 2627 2628 2629
		return;
	}

	/* NVidia chipsets seem to cause troubles with MSI */
2630 2631
	if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
		printk(KERN_INFO "hda_intel: Disabling MSI\n");
2632
		chip->msi = 0;
2633 2634 2635
	}
}

2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664
/* check the snoop mode availability */
static void __devinit azx_check_snoop_available(struct azx *chip)
{
	bool snoop = chip->snoop;

	switch (chip->driver_type) {
	case AZX_DRIVER_VIA:
		/* force to non-snoop mode for a new VIA controller
		 * when BIOS is set
		 */
		if (snoop) {
			u8 val;
			pci_read_config_byte(chip->pci, 0x42, &val);
			if (!(val & 0x80) && chip->pci->revision == 0x30)
				snoop = false;
		}
		break;
	case AZX_DRIVER_ATIHDMI_NS:
		/* new ATI HDMI requires non-snoop */
		snoop = false;
		break;
	}

	if (snoop != chip->snoop) {
		snd_printk(KERN_INFO SFX "Force to %s mode\n",
			   snoop ? "snoop" : "non-snoop");
		chip->snoop = snoop;
	}
}
2665

L
Linus Torvalds 已提交
2666 2667 2668
/*
 * constructor
 */
2669
static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2670
				int dev, unsigned int driver_caps,
2671
				struct azx **rchip)
L
Linus Torvalds 已提交
2672
{
2673
	struct azx *chip;
T
Takashi Iwai 已提交
2674
	int i, err;
2675
	unsigned short gcap;
2676
	static struct snd_device_ops ops = {
L
Linus Torvalds 已提交
2677 2678 2679 2680
		.dev_free = azx_dev_free,
	};

	*rchip = NULL;
2681

2682 2683
	err = pci_enable_device(pci);
	if (err < 0)
L
Linus Torvalds 已提交
2684 2685
		return err;

2686
	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2687
	if (!chip) {
L
Linus Torvalds 已提交
2688 2689 2690 2691 2692 2693
		snd_printk(KERN_ERR SFX "cannot allocate chip\n");
		pci_disable_device(pci);
		return -ENOMEM;
	}

	spin_lock_init(&chip->reg_lock);
2694
	mutex_init(&chip->open_mutex);
L
Linus Torvalds 已提交
2695 2696 2697
	chip->card = card;
	chip->pci = pci;
	chip->irq = -1;
2698 2699
	chip->driver_caps = driver_caps;
	chip->driver_type = driver_caps & 0xff;
2700
	check_msi(chip);
2701
	chip->dev_index = dev;
2702
	INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2703
	INIT_LIST_HEAD(&chip->pcm_list);
L
Linus Torvalds 已提交
2704

2705 2706
	chip->position_fix[0] = chip->position_fix[1] =
		check_position_fix(chip, position_fix[dev]);
2707 2708 2709 2710 2711 2712
	/* combo mode uses LPIB for playback */
	if (chip->position_fix[0] == POS_FIX_COMBO) {
		chip->position_fix[0] = POS_FIX_LPIB;
		chip->position_fix[1] = POS_FIX_AUTO;
	}

2713
	check_probe_mask(chip, dev);
2714

2715
	chip->single_cmd = single_cmd;
T
Takashi Iwai 已提交
2716
	chip->snoop = hda_snoop;
2717
	azx_check_snoop_available(chip);
2718

2719 2720
	if (bdl_pos_adj[dev] < 0) {
		switch (chip->driver_type) {
2721
		case AZX_DRIVER_ICH:
2722
		case AZX_DRIVER_PCH:
2723
			bdl_pos_adj[dev] = 1;
2724 2725
			break;
		default:
2726
			bdl_pos_adj[dev] = 32;
2727 2728 2729 2730
			break;
		}
	}

2731 2732 2733 2734 2735 2736 2737 2738 2739 2740
#if BITS_PER_LONG != 64
	/* Fix up base address on ULI M5461 */
	if (chip->driver_type == AZX_DRIVER_ULI) {
		u16 tmp3;
		pci_read_config_word(pci, 0x40, &tmp3);
		pci_write_config_word(pci, 0x40, tmp3 | 0x10);
		pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
	}
#endif

2741 2742
	err = pci_request_regions(pci, "ICH HD audio");
	if (err < 0) {
L
Linus Torvalds 已提交
2743 2744 2745 2746 2747
		kfree(chip);
		pci_disable_device(pci);
		return err;
	}

2748
	chip->addr = pci_resource_start(pci, 0);
2749
	chip->remap_addr = pci_ioremap_bar(pci, 0);
L
Linus Torvalds 已提交
2750 2751 2752 2753 2754 2755
	if (chip->remap_addr == NULL) {
		snd_printk(KERN_ERR SFX "ioremap error\n");
		err = -ENXIO;
		goto errout;
	}

2756 2757 2758
	if (chip->msi)
		if (pci_enable_msi(pci) < 0)
			chip->msi = 0;
2759

2760
	if (azx_acquire_irq(chip, 0) < 0) {
L
Linus Torvalds 已提交
2761 2762 2763 2764 2765 2766 2767
		err = -EBUSY;
		goto errout;
	}

	pci_set_master(pci);
	synchronize_irq(chip->irq);

2768
	gcap = azx_readw(chip, GCAP);
2769
	snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2770

2771
	/* disable SB600 64bit support for safety */
2772
	if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2773 2774 2775 2776 2777 2778 2779 2780 2781 2782
		struct pci_dev *p_smbus;
		p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
					 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
					 NULL);
		if (p_smbus) {
			if (p_smbus->revision < 0x30)
				gcap &= ~ICH6_GCAP_64OK;
			pci_dev_put(p_smbus);
		}
	}
2783

2784 2785 2786
	/* disable 64bit DMA address on some devices */
	if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
		snd_printd(SFX "Disabling 64bit DMA\n");
2787
		gcap &= ~ICH6_GCAP_64OK;
2788
	}
2789

2790
	/* disable buffer size rounding to 128-byte multiples if supported */
2791 2792 2793 2794 2795 2796 2797 2798 2799 2800
	if (align_buffer_size >= 0)
		chip->align_buffer_size = !!align_buffer_size;
	else {
		if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
			chip->align_buffer_size = 0;
		else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
			chip->align_buffer_size = 1;
		else
			chip->align_buffer_size = 1;
	}
2801

2802
	/* allow 64bit DMA address if supported by H/W */
2803
	if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2804
		pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2805
	else {
2806 2807
		pci_set_dma_mask(pci, DMA_BIT_MASK(32));
		pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2808
	}
2809

2810 2811 2812 2813 2814 2815
	/* read number of streams from GCAP register instead of using
	 * hardcoded value
	 */
	chip->capture_streams = (gcap >> 8) & 0x0f;
	chip->playback_streams = (gcap >> 12) & 0x0f;
	if (!chip->playback_streams && !chip->capture_streams) {
2816 2817 2818 2819 2820 2821 2822 2823
		/* gcap didn't give any info, switching to old method */

		switch (chip->driver_type) {
		case AZX_DRIVER_ULI:
			chip->playback_streams = ULI_NUM_PLAYBACK;
			chip->capture_streams = ULI_NUM_CAPTURE;
			break;
		case AZX_DRIVER_ATIHDMI:
2824
		case AZX_DRIVER_ATIHDMI_NS:
2825 2826 2827
			chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
			chip->capture_streams = ATIHDMI_NUM_CAPTURE;
			break;
2828
		case AZX_DRIVER_GENERIC:
2829 2830 2831 2832 2833
		default:
			chip->playback_streams = ICH6_NUM_PLAYBACK;
			chip->capture_streams = ICH6_NUM_CAPTURE;
			break;
		}
2834
	}
2835 2836
	chip->capture_index_offset = 0;
	chip->playback_index_offset = chip->capture_streams;
2837
	chip->num_streams = chip->playback_streams + chip->capture_streams;
2838 2839
	chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
				GFP_KERNEL);
2840
	if (!chip->azx_dev) {
2841
		snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2842 2843 2844
		goto errout;
	}

T
Takashi Iwai 已提交
2845 2846 2847 2848 2849 2850 2851 2852 2853
	for (i = 0; i < chip->num_streams; i++) {
		/* allocate memory for the BDL for each stream */
		err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
					  snd_dma_pci_data(chip->pci),
					  BDL_SIZE, &chip->azx_dev[i].bdl);
		if (err < 0) {
			snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
			goto errout;
		}
T
Takashi Iwai 已提交
2854
		mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
L
Linus Torvalds 已提交
2855
	}
2856
	/* allocate memory for the position buffer */
2857 2858 2859 2860
	err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
				  snd_dma_pci_data(chip->pci),
				  chip->num_streams * 8, &chip->posbuf);
	if (err < 0) {
2861 2862
		snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
		goto errout;
L
Linus Torvalds 已提交
2863
	}
T
Takashi Iwai 已提交
2864
	mark_pages_wc(chip, &chip->posbuf, true);
L
Linus Torvalds 已提交
2865
	/* allocate CORB/RIRB */
2866 2867 2868
	err = azx_alloc_cmd_io(chip);
	if (err < 0)
		goto errout;
L
Linus Torvalds 已提交
2869 2870 2871 2872 2873

	/* initialize streams */
	azx_init_stream(chip);

	/* initialize chip */
2874
	azx_init_pci(chip);
2875
	azx_init_chip(chip, (probe_only[dev] & 2) == 0);
L
Linus Torvalds 已提交
2876 2877

	/* codec detection */
2878
	if (!chip->codec_mask) {
L
Linus Torvalds 已提交
2879 2880 2881 2882 2883
		snd_printk(KERN_ERR SFX "no codecs found!\n");
		err = -ENODEV;
		goto errout;
	}

2884 2885
	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
	if (err <0) {
L
Linus Torvalds 已提交
2886 2887 2888 2889
		snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
		goto errout;
	}

2890
	strcpy(card->driver, "HDA-Intel");
T
Takashi Iwai 已提交
2891 2892 2893 2894 2895
	strlcpy(card->shortname, driver_short_names[chip->driver_type],
		sizeof(card->shortname));
	snprintf(card->longname, sizeof(card->longname),
		 "%s at 0x%lx irq %i",
		 card->shortname, chip->addr, chip->irq);
2896

L
Linus Torvalds 已提交
2897 2898 2899 2900 2901 2902 2903 2904
	*rchip = chip;
	return 0;

 errout:
	azx_free(chip);
	return err;
}

2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917
static void power_down_all_codecs(struct azx *chip)
{
#ifdef CONFIG_SND_HDA_POWER_SAVE
	/* The codecs were powered up in snd_hda_codec_new().
	 * Now all initialization done, so turn them down if possible
	 */
	struct hda_codec *codec;
	list_for_each_entry(codec, &chip->bus->codec_list, list) {
		snd_hda_power_down(codec);
	}
#endif
}

2918 2919
static int __devinit azx_probe(struct pci_dev *pci,
			       const struct pci_device_id *pci_id)
L
Linus Torvalds 已提交
2920
{
2921
	static int dev;
2922 2923
	struct snd_card *card;
	struct azx *chip;
2924
	int err;
L
Linus Torvalds 已提交
2925

2926 2927 2928 2929 2930 2931 2932
	if (dev >= SNDRV_CARDS)
		return -ENODEV;
	if (!enable[dev]) {
		dev++;
		return -ENOENT;
	}

2933 2934
	err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
	if (err < 0) {
L
Linus Torvalds 已提交
2935
		snd_printk(KERN_ERR SFX "Error creating card!\n");
2936
		return err;
L
Linus Torvalds 已提交
2937 2938
	}

2939 2940 2941
	/* set this here since it's referred in snd_hda_load_patch() */
	snd_card_set_dev(card, &pci->dev);

2942
	err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
W
Wu Fengguang 已提交
2943 2944
	if (err < 0)
		goto out_free;
T
Takashi Iwai 已提交
2945
	card->private_data = chip;
L
Linus Torvalds 已提交
2946

2947 2948 2949 2950
#ifdef CONFIG_SND_HDA_INPUT_BEEP
	chip->beep_mode = beep_mode[dev];
#endif

L
Linus Torvalds 已提交
2951
	/* create codec instances */
2952
	err = azx_codec_create(chip, model[dev]);
W
Wu Fengguang 已提交
2953 2954
	if (err < 0)
		goto out_free;
2955
#ifdef CONFIG_SND_HDA_PATCH_LOADER
2956
	if (patch[dev] && *patch[dev]) {
2957 2958 2959 2960 2961 2962 2963
		snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
			   patch[dev]);
		err = snd_hda_load_patch(chip->bus, patch[dev]);
		if (err < 0)
			goto out_free;
	}
#endif
2964
	if ((probe_only[dev] & 1) == 0) {
2965 2966 2967 2968
		err = azx_codec_configure(chip);
		if (err < 0)
			goto out_free;
	}
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2969 2970

	/* create PCM streams */
2971
	err = snd_hda_build_pcms(chip->bus);
W
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2972 2973
	if (err < 0)
		goto out_free;
L
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2974 2975

	/* create mixer controls */
2976
	err = azx_mixer_create(chip);
W
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2977 2978
	if (err < 0)
		goto out_free;
L
Linus Torvalds 已提交
2979

2980
	err = snd_card_register(card);
W
Wu Fengguang 已提交
2981 2982
	if (err < 0)
		goto out_free;
L
Linus Torvalds 已提交
2983 2984

	pci_set_drvdata(pci, card);
2985 2986
	chip->running = 1;
	power_down_all_codecs(chip);
T
Takashi Iwai 已提交
2987
	azx_notifier_register(chip);
L
Linus Torvalds 已提交
2988

2989
	dev++;
L
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2990
	return err;
W
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2991 2992 2993
out_free:
	snd_card_free(card);
	return err;
L
Linus Torvalds 已提交
2994 2995 2996 2997 2998 2999 3000 3001 3002
}

static void __devexit azx_remove(struct pci_dev *pci)
{
	snd_card_free(pci_get_drvdata(pci));
	pci_set_drvdata(pci, NULL);
}

/* PCI IDs */
3003
static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3004
	/* CPT */
3005
	{ PCI_DEVICE(0x8086, 0x1c20),
3006 3007
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
	  AZX_DCAPS_BUFSIZE },
3008
	/* PBG */
3009
	{ PCI_DEVICE(0x8086, 0x1d20),
3010 3011
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
	  AZX_DCAPS_BUFSIZE},
3012
	/* Panther Point */
3013
	{ PCI_DEVICE(0x8086, 0x1e20),
3014
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3015 3016 3017 3018
	  AZX_DCAPS_BUFSIZE},
	/* Lynx Point */
	{ PCI_DEVICE(0x8086, 0x8c20),
	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3019
	  AZX_DCAPS_BUFSIZE},
3020
	/* SCH */
3021
	{ PCI_DEVICE(0x8086, 0x811b),
3022
	  .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3023
	  AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3024 3025
	{ PCI_DEVICE(0x8086, 0x080a),
	  .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3026
	  AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3027
	/* ICH */
3028
	{ PCI_DEVICE(0x8086, 0x2668),
3029 3030
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH6 */
3031
	{ PCI_DEVICE(0x8086, 0x27d8),
3032 3033
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH7 */
3034
	{ PCI_DEVICE(0x8086, 0x269a),
3035 3036
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ESB2 */
3037
	{ PCI_DEVICE(0x8086, 0x284b),
3038 3039
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH8 */
3040
	{ PCI_DEVICE(0x8086, 0x293e),
3041 3042
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH9 */
3043
	{ PCI_DEVICE(0x8086, 0x293f),
3044 3045
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH9 */
3046
	{ PCI_DEVICE(0x8086, 0x3a3e),
3047 3048
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH10 */
3049
	{ PCI_DEVICE(0x8086, 0x3a6e),
3050 3051
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
	  AZX_DCAPS_BUFSIZE },  /* ICH10 */
3052 3053 3054 3055
	/* Generic Intel */
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
	  .class_mask = 0xffffff,
3056
	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3057 3058 3059 3060 3061 3062 3063 3064
	/* ATI SB 450/600/700/800/900 */
	{ PCI_DEVICE(0x1002, 0x437b),
	  .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
	{ PCI_DEVICE(0x1002, 0x4383),
	  .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
	/* AMD Hudson */
	{ PCI_DEVICE(0x1022, 0x780d),
	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3065
	/* ATI HDMI */
3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093
	{ PCI_DEVICE(0x1002, 0x793b),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0x7919),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0x960f),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0x970f),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa00),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa08),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa10),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa18),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa20),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa28),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa30),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa38),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa40),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaa48),
	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3094 3095 3096 3097 3098 3099 3100 3101
	{ PCI_DEVICE(0x1002, 0x9902),
	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaaa0),
	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaaa8),
	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
	{ PCI_DEVICE(0x1002, 0xaab0),
	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3102
	/* VIA VT8251/VT8237A */
3103 3104
	{ PCI_DEVICE(0x1106, 0x3288),
	  .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3105 3106 3107 3108 3109
	/* SIS966 */
	{ PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
	/* ULI M5461 */
	{ PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
	/* NVIDIA MCP */
3110 3111 3112
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
	  .class_mask = 0xffffff,
3113
	  .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3114
	/* Teradici */
3115 3116
	{ PCI_DEVICE(0x6549, 0x1200),
	  .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3117
	/* Creative X-Fi (CA0110-IBG) */
3118 3119 3120 3121 3122
#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
	/* the following entry conflicts with snd-ctxfi driver,
	 * as ctxfi driver mutates from HD-audio to native mode with
	 * a special command sequence.
	 */
3123 3124 3125
	{ PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
	  .class_mask = 0xffffff,
3126
	  .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3127
	  AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3128 3129
#else
	/* this entry seems still valid -- i.e. without emu20kx chip */
3130 3131
	{ PCI_DEVICE(0x1102, 0x0009),
	  .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3132
	  AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3133
#endif
3134 3135 3136 3137 3138
	/* CTHDA chips */
	{ PCI_DEVICE(0x1102, 0x0010),
	  .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
	{ PCI_DEVICE(0x1102, 0x0012),
	  .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3139 3140
	/* Vortex86MX */
	{ PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3141 3142
	/* VMware HDAudio */
	{ PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3143
	/* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3144 3145 3146
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
	  .class_mask = 0xffffff,
3147
	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3148 3149 3150
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
	  .class_mask = 0xffffff,
3151
	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
L
Linus Torvalds 已提交
3152 3153 3154 3155 3156 3157
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, azx_ids);

/* pci_driver definition */
static struct pci_driver driver = {
3158
	.name = KBUILD_MODNAME,
L
Linus Torvalds 已提交
3159 3160 3161
	.id_table = azx_ids,
	.probe = azx_probe,
	.remove = __devexit_p(azx_remove),
T
Takashi Iwai 已提交
3162 3163 3164 3165
#ifdef CONFIG_PM
	.suspend = azx_suspend,
	.resume = azx_resume,
#endif
L
Linus Torvalds 已提交
3166 3167 3168 3169
};

static int __init alsa_card_azx_init(void)
{
3170
	return pci_register_driver(&driver);
L
Linus Torvalds 已提交
3171 3172 3173 3174 3175 3176 3177 3178 3179
}

static void __exit alsa_card_azx_exit(void)
{
	pci_unregister_driver(&driver);
}

module_init(alsa_card_azx_init)
module_exit(alsa_card_azx_exit)