acpi_lpss.c 18.1 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
/*
 * ACPI support for Intel Lynxpoint LPSS.
 *
 * Copyright (C) 2013, Intel Corporation
 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
 *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/platform_data/clk-lpss.h>
21
#include <linux/pm_runtime.h>
22
#include <linux/delay.h>
23 24 25 26 27

#include "internal.h"

ACPI_MODULE_NAME("acpi_lpss");

28 29 30 31
#ifdef CONFIG_X86_INTEL_LPSS

#define LPSS_ADDR(desc) ((unsigned long)&desc)

32
#define LPSS_CLK_SIZE	0x04
33 34 35
#define LPSS_LTR_SIZE	0x18

/* Offsets relative to LPSS_PRIVATE_OFFSET */
36
#define LPSS_CLK_DIVIDER_DEF_MASK	(BIT(1) | BIT(16))
37 38 39
#define LPSS_RESETS			0x04
#define LPSS_RESETS_RESET_FUNC		BIT(0)
#define LPSS_RESETS_RESET_APB		BIT(1)
40 41
#define LPSS_GENERAL			0x08
#define LPSS_GENERAL_LTR_MODE_SW	BIT(2)
42
#define LPSS_GENERAL_UART_RTS_OVRD	BIT(3)
43 44
#define LPSS_SW_LTR			0x10
#define LPSS_AUTO_LTR			0x14
45 46 47 48 49 50 51
#define LPSS_LTR_SNOOP_REQ		BIT(15)
#define LPSS_LTR_SNOOP_MASK		0x0000FFFF
#define LPSS_LTR_SNOOP_LAT_1US		0x800
#define LPSS_LTR_SNOOP_LAT_32US		0xC00
#define LPSS_LTR_SNOOP_LAT_SHIFT	5
#define LPSS_LTR_SNOOP_LAT_CUTOFF	3000
#define LPSS_LTR_MAX_VAL		0x3FF
52 53
#define LPSS_TX_INT			0x20
#define LPSS_TX_INT_MASK		BIT(1)
54

55 56
#define LPSS_PRV_REG_COUNT		9

57 58 59 60 61 62
struct lpss_shared_clock {
	const char *name;
	unsigned long rate;
	struct clk *clk;
};

63
struct lpss_private_data;
64 65 66

struct lpss_device_desc {
	bool clk_required;
67
	const char *clkdev_name;
68 69
	bool ltr_required;
	unsigned int prv_offset;
70
	size_t prv_size_override;
71
	bool clk_divider;
72
	bool clk_gate;
73
	bool save_ctx;
74
	struct lpss_shared_clock *shared_clock;
75
	void (*setup)(struct lpss_private_data *pdata);
76 77
};

78 79 80 81 82
static struct lpss_device_desc lpss_dma_desc = {
	.clk_required = true,
	.clkdev_name = "hclk",
};

83 84 85 86 87
struct lpss_private_data {
	void __iomem *mmio_base;
	resource_size_t mmio_size;
	struct clk *clk;
	const struct lpss_device_desc *dev_desc;
88
	u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
89 90
};

91 92
static void lpss_uart_setup(struct lpss_private_data *pdata)
{
93
	unsigned int offset;
94 95
	u32 reg;

96 97 98 99 100 101 102
	offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
	reg = readl(pdata->mmio_base + offset);
	writel(reg | LPSS_TX_INT_MASK, pdata->mmio_base + offset);

	offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
	reg = readl(pdata->mmio_base + offset);
	writel(reg | LPSS_GENERAL_UART_RTS_OVRD, pdata->mmio_base + offset);
103 104
}

105 106 107 108 109 110 111 112 113 114 115
static void lpss_i2c_setup(struct lpss_private_data *pdata)
{
	unsigned int offset;
	u32 val;

	offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
	val = readl(pdata->mmio_base + offset);
	val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
	writel(val, pdata->mmio_base + offset);
}

116 117 118 119 120 121 122 123
static struct lpss_device_desc wpt_dev_desc = {
	.clk_required = true,
	.prv_offset = 0x800,
	.ltr_required = true,
	.clk_divider = true,
	.clk_gate = true,
};

124
static struct lpss_device_desc lpt_dev_desc = {
125 126 127 128 129 130 131 132
	.clk_required = true,
	.prv_offset = 0x800,
	.ltr_required = true,
	.clk_divider = true,
	.clk_gate = true,
};

static struct lpss_device_desc lpt_i2c_dev_desc = {
133
	.clk_required = true,
134 135
	.prv_offset = 0x800,
	.ltr_required = true,
136
	.clk_gate = true,
137 138
};

139 140 141 142
static struct lpss_device_desc lpt_uart_dev_desc = {
	.clk_required = true,
	.prv_offset = 0x800,
	.ltr_required = true,
143
	.clk_divider = true,
144 145
	.clk_gate = true,
	.setup = lpss_uart_setup,
146 147 148 149
};

static struct lpss_device_desc lpt_sdio_dev_desc = {
	.prv_offset = 0x1000,
150
	.prv_size_override = 0x1018,
151
	.ltr_required = true,
152 153
};

154 155 156 157 158 159 160
static struct lpss_shared_clock pwm_clock = {
	.name = "pwm_clk",
	.rate = 25000000,
};

static struct lpss_device_desc byt_pwm_dev_desc = {
	.clk_required = true,
161
	.save_ctx = true,
162 163 164
	.shared_clock = &pwm_clock,
};

165 166 167
static struct lpss_device_desc byt_uart_dev_desc = {
	.clk_required = true,
	.prv_offset = 0x800,
168
	.clk_divider = true,
169
	.clk_gate = true,
170
	.save_ctx = true,
171
	.setup = lpss_uart_setup,
172 173 174 175 176
};

static struct lpss_device_desc byt_spi_dev_desc = {
	.clk_required = true,
	.prv_offset = 0x400,
177
	.clk_divider = true,
178
	.clk_gate = true,
179
	.save_ctx = true,
180 181 182 183 184 185 186 187 188 189 190 191 192 193
};

static struct lpss_device_desc byt_sdio_dev_desc = {
	.clk_required = true,
};

static struct lpss_shared_clock i2c_clock = {
	.name = "i2c_clk",
	.rate = 100000000,
};

static struct lpss_device_desc byt_i2c_dev_desc = {
	.clk_required = true,
	.prv_offset = 0x800,
194
	.save_ctx = true,
195
	.shared_clock = &i2c_clock,
196
	.setup = lpss_i2c_setup,
197 198
};

199 200 201 202 203 204
#else

#define LPSS_ADDR(desc) (0UL)

#endif /* CONFIG_X86_INTEL_LPSS */

205
static const struct acpi_device_id acpi_lpss_device_ids[] = {
206
	/* Generic LPSS devices */
207
	{ "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
208

209
	/* Lynxpoint LPSS devices */
210 211 212 213 214 215 216
	{ "INT33C0", LPSS_ADDR(lpt_dev_desc) },
	{ "INT33C1", LPSS_ADDR(lpt_dev_desc) },
	{ "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
	{ "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
	{ "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
	{ "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
	{ "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
217 218
	{ "INT33C7", },

219
	/* BayTrail LPSS devices */
220 221 222 223 224
	{ "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
	{ "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
	{ "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
	{ "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
	{ "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
225
	{ "INT33B2", },
226
	{ "INT33FC", },
227

228 229 230 231 232 233 234
	{ "INT3430", LPSS_ADDR(lpt_dev_desc) },
	{ "INT3431", LPSS_ADDR(lpt_dev_desc) },
	{ "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
	{ "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
	{ "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
	{ "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
	{ "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
235 236
	{ "INT3437", },

237 238
	{ "INT3438", LPSS_ADDR(wpt_dev_desc) },

239 240 241
	{ }
};

242 243
#ifdef CONFIG_X86_INTEL_LPSS

244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261
static int is_memory(struct acpi_resource *res, void *not_used)
{
	struct resource r;
	return !acpi_dev_resource_memory(res, &r);
}

/* LPSS main clock device. */
static struct platform_device *lpss_clk_dev;

static inline void lpt_register_clock_device(void)
{
	lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
}

static int register_device_clock(struct acpi_device *adev,
				 struct lpss_private_data *pdata)
{
	const struct lpss_device_desc *dev_desc = pdata->dev_desc;
262
	struct lpss_shared_clock *shared_clock = dev_desc->shared_clock;
263
	const char *devname = dev_name(&adev->dev);
264
	struct clk *clk = ERR_PTR(-ENODEV);
265
	struct lpss_clk_data *clk_data;
266 267
	const char *parent, *clk_name;
	void __iomem *prv_base;
268 269 270 271

	if (!lpss_clk_dev)
		lpt_register_clock_device();

272 273 274 275 276 277
	clk_data = platform_get_drvdata(lpss_clk_dev);
	if (!clk_data)
		return -ENODEV;

	if (dev_desc->clkdev_name) {
		clk_register_clkdev(clk_data->clk, dev_desc->clkdev_name,
278
				    devname);
279 280 281 282
		return 0;
	}

	if (!pdata->mmio_base
283
	    || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
284 285
		return -ENODATA;

286
	parent = clk_data->name;
287
	prv_base = pdata->mmio_base + dev_desc->prv_offset;
288 289 290 291 292 293 294 295 296 297 298 299 300

	if (shared_clock) {
		clk = shared_clock->clk;
		if (!clk) {
			clk = clk_register_fixed_rate(NULL, shared_clock->name,
						      "lpss_clk", 0,
						      shared_clock->rate);
			shared_clock->clk = clk;
		}
		parent = shared_clock->name;
	}

	if (dev_desc->clk_gate) {
301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328
		clk = clk_register_gate(NULL, devname, parent, 0,
					prv_base, 0, 0, NULL);
		parent = devname;
	}

	if (dev_desc->clk_divider) {
		/* Prevent division by zero */
		if (!readl(prv_base))
			writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);

		clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
		if (!clk_name)
			return -ENOMEM;
		clk = clk_register_fractional_divider(NULL, clk_name, parent,
						      0, prv_base,
						      1, 15, 16, 15, 0, NULL);
		parent = clk_name;

		clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
		if (!clk_name) {
			kfree(parent);
			return -ENOMEM;
		}
		clk = clk_register_gate(NULL, clk_name, parent,
					CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
					prv_base, 31, 0, NULL);
		kfree(parent);
		kfree(clk_name);
329
	}
330

331 332
	if (IS_ERR(clk))
		return PTR_ERR(clk);
333

334 335
	pdata->clk = clk;
	clk_register_clkdev(clk, NULL, devname);
336 337 338 339 340 341 342 343 344 345
	return 0;
}

static int acpi_lpss_create_device(struct acpi_device *adev,
				   const struct acpi_device_id *id)
{
	struct lpss_device_desc *dev_desc;
	struct lpss_private_data *pdata;
	struct resource_list_entry *rentry;
	struct list_head resource_list;
346
	struct platform_device *pdev;
347 348 349
	int ret;

	dev_desc = (struct lpss_device_desc *)id->driver_data;
350 351 352 353
	if (!dev_desc) {
		pdev = acpi_create_platform_device(adev);
		return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
	}
354 355 356 357 358 359 360 361 362 363 364
	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	INIT_LIST_HEAD(&resource_list);
	ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
	if (ret < 0)
		goto err_out;

	list_for_each_entry(rentry, &resource_list, node)
		if (resource_type(&rentry->res) == IORESOURCE_MEM) {
365 366 367 368
			if (dev_desc->prv_size_override)
				pdata->mmio_size = dev_desc->prv_size_override;
			else
				pdata->mmio_size = resource_size(&rentry->res);
369 370 371 372 373 374 375
			pdata->mmio_base = ioremap(rentry->res.start,
						   pdata->mmio_size);
			break;
		}

	acpi_dev_free_resource_list(&resource_list);

376 377
	pdata->dev_desc = dev_desc;

378 379 380
	if (dev_desc->clk_required) {
		ret = register_device_clock(adev, pdata);
		if (ret) {
381 382 383
			/* Skip the device, but continue the namespace scan. */
			ret = 0;
			goto err_out;
384 385 386
		}
	}

387 388 389 390 391 392 393 394 395 396 397 398
	/*
	 * This works around a known issue in ACPI tables where LPSS devices
	 * have _PS0 and _PS3 without _PSC (and no power resources), so
	 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
	 */
	ret = acpi_device_fix_up_power(adev);
	if (ret) {
		/* Skip the device, but continue the namespace scan. */
		ret = 0;
		goto err_out;
	}

399 400 401
	if (dev_desc->setup)
		dev_desc->setup(pdata);

402
	adev->driver_data = pdata;
403 404 405 406 407
	pdev = acpi_create_platform_device(adev);
	if (!IS_ERR_OR_NULL(pdev)) {
		device_enable_async_suspend(&pdev->dev);
		return 1;
	}
408

409
	ret = PTR_ERR(pdev);
410 411 412 413 414 415 416
	adev->driver_data = NULL;

 err_out:
	kfree(pdata);
	return ret;
}

417 418 419 420 421 422 423 424 425 426 427
static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
{
	return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
}

static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
			     unsigned int reg)
{
	writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
}

428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448
static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
{
	struct acpi_device *adev;
	struct lpss_private_data *pdata;
	unsigned long flags;
	int ret;

	ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
	if (WARN_ON(ret))
		return ret;

	spin_lock_irqsave(&dev->power.lock, flags);
	if (pm_runtime_suspended(dev)) {
		ret = -EAGAIN;
		goto out;
	}
	pdata = acpi_driver_data(adev);
	if (WARN_ON(!pdata || !pdata->mmio_base)) {
		ret = -ENODEV;
		goto out;
	}
449
	*val = __lpss_reg_read(pdata, reg);
450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501

 out:
	spin_unlock_irqrestore(&dev->power.lock, flags);
	return ret;
}

static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
			     char *buf)
{
	u32 ltr_value = 0;
	unsigned int reg;
	int ret;

	reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
	ret = lpss_reg_read(dev, reg, &ltr_value);
	if (ret)
		return ret;

	return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
}

static ssize_t lpss_ltr_mode_show(struct device *dev,
				  struct device_attribute *attr, char *buf)
{
	u32 ltr_mode = 0;
	char *outstr;
	int ret;

	ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
	if (ret)
		return ret;

	outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
	return sprintf(buf, "%s\n", outstr);
}

static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);

static struct attribute *lpss_attrs[] = {
	&dev_attr_auto_ltr.attr,
	&dev_attr_sw_ltr.attr,
	&dev_attr_ltr_mode.attr,
	NULL,
};

static struct attribute_group lpss_attr_group = {
	.attrs = lpss_attrs,
	.name = "lpss_ltr",
};

502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532
static void acpi_lpss_set_ltr(struct device *dev, s32 val)
{
	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
	u32 ltr_mode, ltr_val;

	ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
	if (val < 0) {
		if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
			ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
			__lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
		}
		return;
	}
	ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
	if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
		ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
		val = LPSS_LTR_MAX_VAL;
	} else if (val > LPSS_LTR_MAX_VAL) {
		ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
		val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
	} else {
		ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
	}
	ltr_val |= val;
	__lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
	if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
		ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
		__lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
	}
}

533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652
#ifdef CONFIG_PM
/**
 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 * @dev: LPSS device
 *
 * Most LPSS devices have private registers which may loose their context when
 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 * prv_reg_ctx array.
 */
static void acpi_lpss_save_ctx(struct device *dev)
{
	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
	unsigned int i;

	for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
		unsigned long offset = i * sizeof(u32);

		pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
		dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
			pdata->prv_reg_ctx[i], offset);
	}
}

/**
 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 * @dev: LPSS device
 *
 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 */
static void acpi_lpss_restore_ctx(struct device *dev)
{
	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
	unsigned int i;

	/*
	 * The following delay is needed or the subsequent write operations may
	 * fail. The LPSS devices are actually PCI devices and the PCI spec
	 * expects 10ms delay before the device can be accessed after D3 to D0
	 * transition.
	 */
	msleep(10);

	for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
		unsigned long offset = i * sizeof(u32);

		__lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
		dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
			pdata->prv_reg_ctx[i], offset);
	}
}

#ifdef CONFIG_PM_SLEEP
static int acpi_lpss_suspend_late(struct device *dev)
{
	int ret = pm_generic_suspend_late(dev);

	if (ret)
		return ret;

	acpi_lpss_save_ctx(dev);
	return acpi_dev_suspend_late(dev);
}

static int acpi_lpss_restore_early(struct device *dev)
{
	int ret = acpi_dev_resume_early(dev);

	if (ret)
		return ret;

	acpi_lpss_restore_ctx(dev);
	return pm_generic_resume_early(dev);
}
#endif /* CONFIG_PM_SLEEP */

#ifdef CONFIG_PM_RUNTIME
static int acpi_lpss_runtime_suspend(struct device *dev)
{
	int ret = pm_generic_runtime_suspend(dev);

	if (ret)
		return ret;

	acpi_lpss_save_ctx(dev);
	return acpi_dev_runtime_suspend(dev);
}

static int acpi_lpss_runtime_resume(struct device *dev)
{
	int ret = acpi_dev_runtime_resume(dev);

	if (ret)
		return ret;

	acpi_lpss_restore_ctx(dev);
	return pm_generic_runtime_resume(dev);
}
#endif /* CONFIG_PM_RUNTIME */
#endif /* CONFIG_PM */

static struct dev_pm_domain acpi_lpss_pm_domain = {
	.ops = {
#ifdef CONFIG_PM_SLEEP
		.suspend_late = acpi_lpss_suspend_late,
		.restore_early = acpi_lpss_restore_early,
		.prepare = acpi_subsys_prepare,
		.complete = acpi_subsys_complete,
		.suspend = acpi_subsys_suspend,
		.resume_early = acpi_subsys_resume_early,
		.freeze = acpi_subsys_freeze,
		.poweroff = acpi_subsys_suspend,
		.poweroff_late = acpi_subsys_suspend_late,
#endif
#ifdef CONFIG_PM_RUNTIME
		.runtime_suspend = acpi_lpss_runtime_suspend,
		.runtime_resume = acpi_lpss_runtime_resume,
#endif
	},
};

653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668
static int acpi_lpss_platform_notify(struct notifier_block *nb,
				     unsigned long action, void *data)
{
	struct platform_device *pdev = to_platform_device(data);
	struct lpss_private_data *pdata;
	struct acpi_device *adev;
	const struct acpi_device_id *id;

	id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
	if (!id || !id->driver_data)
		return 0;

	if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
		return 0;

	pdata = acpi_driver_data(adev);
669
	if (!pdata || !pdata->mmio_base)
670 671 672 673 674 675 676
		return 0;

	if (pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
		dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
		return 0;
	}

677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695
	switch (action) {
	case BUS_NOTIFY_BOUND_DRIVER:
		if (pdata->dev_desc->save_ctx)
			pdev->dev.pm_domain = &acpi_lpss_pm_domain;
		break;
	case BUS_NOTIFY_UNBOUND_DRIVER:
		if (pdata->dev_desc->save_ctx)
			pdev->dev.pm_domain = NULL;
		break;
	case BUS_NOTIFY_ADD_DEVICE:
		if (pdata->dev_desc->ltr_required)
			return sysfs_create_group(&pdev->dev.kobj,
						  &lpss_attr_group);
	case BUS_NOTIFY_DEL_DEVICE:
		if (pdata->dev_desc->ltr_required)
			sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
	default:
		break;
	}
696

697
	return 0;
698 699 700 701 702 703
}

static struct notifier_block acpi_lpss_nb = {
	.notifier_call = acpi_lpss_platform_notify,
};

704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721
static void acpi_lpss_bind(struct device *dev)
{
	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));

	if (!pdata || !pdata->mmio_base || !pdata->dev_desc->ltr_required)
		return;

	if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
		dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
	else
		dev_err(dev, "MMIO size insufficient to access LTR\n");
}

static void acpi_lpss_unbind(struct device *dev)
{
	dev->power.set_latency_tolerance = NULL;
}

722 723 724
static struct acpi_scan_handler lpss_handler = {
	.ids = acpi_lpss_device_ids,
	.attach = acpi_lpss_create_device,
725 726
	.bind = acpi_lpss_bind,
	.unbind = acpi_lpss_unbind,
727 728 729 730
};

void __init acpi_lpss_init(void)
{
731 732
	if (!lpt_clk_init()) {
		bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
733
		acpi_scan_add_handler(&lpss_handler);
734
	}
735
}
736 737 738 739 740 741 742 743 744 745 746 747 748

#else

static struct acpi_scan_handler lpss_handler = {
	.ids = acpi_lpss_device_ids,
};

void __init acpi_lpss_init(void)
{
	acpi_scan_add_handler(&lpss_handler);
}

#endif /* CONFIG_X86_INTEL_LPSS */