vmwgfx_irq.c 8.2 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
/**************************************************************************
 *
 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 **************************************************************************/

#include "drmP.h"
#include "vmwgfx_drv.h"

#define VMW_FENCE_WRAP (1 << 24)

irqreturn_t vmw_irq_handler(DRM_IRQ_ARGS)
{
	struct drm_device *dev = (struct drm_device *)arg;
	struct vmw_private *dev_priv = vmw_priv(dev);
	uint32_t status;

	spin_lock(&dev_priv->irq_lock);
	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
	spin_unlock(&dev_priv->irq_lock);

	if (status & SVGA_IRQFLAG_ANY_FENCE)
		wake_up_all(&dev_priv->fence_queue);
	if (status & SVGA_IRQFLAG_FIFO_PROGRESS)
		wake_up_all(&dev_priv->fifo_queue);

	if (likely(status)) {
		outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

56
static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno)
57 58 59 60 61 62 63 64 65 66
{
	uint32_t busy;

	mutex_lock(&dev_priv->hw_mutex);
	busy = vmw_read(dev_priv, SVGA_REG_BUSY);
	mutex_unlock(&dev_priv->hw_mutex);

	return (busy == 0);
}

67
void vmw_update_seqno(struct vmw_private *dev_priv,
68 69 70 71
			 struct vmw_fifo_state *fifo_state)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;

72
	uint32_t seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
73

74 75 76
	if (dev_priv->last_read_seqno != seqno) {
		dev_priv->last_read_seqno = seqno;
		vmw_marker_pull(&fifo_state->marker_queue, seqno);
77 78
	}
}
79

80 81
bool vmw_seqno_passed(struct vmw_private *dev_priv,
			 uint32_t seqno)
82 83 84 85
{
	struct vmw_fifo_state *fifo_state;
	bool ret;

86
	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
87 88
		return true;

89
	fifo_state = &dev_priv->fifo;
90 91
	vmw_update_seqno(dev_priv, fifo_state);
	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
92 93 94
		return true;

	if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) &&
95
	    vmw_fifo_idle(dev_priv, seqno))
96 97 98
		return true;

	/**
99
	 * Then check if the seqno is higher than what we've actually
100 101 102
	 * emitted. Then the fence is stale and signaled.
	 */

103
	ret = ((atomic_read(&dev_priv->marker_seq) - seqno)
104
	       > VMW_FENCE_WRAP);
105 106 107 108 109 110 111

	return ret;
}

int vmw_fallback_wait(struct vmw_private *dev_priv,
		      bool lazy,
		      bool fifo_idle,
112
		      uint32_t seqno,
113 114 115 116 117 118 119 120 121 122 123 124 125
		      bool interruptible,
		      unsigned long timeout)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;

	uint32_t count = 0;
	uint32_t signal_seq;
	int ret;
	unsigned long end_jiffies = jiffies + timeout;
	bool (*wait_condition)(struct vmw_private *, uint32_t);
	DEFINE_WAIT(__wait);

	wait_condition = (fifo_idle) ? &vmw_fifo_idle :
126
		&vmw_seqno_passed;
127 128 129 130 131 132 133

	/**
	 * Block command submission while waiting for idle.
	 */

	if (fifo_idle)
		down_read(&fifo_state->rwsem);
134
	signal_seq = atomic_read(&dev_priv->marker_seq);
135 136 137 138 139 140
	ret = 0;

	for (;;) {
		prepare_to_wait(&dev_priv->fence_queue, &__wait,
				(interruptible) ?
				TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
141
		if (wait_condition(dev_priv, seqno))
142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161
			break;
		if (time_after_eq(jiffies, end_jiffies)) {
			DRM_ERROR("SVGA device lockup.\n");
			break;
		}
		if (lazy)
			schedule_timeout(1);
		else if ((++count & 0x0F) == 0) {
			/**
			 * FIXME: Use schedule_hr_timeout here for
			 * newer kernels and lower CPU utilization.
			 */

			__set_current_state(TASK_RUNNING);
			schedule();
			__set_current_state((interruptible) ?
					    TASK_INTERRUPTIBLE :
					    TASK_UNINTERRUPTIBLE);
		}
		if (interruptible && signal_pending(current)) {
162
			ret = -ERESTARTSYS;
163 164 165 166 167 168 169 170 171 172 173 174 175 176 177
			break;
		}
	}
	finish_wait(&dev_priv->fence_queue, &__wait);
	if (ret == 0 && fifo_idle) {
		__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
		iowrite32(signal_seq, fifo_mem + SVGA_FIFO_FENCE);
	}
	wake_up_all(&dev_priv->fence_queue);
	if (fifo_idle)
		up_read(&fifo_state->rwsem);

	return ret;
}

178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209
static void vmw_seqno_waiter_add(struct vmw_private *dev_priv)
{
	mutex_lock(&dev_priv->hw_mutex);
	if (dev_priv->fence_queue_waiters++ == 0) {
		unsigned long irq_flags;

		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
		outl(SVGA_IRQFLAG_ANY_FENCE,
		     dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
		vmw_write(dev_priv, SVGA_REG_IRQMASK,
			  vmw_read(dev_priv, SVGA_REG_IRQMASK) |
			  SVGA_IRQFLAG_ANY_FENCE);
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	}
	mutex_unlock(&dev_priv->hw_mutex);
}

static void vmw_seqno_waiter_remove(struct vmw_private *dev_priv)
{
	mutex_lock(&dev_priv->hw_mutex);
	if (--dev_priv->fence_queue_waiters == 0) {
		unsigned long irq_flags;

		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
		vmw_write(dev_priv, SVGA_REG_IRQMASK,
			  vmw_read(dev_priv, SVGA_REG_IRQMASK) &
			  ~SVGA_IRQFLAG_ANY_FENCE);
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	}
	mutex_unlock(&dev_priv->hw_mutex);
}

210 211 212
int vmw_wait_seqno(struct vmw_private *dev_priv,
		      bool lazy, uint32_t seqno,
		      bool interruptible, unsigned long timeout)
213 214 215 216
{
	long ret;
	struct vmw_fifo_state *fifo = &dev_priv->fifo;

217
	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
218 219
		return 0;

220
	if (likely(vmw_seqno_passed(dev_priv, seqno)))
221 222 223 224 225
		return 0;

	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);

	if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE))
226
		return vmw_fallback_wait(dev_priv, lazy, true, seqno,
227 228 229
					 interruptible, timeout);

	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
230
		return vmw_fallback_wait(dev_priv, lazy, false, seqno,
231 232
					 interruptible, timeout);

233
	vmw_seqno_waiter_add(dev_priv);
234 235 236 237

	if (interruptible)
		ret = wait_event_interruptible_timeout
		    (dev_priv->fence_queue,
238
		     vmw_seqno_passed(dev_priv, seqno),
239 240 241 242
		     timeout);
	else
		ret = wait_event_timeout
		    (dev_priv->fence_queue,
243
		     vmw_seqno_passed(dev_priv, seqno),
244 245
		     timeout);

246 247
	vmw_seqno_waiter_remove(dev_priv);

248
	if (unlikely(ret == 0))
249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308
		ret = -EBUSY;
	else if (likely(ret > 0))
		ret = 0;

	return ret;
}

void vmw_irq_preinstall(struct drm_device *dev)
{
	struct vmw_private *dev_priv = vmw_priv(dev);
	uint32_t status;

	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
		return;

	spin_lock_init(&dev_priv->irq_lock);
	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
	outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
}

int vmw_irq_postinstall(struct drm_device *dev)
{
	return 0;
}

void vmw_irq_uninstall(struct drm_device *dev)
{
	struct vmw_private *dev_priv = vmw_priv(dev);
	uint32_t status;

	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
		return;

	mutex_lock(&dev_priv->hw_mutex);
	vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
	mutex_unlock(&dev_priv->hw_mutex);

	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
	outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
}

#define VMW_FENCE_WAIT_TIMEOUT 3*HZ;

int vmw_fence_wait_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	struct drm_vmw_fence_wait_arg *arg =
	    (struct drm_vmw_fence_wait_arg *)data;
	unsigned long timeout;

	if (!arg->cookie_valid) {
		arg->cookie_valid = 1;
		arg->kernel_cookie = jiffies + VMW_FENCE_WAIT_TIMEOUT;
	}

	timeout = jiffies;
	if (time_after_eq(timeout, (unsigned long)arg->kernel_cookie))
		return -EBUSY;

	timeout = (unsigned long)arg->kernel_cookie - timeout;
309
	return vmw_wait_seqno(vmw_priv(dev), true, arg->seqno, true, timeout);
310
}