apic_32.c 44.5 KB
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/*
 *	Local APIC handling, local APIC timers
 *
 *	(c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
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#include <linux/cpu.h>
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#include <linux/clockchips.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/module.h>
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#include <linux/dmi.h>
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#include <asm/atomic.h>
#include <asm/smp.h>
#include <asm/mtrr.h>
#include <asm/mpspec.h>
#include <asm/desc.h>
#include <asm/arch_hooks.h>
#include <asm/hpet.h>
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#include <asm/i8253.h>
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#include <asm/nmi.h>
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#include <mach_apic.h>
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#include <mach_apicdef.h>
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#include <mach_ipi.h>
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/*
 * Sanity check
 */
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#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
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# error SPURIOUS_APIC_VECTOR definition error
#endif

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unsigned long mp_lapic_addr;

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/*
 * Knob to control our willingness to enable the local APIC.
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 *
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 * +1=force-enable
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 */
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static int force_enable_local_apic;
int disable_apic;
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/* Disable local APIC timer from the kernel commandline or via dmi quirk */
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static int disable_apic_timer __cpuinitdata;
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/* Local APIC timer works in C2 */
int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
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int first_system_vector = 0xfe;

char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};

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/*
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 * Debug level, exported for io_apic.c
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 */
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unsigned int apic_verbosity;
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int pic_mode;

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/* Have we found an MP table */
int smp_found_config;

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static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

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static unsigned int calibration_result;
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static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt);
static void lapic_timer_setup(enum clock_event_mode mode,
			      struct clock_event_device *evt);
static void lapic_timer_broadcast(cpumask_t mask);
static void apic_pm_activate(void);
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/*
 * The local apic timer can be used for any function which is CPU local.
 */
static struct clock_event_device lapic_clockevent = {
	.name		= "lapic",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
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			| CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
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	.shift		= 32,
	.set_mode	= lapic_timer_setup,
	.set_next_event	= lapic_next_event,
	.broadcast	= lapic_timer_broadcast,
	.rating		= 100,
	.irq		= -1,
};
static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
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/* Local APIC was disabled by the BIOS and enabled by the kernel */
static int enabled_via_apicbase;

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static unsigned long apic_phys;

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/*
 * Get the LAPIC version
 */
static inline int lapic_get_version(void)
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{
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	return GET_APIC_VERSION(apic_read(APIC_LVR));
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}

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/*
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 * Check, if the APIC is integrated or a separate chip
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 */
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static inline int lapic_is_integrated(void)
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{
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#ifdef CONFIG_X86_64
	return 1;
#else
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	return APIC_INTEGRATED(lapic_get_version());
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#endif
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}

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/*
 * Check, whether this is a modern or a first generation APIC
 */
static int modern_apic(void)
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{
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	/* AMD systems use old APIC versions, so check the CPU */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	    boot_cpu_data.x86 >= 0xf)
		return 1;
	return lapic_get_version() >= 0x14;
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}

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/*
 * Paravirt kernels also might be using these below ops. So we still
 * use generic apic_read()/apic_write(), which might be pointing to different
 * ops in PARAVIRT case.
 */
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void xapic_wait_icr_idle(void)
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{
	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
		cpu_relax();
}

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u32 safe_xapic_wait_icr_idle(void)
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{
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	u32 send_status;
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	int timeout;

	timeout = 0;
	do {
		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
		if (!send_status)
			break;
		udelay(100);
	} while (timeout++ < 1000);

	return send_status;
}

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void xapic_icr_write(u32 low, u32 id)
{
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	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
	apic_write(APIC_ICR, low);
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}

u64 xapic_icr_read(void)
{
	u32 icr1, icr2;

	icr2 = apic_read(APIC_ICR2);
	icr1 = apic_read(APIC_ICR);

	return icr1 | ((u64)icr2 << 32);
}

static struct apic_ops xapic_ops = {
	.read = native_apic_mem_read,
	.write = native_apic_mem_write,
	.icr_read = xapic_icr_read,
	.icr_write = xapic_icr_write,
	.wait_icr_idle = xapic_wait_icr_idle,
	.safe_wait_icr_idle = safe_xapic_wait_icr_idle,
};

struct apic_ops __read_mostly *apic_ops = &xapic_ops;
EXPORT_SYMBOL_GPL(apic_ops);

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/**
 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
 */
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void __cpuinit enable_NMI_through_LVT0(void)
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{
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	unsigned int v;
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	/* unmask and set to NMI */
	v = APIC_DM_NMI;

	/* Level triggered for 82489DX (32bit mode) */
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	if (!lapic_is_integrated())
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		v |= APIC_LVT_LEVEL_TRIGGER;
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	apic_write(APIC_LVT0, v);
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}

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/**
 * get_physical_broadcast - Get number of physical broadcast IDs
 */
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int get_physical_broadcast(void)
{
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	return modern_apic() ? 0xff : 0xf;
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}

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/**
 * lapic_get_maxlvt - get the maximum number of local vector table entries
 */
int lapic_get_maxlvt(void)
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{
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	unsigned int v;
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	v = apic_read(APIC_LVR);
	/*
	 * - we always have APIC integrated on 64bit mode
	 * - 82489DXs do not report # of LVT entries
	 */
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	return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
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}

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/*
 * Local APIC timer
 */

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/* Clock divisor */
#ifdef CONFG_X86_64
#define APIC_DIVISOR 1
#else
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#define APIC_DIVISOR 16
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#endif
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/*
 * This function sets up the local APIC timer, with a timeout of
 * 'clocks' APIC bus clock. During calibration we actually call
 * this function twice on the boot CPU, once with a bogus timeout
 * value, second time for real. The other (noncalibrating) CPUs
 * call this function only once, with the real, calibrated value.
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 *
 * We do reads before writes even if unnecessary, to get around the
 * P5 APIC double write bug.
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 */
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static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
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{
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	unsigned int lvtt_value, tmp_value;
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	lvtt_value = LOCAL_TIMER_VECTOR;
	if (!oneshot)
		lvtt_value |= APIC_LVT_TIMER_PERIODIC;
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	if (!lapic_is_integrated())
		lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);

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	if (!irqen)
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		lvtt_value |= APIC_LVT_MASKED;

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	apic_write(APIC_LVTT, lvtt_value);
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	/*
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	 * Divide PICLK by 16
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	 */
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	tmp_value = apic_read(APIC_TDCR);
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	apic_write(APIC_TDCR,
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		(tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
		APIC_TDR_DIV_16);
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	if (!oneshot)
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		apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
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}

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/*
 * Setup extended LVT, AMD specific (K8, family 10h)
 *
 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
 * MCE interrupts are supported. Thus MCE offset must be set to 0.
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 *
 * If mask=1, the LVT entry does not generate interrupts while mask=0
 * enables the vector. See also the BKDGs.
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 */

#define APIC_EILVT_LVTOFF_MCE 0
#define APIC_EILVT_LVTOFF_IBS 1

static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
{
	unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
	unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;

	apic_write(reg, v);
}

u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
{
	setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
	return APIC_EILVT_LVTOFF_MCE;
}

u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
{
	setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
	return APIC_EILVT_LVTOFF_IBS;
}
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EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
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/*
 * Program the next event, relative to now
 */
static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt)
{
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	apic_write(APIC_TMICT, delta);
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	return 0;
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}

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/*
 * Setup the lapic timer in periodic or oneshot mode
 */
static void lapic_timer_setup(enum clock_event_mode mode,
			      struct clock_event_device *evt)
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{
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	unsigned long flags;
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	unsigned int v;
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	/* Lapic used as dummy for broadcast ? */
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	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
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		return;

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	local_irq_save(flags);
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	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
		__setup_APIC_LVTT(calibration_result,
				  mode != CLOCK_EVT_MODE_PERIODIC, 1);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		v = apic_read(APIC_LVTT);
		v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
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		apic_write(APIC_LVTT, v);
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		break;
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	case CLOCK_EVT_MODE_RESUME:
		/* Nothing to do here */
		break;
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	}
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	local_irq_restore(flags);
}

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/*
 * Local APIC timer broadcast function
 */
static void lapic_timer_broadcast(cpumask_t mask)
{
#ifdef CONFIG_SMP
	send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
#endif
}

/*
 * Setup the local APIC timer for this CPU. Copy the initilized values
 * of the boot CPU and register the clock event in the framework.
 */
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static void __cpuinit setup_APIC_timer(void)
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{
	struct clock_event_device *levt = &__get_cpu_var(lapic_events);

	memcpy(levt, &lapic_clockevent, sizeof(*levt));
	levt->cpumask = cpumask_of_cpu(smp_processor_id());

	clockevents_register_device(levt);
}

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/*
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 * In this functions we calibrate APIC bus clocks to the external timer.
 *
 * We want to do the calibration only once since we want to have local timer
 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
 * frequency.
 *
 * This was previously done by reading the PIT/HPET and waiting for a wrap
 * around to find out, that a tick has elapsed. I have a box, where the PIT
 * readout is broken, so it never gets out of the wait loop again. This was
 * also reported by others.
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 *
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 * Monitoring the jiffies value is inaccurate and the clockevents
 * infrastructure allows us to do a simple substitution of the interrupt
 * handler.
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 *
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 * The calibration routine also uses the pm_timer when possible, as the PIT
 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
 * back to normal later in the boot process).
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 */

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#define LAPIC_CAL_LOOPS		(HZ/10)
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static __initdata int lapic_cal_loops = -1;
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static __initdata long lapic_cal_t1, lapic_cal_t2;
static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
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/*
 * Temporary interrupt handler.
 */
static void __init lapic_cal_handler(struct clock_event_device *dev)
{
	unsigned long long tsc = 0;
	long tapic = apic_read(APIC_TMCCT);
	unsigned long pm = acpi_pm_read_early();
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	if (cpu_has_tsc)
		rdtscll(tsc);

	switch (lapic_cal_loops++) {
	case 0:
		lapic_cal_t1 = tapic;
		lapic_cal_tsc1 = tsc;
		lapic_cal_pm1 = pm;
		lapic_cal_j1 = jiffies;
		break;
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	case LAPIC_CAL_LOOPS:
		lapic_cal_t2 = tapic;
		lapic_cal_tsc2 = tsc;
		if (pm < lapic_cal_pm1)
			pm += ACPI_PM_OVRRUN;
		lapic_cal_pm2 = pm;
		lapic_cal_j2 = jiffies;
		break;
	}
}
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static int __init calibrate_APIC_clock(void)
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{
	struct clock_event_device *levt = &__get_cpu_var(lapic_events);
	const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
	const long pm_thresh = pm_100ms/100;
	void (*real_handler)(struct clock_event_device *dev);
	unsigned long deltaj;
	long delta, deltapm;
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	int pm_referenced = 0;
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	local_irq_disable();

	/* Replace the global interrupt handler */
	real_handler = global_clock_event->event_handler;
	global_clock_event->event_handler = lapic_cal_handler;
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	/*
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	 * Setup the APIC counter to 1e9. There is no way the lapic
	 * can underflow in the 100ms detection time frame
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	 */
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	__setup_APIC_LVTT(1000000000, 0, 0);
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	/* Let the interrupts run */
	local_irq_enable();

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	while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
		cpu_relax();
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	local_irq_disable();

	/* Restore the real event handler */
	global_clock_event->event_handler = real_handler;

	/* Build delta t1-t2 as apic timer counts down */
	delta = lapic_cal_t1 - lapic_cal_t2;
	apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);

	/* Check, if the PM timer is available */
	deltapm = lapic_cal_pm2 - lapic_cal_pm1;
	apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);

	if (deltapm) {
		unsigned long mult;
		u64 res;

		mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);

		if (deltapm > (pm_100ms - pm_thresh) &&
		    deltapm < (pm_100ms + pm_thresh)) {
			apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
		} else {
			res = (((u64) deltapm) *  mult) >> 22;
			do_div(res, 1000000);
			printk(KERN_WARNING "APIC calibration not consistent "
			       "with PM Timer: %ldms instead of 100ms\n",
			       (long)res);
			/* Correct the lapic counter value */
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			res = (((u64) delta) * pm_100ms);
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			do_div(res, deltapm);
			printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
			       "%lu (%ld)\n", (unsigned long) res, delta);
			delta = (long) res;
		}
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		pm_referenced = 1;
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	}
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	/* Calculate the scaled math multiplication factor */
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	lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
				       lapic_clockevent.shift);
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	lapic_clockevent.max_delta_ns =
		clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
	lapic_clockevent.min_delta_ns =
		clockevent_delta2ns(0xF, &lapic_clockevent);

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	calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;

	apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
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	apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
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	apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
		    calibration_result);
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	if (cpu_has_tsc) {
		delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
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		apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
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			    "%ld.%04ld MHz.\n",
			    (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
			    (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
	}
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	apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
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		    "%u.%04u MHz.\n",
		    calibration_result / (1000000 / HZ),
		    calibration_result % (1000000 / HZ));
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	/*
	 * Do a sanity check on the APIC calibration result
	 */
	if (calibration_result < (1000000 / HZ)) {
		local_irq_enable();
		printk(KERN_WARNING
		       "APIC frequency too slow, disabling apic timer\n");
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		return -1;
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	}

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	levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
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	/* We trust the pm timer based calibration */
	if (!pm_referenced) {
		apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
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		/*
		 * Setup the apic timer manually
		 */
		levt->event_handler = lapic_cal_handler;
		lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
		lapic_cal_loops = -1;
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		/* Let the interrupts run */
		local_irq_enable();
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		while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
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			cpu_relax();
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		local_irq_disable();
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		/* Stop the lapic timer */
		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
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		local_irq_enable();
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		/* Jiffies delta */
		deltaj = lapic_cal_j2 - lapic_cal_j1;
		apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
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		/* Check, if the jiffies result is consistent */
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		if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
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			apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
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		else
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			levt->features |= CLOCK_EVT_FEAT_DUMMY;
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	} else
		local_irq_enable();
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	if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
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		printk(KERN_WARNING
		       "APIC timer disabled due to verification failure.\n");
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			return -1;
	}

	return 0;
}

/*
 * Setup the boot APIC
 *
 * Calibrate and verify the result.
 */
void __init setup_boot_APIC_clock(void)
{
	/*
	 * The local apic timer can be disabled via the kernel
	 * commandline or from the CPU detection code. Register the lapic
	 * timer as a dummy clock event source on SMP systems, so the
	 * broadcast mechanism is used. On UP systems simply ignore it.
	 */
620
	if (disable_apic_timer) {
621
		printk(KERN_INFO "Disabling APIC timer\n");
622
		/* No broadcast on UP ! */
623 624 625 626 627
		if (num_possible_cpus() > 1) {
			lapic_clockevent.mult = 1;
			setup_APIC_timer();
		}
		return;
628
	}
629

630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650
	apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
		    "calibrating APIC timer ...\n");

	if (calibrate_APIC_clock()) {
		/* No broadcast on UP ! */
		if (num_possible_cpus() > 1)
			setup_APIC_timer();
		return;
	}

	/*
	 * If nmi_watchdog is set to IO_APIC, we need the
	 * PIT/HPET going.  Otherwise register lapic as a dummy
	 * device.
	 */
	if (nmi_watchdog != NMI_IO_APIC)
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
	else
		printk(KERN_WARNING "APIC timer registered as dummy,"
			" due to nmi_watchdog=%d!\n", nmi_watchdog);

651 652
	/* Setup the lapic or request the broadcast */
	setup_APIC_timer();
653
}
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655
void __cpuinit setup_secondary_APIC_clock(void)
656
{
657
	setup_APIC_timer();
658
}
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660
/*
661
 * The guts of the apic timer interrupt
662
 */
663
static void local_apic_timer_interrupt(void)
664
{
665 666
	int cpu = smp_processor_id();
	struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
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	/*
669 670 671 672
	 * Normally we should not be here till LAPIC has been initialized but
	 * in some cases like kdump, its possible that there is a pending LAPIC
	 * timer interrupt from previous kernel's context and is delivered in
	 * new kernel the moment interrupts are enabled.
673
	 *
674 675 676 677
	 * Interrupts are enabled early and LAPIC is setup much later, hence
	 * its possible that when we get here evt->event_handler is NULL.
	 * Check for event_handler being NULL and discard the interrupt as
	 * spurious.
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	 */
679 680 681 682 683 684 685 686
	if (!evt->event_handler) {
		printk(KERN_WARNING
		       "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
		/* Switch it off */
		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
		return;
	}

687 688 689
	/*
	 * the NMI deadlock-detector uses this.
	 */
690 691 692
#ifdef CONFIG_X86_64
	add_pda(apic_timer_irqs, 1);
#else
693
	per_cpu(irq_stat, cpu).apic_timer_irqs++;
694
#endif
695 696

	evt->event_handler(evt);
697 698 699 700 701 702 703 704 705 706
}

/*
 * Local APIC timer interrupt. This is the most natural way for doing
 * local interrupts, but local timer interrupts can be emulated by
 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
 *
 * [ if a single-CPU system runs an SMP kernel then we call the local
 *   interrupt as well. Thus we cannot inline the local irq ... ]
 */
707
void smp_apic_timer_interrupt(struct pt_regs *regs)
708 709
{
	struct pt_regs *old_regs = set_irq_regs(regs);
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	/*
712 713
	 * NOTE! We'd better ACK the irq immediately,
	 * because timer handling can be slow.
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714
	 */
715
	ack_APIC_irq();
716
	/*
717 718 719
	 * update_process_times() expects us to have done irq_enter().
	 * Besides, if we don't timer interrupts ignore the global
	 * interrupt lock, which is the WrongThing (tm) to do.
720
	 */
721
	irq_enter();
722
	local_apic_timer_interrupt();
723
	irq_exit();
724

725
	set_irq_regs(old_regs);
726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745
}

int setup_profiling_timer(unsigned int multiplier)
{
	return -EINVAL;
}

/*
 * Local APIC start and shutdown
 */

/**
 * clear_local_APIC - shutdown the local APIC
 *
 * This is called, when a CPU is disabled and before rebooting, so the state of
 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
 * leftovers during boot.
 */
void clear_local_APIC(void)
{
746
	int maxlvt;
747
	u32 v;
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749 750 751 752 753
	/* APIC hasn't been mapped yet */
	if (!apic_phys)
		return;

	maxlvt = lapic_get_maxlvt();
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	/*
755 756
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
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	 */
758 759
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
760
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
761
	}
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	/*
763 764
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
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	 */
766
	v = apic_read(APIC_LVTT);
767
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
768
	v = apic_read(APIC_LVT0);
769
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
770
	v = apic_read(APIC_LVT1);
771
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
772 773
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
774
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
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	}

777
	/* lets not touch this if we didn't frob it */
778
#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
779 780
	if (maxlvt >= 5) {
		v = apic_read(APIC_LVTTHMR);
781
		apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
782 783
	}
#endif
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	/*
785
	 * Clean APIC state for other OSs:
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786
	 */
787 788 789
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
790
	if (maxlvt >= 3)
791
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
792
	if (maxlvt >= 4)
793
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
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795 796
	/* Integrated APIC (!82489DX) ? */
	if (lapic_is_integrated()) {
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797
		if (maxlvt > 3)
798
			/* Clear ESR due to Pentium errata 3AP and 11AP */
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799
			apic_write(APIC_ESR, 0);
800
		apic_read(APIC_ESR);
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801
	}
802
}
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804 805 806 807 808
/**
 * disable_local_APIC - clear and disable the local APIC
 */
void disable_local_APIC(void)
{
809
	unsigned int value;
810 811 812 813 814 815 816 817 818

	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
819
	apic_write(APIC_SPIV, value);
820

821
#ifdef CONFIG_X86_32
822 823 824 825 826 827 828 829 830 831 832
	/*
	 * When LAPIC was disabled by the BIOS and enabled by the kernel,
	 * restore the disabled state.
	 */
	if (enabled_via_apicbase) {
		unsigned int l, h;

		rdmsr(MSR_IA32_APICBASE, l, h);
		l &= ~MSR_IA32_APICBASE_ENABLE;
		wrmsr(MSR_IA32_APICBASE, l, h);
	}
833
#endif
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834 835 836
}

/*
837 838 839
 * If Linux enabled the LAPIC against the BIOS default disable it down before
 * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
 * not power-off.  Additionally clear all LVT entries before disable_local_APIC
840
 * for the case where Linux didn't enable the LAPIC.
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 */
void lapic_shutdown(void)
{
844 845
	unsigned long flags;

846
	if (!cpu_has_apic)
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847 848
		return;

849
	local_irq_save(flags);
850

851 852
#ifdef CONFIG_X86_32
	if (!enabled_via_apicbase)
853
		clear_local_APIC();
854 855
	else
#endif
856 857 858
		disable_local_APIC();


859
	local_irq_restore(flags);
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860 861
}

862 863 864 865 866 867
/*
 * This is to verify that we're looking at a real local APIC.
 * Check these against your board if the CPUs aren't getting
 * started for no apparent reason.
 */
int __init verify_local_APIC(void)
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{
869
	unsigned int reg0, reg1;
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871 872 873 874 875 876 877 878 879 880 881 882 883 884 885
	/*
	 * The version register is read-only in a real APIC.
	 */
	reg0 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	reg1 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);

	/*
	 * The two version reads above should print the same
	 * numbers.  If the second one is different, then we
	 * poke at a non-APIC.
	 */
	if (reg1 != reg0)
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		return 0;

888 889 890 891 892 893 894 895 896
	/*
	 * Check if the version looks reasonably.
	 */
	reg1 = GET_APIC_VERSION(reg0);
	if (reg1 == 0x00 || reg1 == 0xff)
		return 0;
	reg1 = lapic_get_maxlvt();
	if (reg1 < 0x02 || reg1 == 0xff)
		return 0;
897

898 899 900 901 902
	/*
	 * The ID register is read/write in a real APIC.
	 */
	reg0 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
903 904 905 906 907 908
	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	reg1 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	apic_write(APIC_ID, reg0);
	if (reg1 != (reg0 ^ APIC_ID_MASK))
		return 0;
909 910 911 912 913 914 915 916 917 918 919 920

	/*
	 * The next two are just to see if we have sane values.
	 * They're only really relevant if we're in Virtual Wire
	 * compatibility mode, but most boxes are anymore.
	 */
	reg0 = apic_read(APIC_LVT0);
	apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
	reg1 = apic_read(APIC_LVT1);
	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);

	return 1;
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}

923 924 925 926
/**
 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
 */
void __init sync_Arb_IDs(void)
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927
{
928 929 930 931
	/*
	 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
	 * needed on AMD.
	 */
932
	if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
933
		return;
934

935 936 937 938
	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();
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940
	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
941 942
	apic_write(APIC_ICR, APIC_DEST_ALLINC |
			APIC_INT_LEVELTRIG | APIC_DM_INIT);
943
}
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945 946 947 948 949
/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
950
	unsigned int value;
951

952 953 954 955 956 957
	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;
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958 959

	/*
960
	 * Do not trust the local APIC being empty at bootup.
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961
	 */
962
	clear_local_APIC();
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964 965 966 967 968 969 970
	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;

971
#ifdef CONFIG_X86_32
972 973 974 975 976
	/* This bit is reserved on P4/Xeon and should be cleared */
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
	    (boot_cpu_data.x86 == 15))
		value &= ~APIC_SPIV_FOCUS_DISABLED;
	else
977
#endif
978 979
		value |= APIC_SPIV_FOCUS_DISABLED;
	value |= SPURIOUS_APIC_VECTOR;
980
	apic_write(APIC_SPIV, value);
981 982 983 984

	/*
	 * Set up the virtual wire mode.
	 */
985
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
986 987 988
	value = APIC_DM_NMI;
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
989
	apic_write(APIC_LVT1, value);
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}

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992
static void __cpuinit lapic_setup_esr(void)
993 994 995
{
	unsigned long oldvalue, value, maxlvt;
	if (lapic_is_integrated() && !esr_disable) {
996 997 998 999 1000 1001 1002 1003 1004 1005
		if (esr_disable) {
			/*
			 * Something untraceable is creating bad interrupts on
			 * secondary quads ... for the moment, just leave the
			 * ESR disabled - we can't do anything useful with the
			 * errors anyway - mbligh
			 */
			printk(KERN_INFO "Leaving ESR disabled.\n");
			return;
		}
1006 1007 1008 1009 1010 1011 1012 1013
		/* !82489DX */
		maxlvt = lapic_get_maxlvt();
		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
			apic_write(APIC_ESR, 0);
		oldvalue = apic_read(APIC_ESR);

		/* enables sending errors */
		value = ERROR_APIC_VECTOR;
1014
		apic_write(APIC_LVTERR, value);
1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025
		/*
		 * spec says clear errors after enabling vector.
		 */
		if (maxlvt > 3)
			apic_write(APIC_ESR, 0);
		value = apic_read(APIC_ESR);
		if (value != oldvalue)
			apic_printk(APIC_VERBOSE, "ESR value before enabling "
				"vector: 0x%08lx  after: 0x%08lx\n",
				oldvalue, value);
	} else {
1026
		printk(KERN_INFO "No ESR for 82489DX.\n");
1027 1028 1029 1030
	}
}


1031 1032
/**
 * setup_local_APIC - setup the local APIC
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1033
 */
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1034
void __cpuinit setup_local_APIC(void)
1035
{
1036
	unsigned int value;
1037
	int i, j;
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1038

1039
#ifdef CONFIG_X86_32
1040 1041 1042 1043 1044 1045 1046
	/* Pound the ESR really hard over the head with a big hammer - mbligh */
	if (esr_disable) {
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
	}
1047
#endif
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1048

1049
	preempt_disable();
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1050

1051 1052
	/*
	 * Double-check whether this APIC is really registered.
1053
	 * This is meaningless in clustered apic mode, so we skip it.
1054 1055
	 */
	if (!apic_id_registered())
1056
		BUG();
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1058 1059 1060 1061 1062 1063
	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
	init_apic_ldr();
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1065 1066 1067 1068 1069 1070
	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
1071
	apic_write(APIC_TASKPRI, value);
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1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090
	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
		value = apic_read(APIC_ISR + i*0x10);
		for (j = 31; j >= 0; j--) {
			if (value & (1<<j))
				ack_APIC_irq();
		}
	}
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1092 1093 1094 1095 1096 1097 1098 1099 1100
	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;
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1101

1102
#ifdef CONFIG_X86_32
1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121
	/*
	 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
	 * certain networking cards. If high frequency interrupts are
	 * happening on a particular IOAPIC pin, plus the IOAPIC routing
	 * entry is masked/unmasked at a high rate as well then sooner or
	 * later IOAPIC line gets 'stuck', no more interrupts are received
	 * from the device. If focus CPU is disabled then the hang goes
	 * away, oh well :-(
	 *
	 * [ This bug can be reproduced easily with a level-triggered
	 *   PCI Ne2000 networking cards and PII/PIII processors, dual
	 *   BX chipset. ]
	 */
	/*
	 * Actually disabling the focus CPU check just makes the hang less
	 * frequent as it makes the interrupt distributon model be more
	 * like LRU than MRU (the short-term load is more even across CPUs).
	 * See also the comment in end_level_ioapic_irq().  --macro
	 */
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1123 1124 1125 1126 1127
	/*
	 * - enable focus processor (bit==0)
	 * - 64bit mode always use processor focus
	 *   so no need to set it
	 */
1128
	value &= ~APIC_SPIV_FOCUS_DISABLED;
1129
#endif
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1130

1131 1132 1133 1134
	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
1135
	apic_write(APIC_SPIV, value);
1136 1137 1138 1139 1140

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
S
Simon Arlott 已提交
1141
	 * strictly necessary in pure symmetric-IO mode, but sometimes
1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
	if (!smp_processor_id() && (pic_mode || !value)) {
		value = APIC_DM_EXTINT;
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
				smp_processor_id());
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
				smp_processor_id());
	}
1157
	apic_write(APIC_LVT0, value);
1158 1159 1160 1161 1162 1163 1164 1165

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
	if (!smp_processor_id())
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
1166
	if (!lapic_is_integrated())		/* 82489DX */
1167
		value |= APIC_LVT_LEVEL_TRIGGER;
1168
	apic_write(APIC_LVT1, value);
1169 1170

	preempt_enable();
1171
}
1172

1173 1174 1175
void __cpuinit end_local_APIC_setup(void)
{
	lapic_setup_esr();
1176 1177

#ifdef CONFIG_X86_32
1178 1179 1180 1181 1182 1183 1184
	{
		unsigned int value;
		/* Disable the local apic timer */
		value = apic_read(APIC_LVTT);
		value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, value);
	}
1185
#endif
1186

1187 1188
	setup_apic_nmi_watchdog(NULL);
	apic_pm_activate();
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}

1191 1192 1193
/*
 * Detect and initialize APIC
 */
1194
static int __init detect_init_APIC(void)
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{
	u32 h, l, features;

	/* Disabled by kernel option? */
1199
	if (disable_apic)
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		return -1;

	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_AMD:
		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1205
		    (boot_cpu_data.x86 == 15))
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			break;
		goto no_apic;
	case X86_VENDOR_INTEL:
		if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
		    (boot_cpu_data.x86 == 5 && cpu_has_apic))
			break;
		goto no_apic;
	default:
		goto no_apic;
	}

	if (!cpu_has_apic) {
		/*
1219 1220
		 * Over-ride BIOS and try to enable the local APIC only if
		 * "lapic" specified.
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		 */
1222
		if (!force_enable_local_apic) {
1223
			printk(KERN_INFO "Local APIC disabled by BIOS -- "
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			       "you can enable it with \"lapic\"\n");
			return -1;
		}
		/*
1228 1229 1230
		 * Some BIOSes disable the local APIC in the APIC_BASE
		 * MSR. This can only be done in software for Intel P6 or later
		 * and AMD K7 (Model > 1) or later.
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		 */
		rdmsr(MSR_IA32_APICBASE, l, h);
		if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1234 1235
			printk(KERN_INFO
			       "Local APIC disabled by BIOS -- reenabling.\n");
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			l &= ~MSR_IA32_APICBASE_BASE;
			l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
			wrmsr(MSR_IA32_APICBASE, l, h);
			enabled_via_apicbase = 1;
		}
	}
	/*
	 * The APIC feature bit should now be enabled
	 * in `cpuid'
	 */
	features = cpuid_edx(1);
	if (!(features & (1 << X86_FEATURE_APIC))) {
1248
		printk(KERN_WARNING "Could not enable APIC!\n");
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		return -1;
	}
1251
	set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
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	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;

	/* The BIOS may have set up the APIC at some other address */
	rdmsr(MSR_IA32_APICBASE, l, h);
1256 1257
	if (l & MSR_IA32_APICBASE_ENABLE)
		mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
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	printk(KERN_INFO "Found and enabled local APIC!\n");
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1261
	apic_pm_activate();
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1263
	return 0;
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1265 1266 1267 1268
no_apic:
	printk(KERN_INFO "No local APIC present or hardware disabled\n");
	return -1;
}
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1270 1271 1272 1273
/**
 * init_apic_mappings - initialize APIC mappings
 */
void __init init_apic_mappings(void)
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{
	/*
1276 1277 1278
	 * If no local APIC can be found then set up a fake all
	 * zeroes page to simulate the local APIC and another
	 * one for the IO-APIC.
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	 */
1280 1281 1282 1283 1284
	if (!smp_found_config && detect_init_APIC()) {
		apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
		apic_phys = __pa(apic_phys);
	} else
		apic_phys = mp_lapic_addr;
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1286 1287 1288
	set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
	printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
	       apic_phys);
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1290 1291 1292 1293 1294
	/*
	 * Fetch the APIC ID of the BSP in case we have a
	 * default configuration (or the MP table is broken).
	 */
	if (boot_cpu_physical_apicid == -1U)
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		boot_cpu_physical_apicid = read_apic_id();
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}

1299 1300 1301 1302
/*
 * This initializes the IO-APIC and APIC hardware if this is
 * a UP kernel.
 */
1303 1304 1305

int apic_version[MAX_APICS];

1306
int __init APIC_init_uniprocessor(void)
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{
1308 1309
	if (!smp_found_config && !cpu_has_apic)
		return -1;
1310

1311 1312 1313 1314 1315 1316 1317
	/*
	 * Complain if the BIOS pretends there is one.
	 */
	if (!cpu_has_apic &&
	    APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
		printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
		       boot_cpu_physical_apicid);
1318
		clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1319
		return -1;
1320 1321
	}

1322
	verify_local_APIC();
1323

1324
	connect_bsp_APIC();
1325

1326 1327 1328 1329 1330 1331
	/*
	 * Hack: In case of kdump, after a crash, kernel might be booting
	 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
	 * might be zero if read from MP tables. Get it from LAPIC.
	 */
#ifdef CONFIG_CRASH_DUMP
1332
	boot_cpu_physical_apicid = read_apic_id();
1333
#endif
1334
	physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
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1336
	setup_local_APIC();
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1338 1339 1340 1341
#ifdef CONFIG_X86_IO_APIC
	if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
#endif
		localise_nmi_watchdog();
1342
	end_local_APIC_setup();
1343 1344 1345 1346
#ifdef CONFIG_X86_IO_APIC
	if (smp_found_config)
		if (!skip_ioapic_setup && nr_ioapics)
			setup_IO_APIC();
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#endif
1348
	setup_boot_clock();
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1350
	return 0;
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}

1353 1354 1355 1356
/*
 * Local APIC interrupts
 */

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/*
 * This interrupt should _never_ happen with our APIC/SMP architecture
 */
1360
void smp_spurious_interrupt(struct pt_regs *regs)
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{
	unsigned long v;

	irq_enter();
	/*
	 * Check if this really is a spurious interrupt and ACK it
	 * if it is a vectored one.  Just in case...
	 * Spurious interrupts should not be ACKed.
	 */
	v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
	if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
		ack_APIC_irq();

	/* see sw-dev-man vol 3, chapter 7.4.13.5 */
1375 1376
	printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
	       "should never happen.\n", smp_processor_id());
1377
	__get_cpu_var(irq_stat).irq_spurious_count++;
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	irq_exit();
}

/*
 * This interrupt should never happen with our APIC/SMP architecture
 */
1384
void smp_error_interrupt(struct pt_regs *regs)
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{
	unsigned long v, v1;

	irq_enter();
	/* First tickle the hardware, only then report what went on. -- REW */
	v = apic_read(APIC_ESR);
	apic_write(APIC_ESR, 0);
	v1 = apic_read(APIC_ESR);
	ack_APIC_irq();
	atomic_inc(&irq_err_count);

	/* Here is what the APIC error bits mean:
	   0: Send CS error
	   1: Receive CS error
	   2: Send accept error
	   3: Receive accept error
	   4: Reserved
	   5: Send illegal vector
	   6: Received illegal vector
	   7: Illegal register address
	*/
1406
	printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1407
		smp_processor_id(), v , v1);
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	irq_exit();
}

1411 1412 1413 1414 1415
/**
 * connect_bsp_APIC - attach the APIC to the interrupt system
 */
void __init connect_bsp_APIC(void)
{
1416
#ifdef CONFIG_X86_32
1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429
	if (pic_mode) {
		/*
		 * Do not trust the local APIC being empty at bootup.
		 */
		clear_local_APIC();
		/*
		 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
		 * local APIC to INT and NMI lines.
		 */
		apic_printk(APIC_VERBOSE, "leaving PIC mode, "
				"enabling APIC mode.\n");
		outb(0x70, 0x22);
		outb(0x01, 0x23);
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	}
1431
#endif
1432 1433
	enable_apic_mode();
}
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1435 1436 1437 1438 1439 1440 1441 1442 1443
/**
 * disconnect_bsp_APIC - detach the APIC from the interrupt system
 * @virt_wire_setup:	indicates, whether virtual wire mode is selected
 *
 * Virtual wire mode is necessary to deliver legacy interrupts even when the
 * APIC is disabled.
 */
void disconnect_bsp_APIC(int virt_wire_setup)
{
1444 1445
	unsigned int value;

1446
#ifdef CONFIG_X86_32
1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457
	if (pic_mode) {
		/*
		 * Put the board back into PIC mode (has an effect only on
		 * certain older boards).  Note that APIC interrupts, including
		 * IPIs, won't work beyond this point!  The only exception are
		 * INIT IPIs.
		 */
		apic_printk(APIC_VERBOSE, "disabling APIC mode, "
				"entering PIC mode.\n");
		outb(0x70, 0x22);
		outb(0x00, 0x23);
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		return;
	}
#endif
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1462
	/* Go back to Virtual Wire compatibility mode */
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1464 1465 1466 1467 1468 1469
	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);
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1471
	if (!virt_wire_setup) {
1472
		/*
1473 1474
		 * For LVT0 make it edge triggered, active high,
		 * external and enabled
1475
		 */
1476 1477
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1478 1479 1480
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1481 1482 1483 1484 1485
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
1486
	}
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1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498
	/*
	 * For LVT1 make it edge triggered, active high,
	 * nmi and enabled
	 */
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
1499
}
1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526

void __cpuinit generic_processor_info(int apicid, int version)
{
	int cpu;
	cpumask_t tmp_map;

	/*
	 * Validate version
	 */
	if (version == 0x0) {
		printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
				"fixing up to 0x10. (tell your hw vendor)\n",
				version);
		version = 0x10;
	}
	apic_version[apicid] = version;

	if (num_processors >= NR_CPUS) {
		printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
			"  Processor ignored.\n", NR_CPUS);
		return;
	}

	num_processors++;
	cpus_complement(tmp_map, cpu_present_map);
	cpu = first_cpu(tmp_map);

1527 1528
	physid_set(apicid, phys_cpu_present_map);
	if (apicid == boot_cpu_physical_apicid) {
1529 1530 1531 1532 1533 1534
		/*
		 * x86_bios_cpu_apicid is required to have processors listed
		 * in same order as logical cpu numbers. Hence the first
		 * entry is BSP, and so on.
		 */
		cpu = 0;
1535
	}
1536 1537 1538
	if (apicid > max_physical_apicid)
		max_physical_apicid = apicid;

1539
#ifdef CONFIG_X86_32
1540 1541 1542 1543 1544 1545 1546
	/*
	 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
	 * but we need to work other dependencies like SMP_SUSPEND etc
	 * before this can be done without some confusion.
	 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
	 *       - Ashok Raj <ashok.raj@intel.com>
	 */
1547
	if (max_physical_apicid >= 8) {
1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558
		switch (boot_cpu_data.x86_vendor) {
		case X86_VENDOR_INTEL:
			if (!APIC_XAPIC(version)) {
				def_to_bigsmp = 0;
				break;
			}
			/* If P4 and above fall through */
		case X86_VENDOR_AMD:
			def_to_bigsmp = 1;
		}
	}
1559 1560 1561
#endif

#if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1562
	/* are we being called early in kernel startup? */
1563 1564 1565
	if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
		u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
		u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1566 1567 1568 1569 1570 1571 1572 1573

		cpu_to_apicid[cpu] = apicid;
		bios_cpu_apicid[cpu] = apicid;
	} else {
		per_cpu(x86_cpu_to_apicid, cpu) = apicid;
		per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
	}
#endif
1574

1575 1576 1577 1578
	cpu_set(cpu, cpu_possible_map);
	cpu_set(cpu, cpu_present_map);
}

1579 1580 1581 1582 1583 1584
/*
 * Power management
 */
#ifdef CONFIG_PM

static struct {
1585 1586 1587 1588 1589
	/*
	 * 'active' is true if the local APIC was enabled by us and
	 * not the BIOS; this signifies that we are also responsible
	 * for disabling it before entering apm/acpi suspend
	 */
1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

static int lapic_suspend(struct sys_device *dev, pm_message_t state)
{
	unsigned long flags;
	int maxlvt;

	if (!apic_pm_state.active)
		return 0;

	maxlvt = lapic_get_maxlvt();

	apic_pm_state.apic_id = apic_read(APIC_ID);
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1630
#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1631 1632
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
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#endif
1634

1635 1636 1637
	local_irq_save(flags);
	disable_local_APIC();
	local_irq_restore(flags);
1638
	return 0;
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}
1640

1641
static int lapic_resume(struct sys_device *dev)
1642
{
1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653
	unsigned int l, h;
	unsigned long flags;
	int maxlvt;

	if (!apic_pm_state.active)
		return 0;

	maxlvt = lapic_get_maxlvt();

	local_irq_save(flags);

1654 1655 1656 1657 1658
#ifdef CONFIG_X86_64
	if (x2apic)
		enable_x2apic();
	else
#endif
1659
	{
1660 1661 1662 1663 1664 1665 1666 1667 1668 1669
		/*
		 * Make sure the APICBASE points to the right address
		 *
		 * FIXME! This will be wrong if we ever support suspend on
		 * SMP! We'll need to do this as part of the CPU restore!
		 */
		rdmsr(MSR_IA32_APICBASE, l, h);
		l &= ~MSR_IA32_APICBASE_BASE;
		l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
		wrmsr(MSR_IA32_APICBASE, l, h);
1670
	}
1671 1672 1673 1674 1675 1676 1677 1678 1679

	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
	apic_write(APIC_ID, apic_pm_state.apic_id);
	apic_write(APIC_DFR, apic_pm_state.apic_dfr);
	apic_write(APIC_LDR, apic_pm_state.apic_ldr);
	apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
	apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
	apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
	apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1680
#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693
	if (maxlvt >= 5)
		apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
#endif
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
	apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
	apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
	apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
	apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
1694

1695
	local_irq_restore(flags);
1696

1697 1698 1699
	return 0;
}

1700 1701 1702 1703 1704 1705
/*
 * This device has no shutdown method - fully functioning local APICs
 * are needed on every CPU up until machine_halt/restart/poweroff.
 */

static struct sysdev_class lapic_sysclass = {
1706
	.name		= "lapic",
1707 1708 1709 1710 1711 1712 1713 1714 1715
	.resume		= lapic_resume,
	.suspend	= lapic_suspend,
};

static struct sys_device device_lapic = {
	.id	= 0,
	.cls	= &lapic_sysclass,
};

1716
static void __cpuinit apic_pm_activate(void)
1717
{
1718
	apic_pm_state.active = 1;
1719 1720
}

1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740
static int __init init_lapic_sysfs(void)
{
	int error;

	if (!cpu_has_apic)
		return 0;
	/* XXX: remove suspend/resume procs if !apic_pm_state.active? */

	error = sysdev_class_register(&lapic_sysclass);
	if (!error)
		error = sysdev_register(&device_lapic);
	return error;
}
device_initcall(init_lapic_sysfs);

#else	/* CONFIG_PM */

static void apic_pm_activate(void) { }

#endif	/* CONFIG_PM */
1741 1742 1743 1744 1745 1746

/*
 * APIC command line parameters
 */
static int __init parse_lapic(char *arg)
{
1747
	force_enable_local_apic = 1;
1748 1749 1750 1751
	return 0;
}
early_param("lapic", parse_lapic);

1752
static int __init setup_disableapic(char *arg)
1753
{
1754
	disable_apic = 1;
1755
	setup_clear_cpu_cap(X86_FEATURE_APIC);
1756 1757
	return 0;
}
1758
early_param("disableapic", setup_disableapic);
1759

1760 1761
/* same as disableapic, for compatibility */
static int __init setup_nolapic(char *arg)
1762
{
1763
	return setup_disableapic(arg);
1764
}
1765
early_param("nolapic", setup_nolapic);
1766 1767 1768 1769 1770 1771 1772 1773

static int __init parse_lapic_timer_c2_ok(char *arg)
{
	local_apic_timer_c2_ok = 1;
	return 0;
}
early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);

1774
static int __init parse_disable_apic_timer(char *arg)
1775
{
1776
	disable_apic_timer = 1;
1777 1778
	return 0;
}
1779 1780 1781
early_param("noapictimer", parse_disable_apic_timer);

static int __init parse_nolapic_timer(char *arg)
1782
{
1783 1784 1785 1786
	disable_apic_timer = 1;
	return 0;
}
early_param("nolapic_timer", parse_nolapic_timer);
1787

1788 1789 1790 1791 1792 1793 1794 1795 1796 1797
#ifdef CONFIG_X86_64
static __init int setup_apicpmtimer(char *s)
{
	apic_calibrate_pmtmr = 1;
	notsc_setup(NULL);
	return 0;
}
__setup("apicpmtimer", setup_apicpmtimer);
#endif

1798
static int __init apic_set_verbosity(char *arg)
1799
{
1800 1801 1802 1803 1804 1805
	if (!arg)  {
#ifdef CONFIG_X86_64
		skip_ioapic_setup = 0;
		ioapic_force = 1;
		return 0;
#endif
1806
		return -EINVAL;
1807
	}
1808

1809
	if (strcmp("debug", arg) == 0)
1810
		apic_verbosity = APIC_DEBUG;
1811
	else if (strcmp("verbose", arg) == 0)
1812
		apic_verbosity = APIC_VERBOSE;
1813 1814 1815 1816 1817
	else {
		printk(KERN_WARNING "APIC Verbosity level %s not recognised"
			" use apic=verbose or apic=debug\n", arg);
		return -EINVAL;
	}
1818

1819
	return 0;
1820
}
1821
early_param("apic", apic_set_verbosity);
1822

1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840
static int __init lapic_insert_resource(void)
{
	if (!apic_phys)
		return -1;

	/* Put local APIC into the resource map. */
	lapic_resource.start = apic_phys;
	lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
	insert_resource(&iomem_resource, &lapic_resource);

	return 0;
}

/*
 * need call insert after e820_reserve_resources()
 * that is using request_resource
 */
late_initcall(lapic_insert_resource);
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