gianfar.c 59.6 KB
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/*
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 * drivers/net/gianfar.c
 *
 * Gianfar Ethernet Driver
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 * This driver is designed for the non-CPM ethernet controllers
 * on the 85xx and 83xx family of integrated processors
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 * Based on 8260_io/fcc_enet.c
 *
 * Author: Andy Fleming
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 * Maintainer: Kumar Gala
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 *
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 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
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 * Copyright (c) 2007 MontaVista Software, Inc.
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 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 *  Gianfar:  AKA Lambda Draconis, "Dragon"
 *  RA 11 31 24.2
 *  Dec +69 19 52
 *  V 3.84
 *  B-V +1.62
 *
 *  Theory of operation
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 *
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 *  The driver is initialized through of_device. Configuration information
 *  is therefore conveyed through an OF-style device tree.
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 *
 *  The Gianfar Ethernet Controller uses a ring of buffer
 *  descriptors.  The beginning is indicated by a register
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 *  pointing to the physical address of the start of the ring.
 *  The end is determined by a "wrap" bit being set in the
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 *  last descriptor of the ring.
 *
 *  When a packet is received, the RXF bit in the
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 *  IEVENT register is set, triggering an interrupt when the
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 *  corresponding bit in the IMASK register is also set (if
 *  interrupt coalescing is active, then the interrupt may not
 *  happen immediately, but will wait until either a set number
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 *  of frames or amount of time have passed).  In NAPI, the
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 *  interrupt handler will signal there is work to be done, and
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 *  exit. This method will start at the last known empty
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 *  descriptor, and process every subsequent descriptor until there
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 *  are none left with data (NAPI will stop after a set number of
 *  packets to give time to other tasks, but will eventually
 *  process all the packets).  The data arrives inside a
 *  pre-allocated skb, and so after the skb is passed up to the
 *  stack, a new skb must be allocated, and the address field in
 *  the buffer descriptor must be updated to indicate this new
 *  skb.
 *
 *  When the kernel requests that a packet be transmitted, the
 *  driver starts where it left off last time, and points the
 *  descriptor at the buffer which was passed in.  The driver
 *  then informs the DMA engine that there are packets ready to
 *  be transmitted.  Once the controller is finished transmitting
 *  the packet, an interrupt may be triggered (under the same
 *  conditions as for reception, but depending on the TXF bit).
 *  The driver then cleans up the buffer.
 */

#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
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#include <linux/unistd.h>
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#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
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#include <linux/if_vlan.h>
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#include <linux/spinlock.h>
#include <linux/mm.h>
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#include <linux/of_platform.h>
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#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/udp.h>
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#include <linux/in.h>
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#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/crc32.h>
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#include <linux/mii.h>
#include <linux/phy.h>
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#include <linux/phy_fixed.h>
#include <linux/of.h>
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#include "gianfar.h"
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#include "gianfar_mii.h"
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#define TX_TIMEOUT      (1*HZ)
#undef BRIEF_GFAR_ERRORS
#undef VERBOSE_GFAR_ERRORS

const char gfar_driver_name[] = "Gianfar Ethernet";
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const char gfar_driver_version[] = "1.3";
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static int gfar_enet_open(struct net_device *dev);
static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
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static void gfar_reset_task(struct work_struct *work);
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static void gfar_timeout(struct net_device *dev);
static int gfar_close(struct net_device *dev);
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struct sk_buff *gfar_new_skb(struct net_device *dev);
static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
		struct sk_buff *skb);
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static int gfar_set_mac_address(struct net_device *dev);
static int gfar_change_mtu(struct net_device *dev, int new_mtu);
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static irqreturn_t gfar_error(int irq, void *dev_id);
static irqreturn_t gfar_transmit(int irq, void *dev_id);
static irqreturn_t gfar_interrupt(int irq, void *dev_id);
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static void adjust_link(struct net_device *dev);
static void init_registers(struct net_device *dev);
static int init_phy(struct net_device *dev);
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static int gfar_probe(struct of_device *ofdev,
		const struct of_device_id *match);
static int gfar_remove(struct of_device *ofdev);
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static void free_skb_resources(struct gfar_private *priv);
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static void gfar_set_multi(struct net_device *dev);
static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
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static void gfar_configure_serdes(struct net_device *dev);
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static int gfar_poll(struct napi_struct *napi, int budget);
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#ifdef CONFIG_NET_POLL_CONTROLLER
static void gfar_netpoll(struct net_device *dev);
#endif
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int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
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static int gfar_clean_tx_ring(struct net_device *dev);
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static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
			      int amount_pull);
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static void gfar_vlan_rx_register(struct net_device *netdev,
		                struct vlan_group *grp);
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void gfar_halt(struct net_device *dev);
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static void gfar_halt_nodisable(struct net_device *dev);
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void gfar_start(struct net_device *dev);
static void gfar_clear_exact_match(struct net_device *dev);
static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
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extern const struct ethtool_ops gfar_ethtool_ops;
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MODULE_AUTHOR("Freescale Semiconductor, Inc");
MODULE_DESCRIPTION("Gianfar Ethernet Driver");
MODULE_LICENSE("GPL");

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/* Returns 1 if incoming frames use an FCB */
static inline int gfar_uses_fcb(struct gfar_private *priv)
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{
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	return priv->vlgrp || priv->rx_csum_enable;
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}
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static int gfar_of_init(struct net_device *dev)
{
	struct device_node *phy, *mdio;
	const unsigned int *id;
	const char *model;
	const char *ctype;
	const void *mac_addr;
	const phandle *ph;
	u64 addr, size;
	int err = 0;
	struct gfar_private *priv = netdev_priv(dev);
	struct device_node *np = priv->node;
	char bus_name[MII_BUS_ID_SIZE];

	if (!np || !of_device_is_available(np))
		return -ENODEV;

	/* get a pointer to the register memory */
	addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
	priv->regs = ioremap(addr, size);

	if (priv->regs == NULL)
		return -ENOMEM;

	priv->interruptTransmit = irq_of_parse_and_map(np, 0);

	model = of_get_property(np, "model", NULL);

	/* If we aren't the FEC we have multiple interrupts */
	if (model && strcasecmp(model, "FEC")) {
		priv->interruptReceive = irq_of_parse_and_map(np, 1);

		priv->interruptError = irq_of_parse_and_map(np, 2);

		if (priv->interruptTransmit < 0 ||
				priv->interruptReceive < 0 ||
				priv->interruptError < 0) {
			err = -EINVAL;
			goto err_out;
		}
	}

	mac_addr = of_get_mac_address(np);
	if (mac_addr)
		memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);

	if (model && !strcasecmp(model, "TSEC"))
		priv->device_flags =
			FSL_GIANFAR_DEV_HAS_GIGABIT |
			FSL_GIANFAR_DEV_HAS_COALESCE |
			FSL_GIANFAR_DEV_HAS_RMON |
			FSL_GIANFAR_DEV_HAS_MULTI_INTR;
	if (model && !strcasecmp(model, "eTSEC"))
		priv->device_flags =
			FSL_GIANFAR_DEV_HAS_GIGABIT |
			FSL_GIANFAR_DEV_HAS_COALESCE |
			FSL_GIANFAR_DEV_HAS_RMON |
			FSL_GIANFAR_DEV_HAS_MULTI_INTR |
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			FSL_GIANFAR_DEV_HAS_PADDING |
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			FSL_GIANFAR_DEV_HAS_CSUM |
			FSL_GIANFAR_DEV_HAS_VLAN |
			FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
			FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;

	ctype = of_get_property(np, "phy-connection-type", NULL);

	/* We only care about rgmii-id.  The rest are autodetected */
	if (ctype && !strcmp(ctype, "rgmii-id"))
		priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
	else
		priv->interface = PHY_INTERFACE_MODE_MII;

	if (of_get_property(np, "fsl,magic-packet", NULL))
		priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;

	ph = of_get_property(np, "phy-handle", NULL);
	if (ph == NULL) {
		u32 *fixed_link;

		fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
		if (!fixed_link) {
			err = -ENODEV;
			goto err_out;
		}

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		snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id),
				PHY_ID_FMT, "0", fixed_link[0]);
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	} else {
		phy = of_find_node_by_phandle(*ph);

		if (phy == NULL) {
			err = -ENODEV;
			goto err_out;
		}

		mdio = of_get_parent(phy);

		id = of_get_property(phy, "reg", NULL);

		of_node_put(phy);
		of_node_put(mdio);

		gfar_mdio_bus_name(bus_name, mdio);
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		snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x",
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				bus_name, *id);
	}

	/* Find the TBI PHY.  If it's not there, we don't support SGMII */
	ph = of_get_property(np, "tbi-handle", NULL);
	if (ph) {
		struct device_node *tbi = of_find_node_by_phandle(*ph);
		struct of_device *ofdev;
		struct mii_bus *bus;

		if (!tbi)
			return 0;

		mdio = of_get_parent(tbi);
		if (!mdio)
			return 0;

		ofdev = of_find_device_by_node(mdio);

		of_node_put(mdio);

		id = of_get_property(tbi, "reg", NULL);
		if (!id)
			return 0;

		of_node_put(tbi);

		bus = dev_get_drvdata(&ofdev->dev);

		priv->tbiphy = bus->phy_map[*id];
	}

	return 0;

err_out:
	iounmap(priv->regs);
	return err;
}

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/* Set up the ethernet device structure, private data,
 * and anything else we need before we start */
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static int gfar_probe(struct of_device *ofdev,
		const struct of_device_id *match)
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{
	u32 tempval;
	struct net_device *dev = NULL;
	struct gfar_private *priv = NULL;
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	DECLARE_MAC_BUF(mac);
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	int err = 0;
	int len_devname;
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	/* Create an ethernet device instance */
	dev = alloc_etherdev(sizeof (*priv));

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	if (NULL == dev)
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		return -ENOMEM;

	priv = netdev_priv(dev);
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	priv->dev = dev;
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	priv->node = ofdev->node;
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	err = gfar_of_init(dev);
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	if (err)
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		goto regs_fail;

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	spin_lock_init(&priv->txlock);
	spin_lock_init(&priv->rxlock);
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	spin_lock_init(&priv->bflock);
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	INIT_WORK(&priv->reset_task, gfar_reset_task);
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	dev_set_drvdata(&ofdev->dev, priv);
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	/* Stop the DMA engine now, in case it was running before */
	/* (The firmware could have used it, and left it running). */
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	gfar_halt(dev);
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	/* Reset MAC layer */
	gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);

	tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
	gfar_write(&priv->regs->maccfg1, tempval);

	/* Initialize MACCFG2. */
	gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);

	/* Initialize ECNTRL */
	gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);

	/* Set the dev->base_addr to the gfar reg region */
	dev->base_addr = (unsigned long) (priv->regs);

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	SET_NETDEV_DEV(dev, &ofdev->dev);
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	/* Fill in the dev structure */
	dev->open = gfar_enet_open;
	dev->hard_start_xmit = gfar_start_xmit;
	dev->tx_timeout = gfar_timeout;
	dev->watchdog_timeo = TX_TIMEOUT;
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	netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
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#ifdef CONFIG_NET_POLL_CONTROLLER
	dev->poll_controller = gfar_netpoll;
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#endif
	dev->stop = gfar_close;
	dev->change_mtu = gfar_change_mtu;
	dev->mtu = 1500;
	dev->set_multicast_list = gfar_set_multi;

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	dev->ethtool_ops = &gfar_ethtool_ops;

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	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
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		priv->rx_csum_enable = 1;
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		dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
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	} else
		priv->rx_csum_enable = 0;

	priv->vlgrp = NULL;
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	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
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		dev->vlan_rx_register = gfar_vlan_rx_register;
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		dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
	}

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	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
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		priv->extended_hash = 1;
		priv->hash_width = 9;

		priv->hash_regs[0] = &priv->regs->igaddr0;
		priv->hash_regs[1] = &priv->regs->igaddr1;
		priv->hash_regs[2] = &priv->regs->igaddr2;
		priv->hash_regs[3] = &priv->regs->igaddr3;
		priv->hash_regs[4] = &priv->regs->igaddr4;
		priv->hash_regs[5] = &priv->regs->igaddr5;
		priv->hash_regs[6] = &priv->regs->igaddr6;
		priv->hash_regs[7] = &priv->regs->igaddr7;
		priv->hash_regs[8] = &priv->regs->gaddr0;
		priv->hash_regs[9] = &priv->regs->gaddr1;
		priv->hash_regs[10] = &priv->regs->gaddr2;
		priv->hash_regs[11] = &priv->regs->gaddr3;
		priv->hash_regs[12] = &priv->regs->gaddr4;
		priv->hash_regs[13] = &priv->regs->gaddr5;
		priv->hash_regs[14] = &priv->regs->gaddr6;
		priv->hash_regs[15] = &priv->regs->gaddr7;

	} else {
		priv->extended_hash = 0;
		priv->hash_width = 8;

		priv->hash_regs[0] = &priv->regs->gaddr0;
                priv->hash_regs[1] = &priv->regs->gaddr1;
		priv->hash_regs[2] = &priv->regs->gaddr2;
		priv->hash_regs[3] = &priv->regs->gaddr3;
		priv->hash_regs[4] = &priv->regs->gaddr4;
		priv->hash_regs[5] = &priv->regs->gaddr5;
		priv->hash_regs[6] = &priv->regs->gaddr6;
		priv->hash_regs[7] = &priv->regs->gaddr7;
	}

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	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
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		priv->padding = DEFAULT_PADDING;
	else
		priv->padding = 0;

	if (dev->features & NETIF_F_IP_CSUM)
		dev->hard_header_len += GMAC_FCB_LEN;
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	priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
	priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
	priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
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	priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
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	priv->txcoalescing = DEFAULT_TX_COALESCE;
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	priv->txic = DEFAULT_TXIC;
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	priv->rxcoalescing = DEFAULT_RX_COALESCE;
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	priv->rxic = DEFAULT_RXIC;
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	/* Enable most messages by default */
	priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;

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	/* Carrier starts down, phylib will bring it up */
	netif_carrier_off(dev);

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	err = register_netdev(dev);

	if (err) {
		printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
				dev->name);
		goto register_fail;
	}

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	/* fill out IRQ number and name fields */
	len_devname = strlen(dev->name);
	strncpy(&priv->int_name_tx[0], dev->name, len_devname);
	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
		strncpy(&priv->int_name_tx[len_devname],
			"_tx", sizeof("_tx") + 1);

		strncpy(&priv->int_name_rx[0], dev->name, len_devname);
		strncpy(&priv->int_name_rx[len_devname],
			"_rx", sizeof("_rx") + 1);

		strncpy(&priv->int_name_er[0], dev->name, len_devname);
		strncpy(&priv->int_name_er[len_devname],
			"_er", sizeof("_er") + 1);
	} else
		priv->int_name_tx[len_devname] = '\0';

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	/* Create all the sysfs files */
	gfar_init_sysfs(dev);

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	/* Print out the device info */
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	printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
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	/* Even more device info helps when determining which kernel */
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	/* provided which set of benchmarks. */
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	printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
	printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
	       dev->name, priv->rx_ring_size, priv->tx_ring_size);

	return 0;

register_fail:
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	iounmap(priv->regs);
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regs_fail:
	free_netdev(dev);
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	return err;
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}

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static int gfar_remove(struct of_device *ofdev)
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{
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	struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
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	dev_set_drvdata(&ofdev->dev, NULL);
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	iounmap(priv->regs);
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	free_netdev(priv->dev);
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	return 0;
}

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#ifdef CONFIG_PM
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static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
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{
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	struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
	struct net_device *dev = priv->dev;
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	unsigned long flags;
	u32 tempval;

	int magic_packet = priv->wol_en &&
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		(priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
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	netif_device_detach(dev);

	if (netif_running(dev)) {
		spin_lock_irqsave(&priv->txlock, flags);
		spin_lock(&priv->rxlock);

		gfar_halt_nodisable(dev);

		/* Disable Tx, and Rx if wake-on-LAN is disabled. */
		tempval = gfar_read(&priv->regs->maccfg1);

		tempval &= ~MACCFG1_TX_EN;

		if (!magic_packet)
			tempval &= ~MACCFG1_RX_EN;

		gfar_write(&priv->regs->maccfg1, tempval);

		spin_unlock(&priv->rxlock);
		spin_unlock_irqrestore(&priv->txlock, flags);

		napi_disable(&priv->napi);

		if (magic_packet) {
			/* Enable interrupt on Magic Packet */
			gfar_write(&priv->regs->imask, IMASK_MAG);

			/* Enable Magic Packet mode */
			tempval = gfar_read(&priv->regs->maccfg2);
			tempval |= MACCFG2_MPEN;
			gfar_write(&priv->regs->maccfg2, tempval);
		} else {
			phy_stop(priv->phydev);
		}
	}

	return 0;
}

551
static int gfar_resume(struct of_device *ofdev)
552
{
553 554
	struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
	struct net_device *dev = priv->dev;
555 556 557
	unsigned long flags;
	u32 tempval;
	int magic_packet = priv->wol_en &&
558
		(priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593

	if (!netif_running(dev)) {
		netif_device_attach(dev);
		return 0;
	}

	if (!magic_packet && priv->phydev)
		phy_start(priv->phydev);

	/* Disable Magic Packet mode, in case something
	 * else woke us up.
	 */

	spin_lock_irqsave(&priv->txlock, flags);
	spin_lock(&priv->rxlock);

	tempval = gfar_read(&priv->regs->maccfg2);
	tempval &= ~MACCFG2_MPEN;
	gfar_write(&priv->regs->maccfg2, tempval);

	gfar_start(dev);

	spin_unlock(&priv->rxlock);
	spin_unlock_irqrestore(&priv->txlock, flags);

	netif_device_attach(dev);

	napi_enable(&priv->napi);

	return 0;
}
#else
#define gfar_suspend NULL
#define gfar_resume NULL
#endif
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595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615
/* Reads the controller's registers to determine what interface
 * connects it to the PHY.
 */
static phy_interface_t gfar_get_interface(struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);
	u32 ecntrl = gfar_read(&priv->regs->ecntrl);

	if (ecntrl & ECNTRL_SGMII_MODE)
		return PHY_INTERFACE_MODE_SGMII;

	if (ecntrl & ECNTRL_TBI_MODE) {
		if (ecntrl & ECNTRL_REDUCED_MODE)
			return PHY_INTERFACE_MODE_RTBI;
		else
			return PHY_INTERFACE_MODE_TBI;
	}

	if (ecntrl & ECNTRL_REDUCED_MODE) {
		if (ecntrl & ECNTRL_REDUCED_MII_MODE)
			return PHY_INTERFACE_MODE_RMII;
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		else {
617
			phy_interface_t interface = priv->interface;
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			/*
			 * This isn't autodetected right now, so it must
			 * be set by the device tree or platform code.
			 */
			if (interface == PHY_INTERFACE_MODE_RGMII_ID)
				return PHY_INTERFACE_MODE_RGMII_ID;

626
			return PHY_INTERFACE_MODE_RGMII;
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		}
628 629
	}

630
	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
631 632 633 634 635 636
		return PHY_INTERFACE_MODE_GMII;

	return PHY_INTERFACE_MODE_MII;
}


637 638
/* Initializes driver's PHY state, and attaches to the PHY.
 * Returns 0 on success.
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 */
static int init_phy(struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);
643
	uint gigabit_support =
644
		priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
645 646
		SUPPORTED_1000baseT_Full : 0;
	struct phy_device *phydev;
647
	phy_interface_t interface;
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	priv->oldlink = 0;
	priv->oldspeed = 0;
	priv->oldduplex = -1;

653 654
	interface = gfar_get_interface(dev);

655
	phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
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	if (interface == PHY_INTERFACE_MODE_SGMII)
		gfar_configure_serdes(dev);

660 661 662
	if (IS_ERR(phydev)) {
		printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
		return PTR_ERR(phydev);
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	}

665 666 667
	/* Remove any features not supported by the controller */
	phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
	phydev->advertising = phydev->supported;
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669
	priv->phydev = phydev;
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	return 0;
}

674 675 676 677 678 679 680 681 682
/*
 * Initialize TBI PHY interface for communicating with the
 * SERDES lynx PHY on the chip.  We communicate with this PHY
 * through the MDIO bus on each controller, treating it as a
 * "normal" PHY at the address found in the TBIPA register.  We assume
 * that the TBIPA register is valid.  Either the MDIO bus code will set
 * it to a value that doesn't conflict with other PHYs on the bus, or the
 * value doesn't matter, as there are no other PHYs on the bus.
 */
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static void gfar_configure_serdes(struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);
686

687 688 689 690 691
	if (!priv->tbiphy) {
		printk(KERN_WARNING "SGMII mode requires that the device "
				"tree specify a tbi-handle\n");
		return;
	}
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693 694
	/*
	 * If the link is already up, we must already be ok, and don't need to
695 696 697 698
	 * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
	 * everything for us?  Resetting it takes the link down and requires
	 * several seconds for it to come back.
	 */
699 700
	if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
		return;
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702
	/* Single clk mode, mii mode off(for serdes communication) */
703
	phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
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705
	phy_write(priv->tbiphy, MII_ADVERTISE,
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			ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
			ADVERTISE_1000XPSE_ASYM);

709
	phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
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			BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
}

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static void init_registers(struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);

	/* Clear IEVENT */
	gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);

	/* Initialize IMASK */
	gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);

	/* Init hash registers to zero */
724 725 726 727 728 729 730 731
	gfar_write(&priv->regs->igaddr0, 0);
	gfar_write(&priv->regs->igaddr1, 0);
	gfar_write(&priv->regs->igaddr2, 0);
	gfar_write(&priv->regs->igaddr3, 0);
	gfar_write(&priv->regs->igaddr4, 0);
	gfar_write(&priv->regs->igaddr5, 0);
	gfar_write(&priv->regs->igaddr6, 0);
	gfar_write(&priv->regs->igaddr7, 0);
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	gfar_write(&priv->regs->gaddr0, 0);
	gfar_write(&priv->regs->gaddr1, 0);
	gfar_write(&priv->regs->gaddr2, 0);
	gfar_write(&priv->regs->gaddr3, 0);
	gfar_write(&priv->regs->gaddr4, 0);
	gfar_write(&priv->regs->gaddr5, 0);
	gfar_write(&priv->regs->gaddr6, 0);
	gfar_write(&priv->regs->gaddr7, 0);

	/* Zero out the rmon mib registers if it has them */
743
	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
744
		memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
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		/* Mask off the CAM interrupts */
		gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
		gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
	}

	/* Initialize the max receive buffer length */
	gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);

	/* Initialize the Minimum Frame Length Register */
	gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
}

758 759

/* Halt the receive and transmit queues */
760
static void gfar_halt_nodisable(struct net_device *dev)
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{
	struct gfar_private *priv = netdev_priv(dev);
763
	struct gfar __iomem *regs = priv->regs;
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	u32 tempval;

	/* Mask all interrupts */
	gfar_write(&regs->imask, IMASK_INIT_CLEAR);

	/* Clear all interrupts */
	gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);

	/* Stop the DMA, and wait for it to stop */
	tempval = gfar_read(&priv->regs->dmactrl);
	if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
	    != (DMACTRL_GRS | DMACTRL_GTS)) {
		tempval |= (DMACTRL_GRS | DMACTRL_GTS);
		gfar_write(&priv->regs->dmactrl, tempval);

		while (!(gfar_read(&priv->regs->ievent) &
			 (IEVENT_GRSC | IEVENT_GTSC)))
			cpu_relax();
	}
783 784 785 786 787 788 789 790
}

/* Halt the receive and transmit queues */
void gfar_halt(struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);
	struct gfar __iomem *regs = priv->regs;
	u32 tempval;
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792 793
	gfar_halt_nodisable(dev);

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	/* Disable Rx and Tx */
	tempval = gfar_read(&regs->maccfg1);
	tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
	gfar_write(&regs->maccfg1, tempval);
798 799 800 801 802
}

void stop_gfar(struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);
803
	struct gfar __iomem *regs = priv->regs;
804 805
	unsigned long flags;

806 807
	phy_stop(priv->phydev);

808
	/* Lock it down */
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	spin_lock_irqsave(&priv->txlock, flags);
	spin_lock(&priv->rxlock);
811 812

	gfar_halt(dev);
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	spin_unlock(&priv->rxlock);
	spin_unlock_irqrestore(&priv->txlock, flags);
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	/* Free the IRQs */
818
	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
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		free_irq(priv->interruptError, dev);
		free_irq(priv->interruptTransmit, dev);
		free_irq(priv->interruptReceive, dev);
	} else {
823
 		free_irq(priv->interruptTransmit, dev);
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	}

	free_skb_resources(priv);

828
	dma_free_coherent(&dev->dev,
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			sizeof(struct txbd8)*priv->tx_ring_size
			+ sizeof(struct rxbd8)*priv->rx_ring_size,
			priv->tx_bd_base,
832
			gfar_read(&regs->tbase0));
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}

/* If there are any tx skbs or rx skbs still around, free them.
 * Then free tx_skbuff and rx_skbuff */
837
static void free_skb_resources(struct gfar_private *priv)
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838 839 840
{
	struct rxbd8 *rxbdp;
	struct txbd8 *txbdp;
D
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841
	int i, j;
L
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842 843 844 845 846

	/* Go through all the buffer descriptors and free their data buffers */
	txbdp = priv->tx_bd_base;

	for (i = 0; i < priv->tx_ring_size; i++) {
D
Dai Haruki 已提交
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		if (!priv->tx_skbuff[i])
			continue;
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849

D
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850 851 852 853 854 855 856
		dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
				txbdp->length, DMA_TO_DEVICE);
		txbdp->lstatus = 0;
		for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
			txbdp++;
			dma_unmap_page(&priv->dev->dev, txbdp->bufPtr,
					txbdp->length, DMA_TO_DEVICE);
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857
		}
858
		txbdp++;
D
Dai Haruki 已提交
859 860
		dev_kfree_skb_any(priv->tx_skbuff[i]);
		priv->tx_skbuff[i] = NULL;
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861 862 863 864 865 866 867 868 869 870 871
	}

	kfree(priv->tx_skbuff);

	rxbdp = priv->rx_bd_base;

	/* rx_skbuff is not guaranteed to be allocated, so only
	 * free it and its contents if it is allocated */
	if(priv->rx_skbuff != NULL) {
		for (i = 0; i < priv->rx_ring_size; i++) {
			if (priv->rx_skbuff[i]) {
872
				dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
873
						priv->rx_buffer_size,
L
Linus Torvalds 已提交
874 875 876 877 878 879
						DMA_FROM_DEVICE);

				dev_kfree_skb_any(priv->rx_skbuff[i]);
				priv->rx_skbuff[i] = NULL;
			}

880
			rxbdp->lstatus = 0;
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881 882 883 884 885 886 887 888 889
			rxbdp->bufPtr = 0;

			rxbdp++;
		}

		kfree(priv->rx_skbuff);
	}
}

890 891 892
void gfar_start(struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);
893
	struct gfar __iomem *regs = priv->regs;
894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910
	u32 tempval;

	/* Enable Rx and Tx in MACCFG1 */
	tempval = gfar_read(&regs->maccfg1);
	tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
	gfar_write(&regs->maccfg1, tempval);

	/* Initialize DMACTRL to have WWR and WOP */
	tempval = gfar_read(&priv->regs->dmactrl);
	tempval |= DMACTRL_INIT_SETTINGS;
	gfar_write(&priv->regs->dmactrl, tempval);

	/* Make sure we aren't stopped */
	tempval = gfar_read(&priv->regs->dmactrl);
	tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
	gfar_write(&priv->regs->dmactrl, tempval);

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Andy Fleming 已提交
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	/* Clear THLT/RHLT, so that the DMA starts polling now */
	gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
	gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);

915 916
	/* Unmask the interrupts we look for */
	gfar_write(&regs->imask, IMASK_DEFAULT);
917 918

	dev->trans_start = jiffies;
919 920
}

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921 922 923 924 925
/* Bring the controller up and running */
int startup_gfar(struct net_device *dev)
{
	struct txbd8 *txbdp;
	struct rxbd8 *rxbdp;
G
Grant Likely 已提交
926
	dma_addr_t addr = 0;
L
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927 928 929
	unsigned long vaddr;
	int i;
	struct gfar_private *priv = netdev_priv(dev);
930
	struct gfar __iomem *regs = priv->regs;
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931
	int err = 0;
932
	u32 rctrl = 0;
933
	u32 attrs = 0;
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934 935 936 937

	gfar_write(&regs->imask, IMASK_INIT_CLEAR);

	/* Allocate memory for the buffer descriptors */
938
	vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
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939 940 941 942 943
			sizeof (struct txbd8) * priv->tx_ring_size +
			sizeof (struct rxbd8) * priv->rx_ring_size,
			&addr, GFP_KERNEL);

	if (vaddr == 0) {
944 945 946
		if (netif_msg_ifup(priv))
			printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
					dev->name);
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947 948 949 950 951 952
		return -ENOMEM;
	}

	priv->tx_bd_base = (struct txbd8 *) vaddr;

	/* enet DMA only understands physical addresses */
953
	gfar_write(&regs->tbase0, addr);
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	/* Start the rx descriptor ring where the tx ring leaves off */
	addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
	vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
	priv->rx_bd_base = (struct rxbd8 *) vaddr;
959
	gfar_write(&regs->rbase0, addr);
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960 961 962 963 964 965

	/* Setup the skbuff rings */
	priv->tx_skbuff =
	    (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
					priv->tx_ring_size, GFP_KERNEL);

966
	if (NULL == priv->tx_skbuff) {
967 968 969
		if (netif_msg_ifup(priv))
			printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
					dev->name);
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		err = -ENOMEM;
		goto tx_skb_fail;
	}

	for (i = 0; i < priv->tx_ring_size; i++)
		priv->tx_skbuff[i] = NULL;

	priv->rx_skbuff =
	    (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
					priv->rx_ring_size, GFP_KERNEL);

981
	if (NULL == priv->rx_skbuff) {
982 983 984
		if (netif_msg_ifup(priv))
			printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
					dev->name);
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985 986 987 988 989 990 991 992
		err = -ENOMEM;
		goto rx_skb_fail;
	}

	for (i = 0; i < priv->rx_ring_size; i++)
		priv->rx_skbuff[i] = NULL;

	/* Initialize some variables in our dev structure */
D
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993
	priv->num_txbdfree = priv->tx_ring_size;
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	priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
	priv->cur_rx = priv->rx_bd_base;
	priv->skb_curtx = priv->skb_dirtytx = 0;
	priv->skb_currx = 0;

	/* Initialize Transmit Descriptor Ring */
	txbdp = priv->tx_bd_base;
	for (i = 0; i < priv->tx_ring_size; i++) {
1002
		txbdp->lstatus = 0;
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1003 1004 1005 1006 1007 1008 1009 1010 1011 1012
		txbdp->bufPtr = 0;
		txbdp++;
	}

	/* Set the last descriptor in the ring to indicate wrap */
	txbdp--;
	txbdp->status |= TXBD_WRAP;

	rxbdp = priv->rx_bd_base;
	for (i = 0; i < priv->rx_ring_size; i++) {
1013
		struct sk_buff *skb;
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1014

1015
		skb = gfar_new_skb(dev);
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1016

1017 1018 1019 1020 1021 1022
		if (!skb) {
			printk(KERN_ERR "%s: Can't allocate RX buffers\n",
					dev->name);

			goto err_rxalloc_fail;
		}
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		priv->rx_skbuff[i] = skb;

1026 1027
		gfar_new_rxbdp(dev, rxbdp, skb);

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		rxbdp++;
	}

	/* Set the last descriptor in the ring to wrap */
	rxbdp--;
	rxbdp->status |= RXBD_WRAP;

	/* If the device has multiple interrupts, register for
	 * them.  Otherwise, only register for the one */
1037
	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1038
		/* Install our interrupt handlers for Error,
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1039 1040
		 * Transmit, and Receive */
		if (request_irq(priv->interruptError, gfar_error,
1041
				0, priv->int_name_er, dev) < 0) {
1042 1043 1044
			if (netif_msg_intr(priv))
				printk(KERN_ERR "%s: Can't get IRQ %d\n",
					dev->name, priv->interruptError);
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1045 1046 1047 1048 1049 1050

			err = -1;
			goto err_irq_fail;
		}

		if (request_irq(priv->interruptTransmit, gfar_transmit,
1051
				0, priv->int_name_tx, dev) < 0) {
1052 1053 1054
			if (netif_msg_intr(priv))
				printk(KERN_ERR "%s: Can't get IRQ %d\n",
					dev->name, priv->interruptTransmit);
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1055 1056 1057 1058 1059 1060 1061

			err = -1;

			goto tx_irq_fail;
		}

		if (request_irq(priv->interruptReceive, gfar_receive,
1062
				0, priv->int_name_rx, dev) < 0) {
1063 1064 1065
			if (netif_msg_intr(priv))
				printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
						dev->name, priv->interruptReceive);
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1066 1067 1068 1069 1070 1071

			err = -1;
			goto rx_irq_fail;
		}
	} else {
		if (request_irq(priv->interruptTransmit, gfar_interrupt,
1072
				0, priv->int_name_tx, dev) < 0) {
1073 1074
			if (netif_msg_intr(priv))
				printk(KERN_ERR "%s: Can't get IRQ %d\n",
1075
					dev->name, priv->interruptTransmit);
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1076 1077 1078 1079 1080 1081

			err = -1;
			goto err_irq_fail;
		}
	}

1082
	phy_start(priv->phydev);
L
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1083 1084

	/* Configure the coalescing support */
1085
	gfar_write(&regs->txic, 0);
L
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1086
	if (priv->txcoalescing)
1087
		gfar_write(&regs->txic, priv->txic);
L
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1088

1089
	gfar_write(&regs->rxic, 0);
L
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1090
	if (priv->rxcoalescing)
1091
		gfar_write(&regs->rxic, priv->rxic);
L
Linus Torvalds 已提交
1092

1093 1094
	if (priv->rx_csum_enable)
		rctrl |= RCTRL_CHECKSUMMING;
L
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1095

1096
	if (priv->extended_hash) {
1097
		rctrl |= RCTRL_EXTHASH;
L
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1098

1099 1100 1101 1102 1103 1104 1105 1106 1107
		gfar_clear_exact_match(dev);
		rctrl |= RCTRL_EMEN;
	}

	if (priv->padding) {
		rctrl &= ~RCTRL_PAL_MASK;
		rctrl |= RCTRL_PADDING(priv->padding);
	}

1108 1109
	/* Init rctrl based on our settings */
	gfar_write(&priv->regs->rctrl, rctrl);
L
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1110

1111 1112
	if (dev->features & NETIF_F_IP_CSUM)
		gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
L
Linus Torvalds 已提交
1113

1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136
	/* Set the extraction length and index */
	attrs = ATTRELI_EL(priv->rx_stash_size) |
		ATTRELI_EI(priv->rx_stash_index);

	gfar_write(&priv->regs->attreli, attrs);

	/* Start with defaults, and add stashing or locking
	 * depending on the approprate variables */
	attrs = ATTR_INIT_SETTINGS;

	if (priv->bd_stash_en)
		attrs |= ATTR_BDSTASH;

	if (priv->rx_stash_size != 0)
		attrs |= ATTR_BUFSTASH;

	gfar_write(&priv->regs->attr, attrs);

	gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
	gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
	gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);

	/* Start the controller */
1137
	gfar_start(dev);
L
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1138 1139 1140 1141 1142 1143 1144 1145

	return 0;

rx_irq_fail:
	free_irq(priv->interruptTransmit, dev);
tx_irq_fail:
	free_irq(priv->interruptError, dev);
err_irq_fail:
1146
err_rxalloc_fail:
L
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1147 1148 1149
rx_skb_fail:
	free_skb_resources(priv);
tx_skb_fail:
1150
	dma_free_coherent(&dev->dev,
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			sizeof(struct txbd8)*priv->tx_ring_size
			+ sizeof(struct rxbd8)*priv->rx_ring_size,
			priv->tx_bd_base,
1154
			gfar_read(&regs->tbase0));
L
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1155 1156 1157 1158 1159 1160 1161 1162

	return err;
}

/* Called when something needs to use the ethernet device */
/* Returns 0 for success. */
static int gfar_enet_open(struct net_device *dev)
{
1163
	struct gfar_private *priv = netdev_priv(dev);
L
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1164 1165
	int err;

1166 1167
	napi_enable(&priv->napi);

L
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1168 1169 1170 1171 1172 1173 1174
	/* Initialize a bunch of registers */
	init_registers(dev);

	gfar_set_mac_address(dev);

	err = init_phy(dev);

1175 1176
	if(err) {
		napi_disable(&priv->napi);
L
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1177
		return err;
1178
	}
L
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1179 1180

	err = startup_gfar(dev);
1181
	if (err) {
1182
		napi_disable(&priv->napi);
1183 1184
		return err;
	}
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1185 1186 1187 1188 1189 1190

	netif_start_queue(dev);

	return err;
}

1191
static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1192 1193 1194
{
	struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);

1195
	cacheable_memzero(fcb, GMAC_FCB_LEN);
1196 1197 1198 1199 1200 1201

	return fcb;
}

static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
{
1202
	u8 flags = 0;
1203 1204 1205 1206 1207

	/* If we're here, it's a IP packet with a TCP or UDP
	 * payload.  We set it to checksum, using a pseudo-header
	 * we provide
	 */
1208
	flags = TXFCB_DEFAULT;
1209

1210 1211
	/* Tell the controller what the protocol is */
	/* And provide the already calculated phcs */
1212
	if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1213
		flags |= TXFCB_UDP;
1214
		fcb->phcs = udp_hdr(skb)->check;
1215
	} else
1216
		fcb->phcs = tcp_hdr(skb)->check;
1217 1218 1219 1220 1221

	/* l3os is the distance between the start of the
	 * frame (skb->data) and the start of the IP hdr.
	 * l4os is the distance between the start of the
	 * l3 hdr and the l4 hdr */
1222
	fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1223
	fcb->l4os = skb_network_header_len(skb);
1224

1225
	fcb->flags = flags;
1226 1227
}

1228
void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1229
{
1230
	fcb->flags |= TXFCB_VLN;
1231 1232 1233
	fcb->vlctl = vlan_tx_tag_get(skb);
}

D
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1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
			       struct txbd8 *base, int ring_size)
{
	struct txbd8 *new_bd = bdp + stride;

	return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
}

static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
		int ring_size)
{
	return skip_txbd(bdp, 1, base, ring_size);
}

L
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1248 1249 1250 1251 1252
/* This is called by the kernel when a frame is ready for transmission. */
/* It is pointed to by the dev->hard_start_xmit function pointer */
static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);
1253
	struct txfcb *fcb = NULL;
D
Dai Haruki 已提交
1254
	struct txbd8 *txbdp, *txbdp_start, *base;
1255
	u32 lstatus;
D
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1256 1257
	int i;
	u32 bufaddr;
A
Andy Fleming 已提交
1258
	unsigned long flags;
D
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1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275
	unsigned int nr_frags, length;

	base = priv->tx_bd_base;

	/* total number of fragments in the SKB */
	nr_frags = skb_shinfo(skb)->nr_frags;

	spin_lock_irqsave(&priv->txlock, flags);

	/* check if there is space to queue this packet */
	if (nr_frags > priv->num_txbdfree) {
		/* no space, stop the queue */
		netif_stop_queue(dev);
		dev->stats.tx_fifo_errors++;
		spin_unlock_irqrestore(&priv->txlock, flags);
		return NETDEV_TX_BUSY;
	}
L
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1276 1277

	/* Update transmit stats */
1278
	dev->stats.tx_bytes += skb->len;
L
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1279

D
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1280
	txbdp = txbdp_start = priv->cur_tx;
L
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1281

D
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1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297
	if (nr_frags == 0) {
		lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
	} else {
		/* Place the fragment addresses and lengths into the TxBDs */
		for (i = 0; i < nr_frags; i++) {
			/* Point at the next BD, wrapping as needed */
			txbdp = next_txbd(txbdp, base, priv->tx_ring_size);

			length = skb_shinfo(skb)->frags[i].size;

			lstatus = txbdp->lstatus | length |
				BD_LFLAG(TXBD_READY);

			/* Handle the last BD specially */
			if (i == nr_frags - 1)
				lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
L
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1298

D
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1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311
			bufaddr = dma_map_page(&dev->dev,
					skb_shinfo(skb)->frags[i].page,
					skb_shinfo(skb)->frags[i].page_offset,
					length,
					DMA_TO_DEVICE);

			/* set the TxBD length and buffer pointer */
			txbdp->bufPtr = bufaddr;
			txbdp->lstatus = lstatus;
		}

		lstatus = txbdp_start->lstatus;
	}
L
Linus Torvalds 已提交
1312

1313
	/* Set up checksumming */
1314
	if (CHECKSUM_PARTIAL == skb->ip_summed) {
1315
		fcb = gfar_add_fcb(skb);
1316
		lstatus |= BD_LFLAG(TXBD_TOE);
1317 1318 1319
		gfar_tx_checksum(skb, fcb);
	}

1320
	if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1321
		if (unlikely(NULL == fcb)) {
1322
			fcb = gfar_add_fcb(skb);
1323
			lstatus |= BD_LFLAG(TXBD_TOE);
1324
		}
1325 1326 1327 1328

		gfar_tx_vlan(skb, fcb);
	}

D
Dai Haruki 已提交
1329
	/* setup the TxBD length and buffer pointer for the first BD */
L
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1330
	priv->tx_skbuff[priv->skb_curtx] = skb;
D
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1331 1332
	txbdp_start->bufPtr = dma_map_single(&dev->dev, skb->data,
			skb_headlen(skb), DMA_TO_DEVICE);
L
Linus Torvalds 已提交
1333

D
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1334
	lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
L
Linus Torvalds 已提交
1335

D
Dai Haruki 已提交
1336 1337
	/*
	 * The powerpc-specific eieio() is used, as wmb() has too strong
1338 1339 1340 1341 1342 1343 1344
	 * semantics (it requires synchronization between cacheable and
	 * uncacheable mappings, which eieio doesn't provide and which we
	 * don't need), thus requiring a more expensive sync instruction.  At
	 * some point, the set of architecture-independent barrier functions
	 * should be expanded to include weaker barriers.
	 */
	eieio();
1345

D
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1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358
	txbdp_start->lstatus = lstatus;

	/* Update the current skb pointer to the next entry we will use
	 * (wrapping if necessary) */
	priv->skb_curtx = (priv->skb_curtx + 1) &
		TX_RING_MOD_MASK(priv->tx_ring_size);

	priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);

	/* reduce TxBD free count */
	priv->num_txbdfree -= (nr_frags + 1);

	dev->trans_start = jiffies;
L
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1359 1360 1361

	/* If the next BD still needs to be cleaned up, then the bds
	   are full.  We need to tell the kernel to stop sending us stuff. */
D
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1362
	if (!priv->num_txbdfree) {
L
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1363 1364
		netif_stop_queue(dev);

1365
		dev->stats.tx_fifo_errors++;
L
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1366 1367 1368 1369 1370 1371
	}

	/* Tell the DMA to go go go */
	gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);

	/* Unlock priv */
A
Andy Fleming 已提交
1372
	spin_unlock_irqrestore(&priv->txlock, flags);
L
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1373 1374 1375 1376 1377 1378 1379 1380

	return 0;
}

/* Stops the kernel queue, and halts the controller */
static int gfar_close(struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);
1381 1382 1383

	napi_disable(&priv->napi);

1384
	cancel_work_sync(&priv->reset_task);
L
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1385 1386
	stop_gfar(dev);

1387 1388 1389
	/* Disconnect from the PHY */
	phy_disconnect(priv->phydev);
	priv->phydev = NULL;
L
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1390 1391 1392 1393 1394 1395 1396

	netif_stop_queue(dev);

	return 0;
}

/* Changes the mac address if the controller is not running. */
1397
static int gfar_set_mac_address(struct net_device *dev)
L
Linus Torvalds 已提交
1398
{
1399
	gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
L
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1400 1401 1402 1403 1404

	return 0;
}


1405 1406 1407 1408 1409 1410
/* Enables and disables VLAN insertion/extraction */
static void gfar_vlan_rx_register(struct net_device *dev,
		struct vlan_group *grp)
{
	struct gfar_private *priv = netdev_priv(dev);
	unsigned long flags;
1411
	struct vlan_group *old_grp;
1412 1413
	u32 tempval;

A
Andy Fleming 已提交
1414
	spin_lock_irqsave(&priv->rxlock, flags);
1415

1416 1417 1418 1419
	old_grp = priv->vlgrp;

	if (old_grp == grp)
		return;
1420 1421 1422 1423 1424 1425 1426

	if (grp) {
		/* Enable VLAN tag insertion */
		tempval = gfar_read(&priv->regs->tctrl);
		tempval |= TCTRL_VLINS;

		gfar_write(&priv->regs->tctrl, tempval);
1427

1428 1429 1430
		/* Enable VLAN tag extraction */
		tempval = gfar_read(&priv->regs->rctrl);
		tempval |= RCTRL_VLEX;
1431
		tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1432 1433 1434 1435 1436 1437 1438 1439 1440 1441
		gfar_write(&priv->regs->rctrl, tempval);
	} else {
		/* Disable VLAN tag insertion */
		tempval = gfar_read(&priv->regs->tctrl);
		tempval &= ~TCTRL_VLINS;
		gfar_write(&priv->regs->tctrl, tempval);

		/* Disable VLAN tag extraction */
		tempval = gfar_read(&priv->regs->rctrl);
		tempval &= ~RCTRL_VLEX;
1442 1443 1444 1445 1446
		/* If parse is no longer required, then disable parser */
		if (tempval & RCTRL_REQ_PARSER)
			tempval |= RCTRL_PRSDEP_INIT;
		else
			tempval &= ~RCTRL_PRSDEP_INIT;
1447 1448 1449
		gfar_write(&priv->regs->rctrl, tempval);
	}

1450 1451
	gfar_change_mtu(dev, dev->mtu);

A
Andy Fleming 已提交
1452
	spin_unlock_irqrestore(&priv->rxlock, flags);
1453 1454
}

L
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1455 1456 1457 1458 1459
static int gfar_change_mtu(struct net_device *dev, int new_mtu)
{
	int tempsize, tempval;
	struct gfar_private *priv = netdev_priv(dev);
	int oldsize = priv->rx_buffer_size;
1460 1461
	int frame_size = new_mtu + ETH_HLEN;

1462
	if (priv->vlgrp)
1463
		frame_size += VLAN_HLEN;
1464

L
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1465
	if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1466 1467 1468
		if (netif_msg_drv(priv))
			printk(KERN_ERR "%s: Invalid MTU setting\n",
					dev->name);
L
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1469 1470 1471
		return -EINVAL;
	}

1472 1473 1474 1475 1476
	if (gfar_uses_fcb(priv))
		frame_size += GMAC_FCB_LEN;

	frame_size += priv->padding;

L
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1477 1478 1479 1480 1481
	tempsize =
	    (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
	    INCREMENTAL_BUFFER_SIZE;

	/* Only stop and start the controller if it isn't already
1482
	 * stopped, and we changed something */
L
Linus Torvalds 已提交
1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510
	if ((oldsize != tempsize) && (dev->flags & IFF_UP))
		stop_gfar(dev);

	priv->rx_buffer_size = tempsize;

	dev->mtu = new_mtu;

	gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
	gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);

	/* If the mtu is larger than the max size for standard
	 * ethernet frames (ie, a jumbo frame), then set maccfg2
	 * to allow huge frames, and to check the length */
	tempval = gfar_read(&priv->regs->maccfg2);

	if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
		tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
	else
		tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);

	gfar_write(&priv->regs->maccfg2, tempval);

	if ((oldsize != tempsize) && (dev->flags & IFF_UP))
		startup_gfar(dev);

	return 0;
}

1511
/* gfar_reset_task gets scheduled when a packet has not been
L
Linus Torvalds 已提交
1512 1513
 * transmitted after a set amount of time.
 * For now, assume that clearing out all the structures, and
1514 1515 1516
 * starting over will fix the problem.
 */
static void gfar_reset_task(struct work_struct *work)
L
Linus Torvalds 已提交
1517
{
1518 1519 1520
	struct gfar_private *priv = container_of(work, struct gfar_private,
			reset_task);
	struct net_device *dev = priv->dev;
L
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1521 1522 1523 1524 1525 1526

	if (dev->flags & IFF_UP) {
		stop_gfar(dev);
		startup_gfar(dev);
	}

1527
	netif_tx_schedule_all(dev);
L
Linus Torvalds 已提交
1528 1529
}

1530 1531 1532 1533 1534 1535 1536 1537
static void gfar_timeout(struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);

	dev->stats.tx_errors++;
	schedule_work(&priv->reset_task);
}

L
Linus Torvalds 已提交
1538
/* Interrupt Handler for Transmit complete */
1539
static int gfar_clean_tx_ring(struct net_device *dev)
L
Linus Torvalds 已提交
1540
{
D
Dai Haruki 已提交
1541
	struct gfar_private *priv = netdev_priv(dev);
D
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1542 1543 1544 1545 1546 1547 1548 1549
	struct txbd8 *bdp;
	struct txbd8 *lbdp = NULL;
	struct txbd8 *base = priv->tx_bd_base;
	struct sk_buff *skb;
	int skb_dirtytx;
	int tx_ring_size = priv->tx_ring_size;
	int frags = 0;
	int i;
D
Dai Haruki 已提交
1550
	int howmany = 0;
D
Dai Haruki 已提交
1551
	u32 lstatus;
L
Linus Torvalds 已提交
1552 1553

	bdp = priv->dirty_tx;
D
Dai Haruki 已提交
1554
	skb_dirtytx = priv->skb_dirtytx;
L
Linus Torvalds 已提交
1555

D
Dai Haruki 已提交
1556 1557 1558
	while ((skb = priv->tx_skbuff[skb_dirtytx])) {
		frags = skb_shinfo(skb)->nr_frags;
		lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
L
Linus Torvalds 已提交
1559

D
Dai Haruki 已提交
1560
		lstatus = lbdp->lstatus;
L
Linus Torvalds 已提交
1561

D
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1562 1563 1564 1565 1566 1567 1568 1569 1570
		/* Only clean completed frames */
		if ((lstatus & BD_LFLAG(TXBD_READY)) &&
				(lstatus & BD_LENGTH_MASK))
			break;

		dma_unmap_single(&dev->dev,
				bdp->bufPtr,
				bdp->length,
				DMA_TO_DEVICE);
A
Andy Fleming 已提交
1571

D
Dai Haruki 已提交
1572 1573
		bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
		bdp = next_txbd(bdp, base, tx_ring_size);
D
Dai Haruki 已提交
1574

D
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1575 1576 1577 1578 1579 1580 1581 1582
		for (i = 0; i < frags; i++) {
			dma_unmap_page(&dev->dev,
					bdp->bufPtr,
					bdp->length,
					DMA_TO_DEVICE);
			bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
			bdp = next_txbd(bdp, base, tx_ring_size);
		}
L
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1583

D
Dai Haruki 已提交
1584 1585
		dev_kfree_skb_any(skb);
		priv->tx_skbuff[skb_dirtytx] = NULL;
D
Dai Haruki 已提交
1586

D
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1587 1588 1589 1590 1591 1592
		skb_dirtytx = (skb_dirtytx + 1) &
			TX_RING_MOD_MASK(tx_ring_size);

		howmany++;
		priv->num_txbdfree += frags + 1;
	}
L
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1593

D
Dai Haruki 已提交
1594 1595 1596
	/* If we freed a buffer, we can restart transmission, if necessary */
	if (netif_queue_stopped(dev) && priv->num_txbdfree)
		netif_wake_queue(dev);
L
Linus Torvalds 已提交
1597

D
Dai Haruki 已提交
1598 1599 1600
	/* Update dirty indicators */
	priv->skb_dirtytx = skb_dirtytx;
	priv->dirty_tx = bdp;
L
Linus Torvalds 已提交
1601

D
Dai Haruki 已提交
1602 1603 1604 1605 1606
	dev->stats.tx_packets += howmany;

	return howmany;
}

1607
static void gfar_schedule_cleanup(struct net_device *dev)
D
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{
	struct gfar_private *priv = netdev_priv(dev);
1610
	if (netif_rx_schedule_prep(&priv->napi)) {
1611
		gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1612
		__netif_rx_schedule(&priv->napi);
1613
	}
1614
}
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1616 1617 1618 1619
/* Interrupt Handler for Transmit complete */
static irqreturn_t gfar_transmit(int irq, void *dev_id)
{
	gfar_schedule_cleanup((struct net_device *)dev_id);
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	return IRQ_HANDLED;
}

1623 1624 1625 1626
static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
		struct sk_buff *skb)
{
	struct gfar_private *priv = netdev_priv(dev);
1627
	u32 lstatus;
1628 1629 1630 1631

	bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
			priv->rx_buffer_size, DMA_FROM_DEVICE);

1632
	lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1633 1634

	if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1635
		lstatus |= BD_LFLAG(RXBD_WRAP);
1636 1637 1638

	eieio();

1639
	bdp->lstatus = lstatus;
1640 1641 1642 1643
}


struct sk_buff * gfar_new_skb(struct net_device *dev)
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{
1645
	unsigned int alignamount;
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	struct gfar_private *priv = netdev_priv(dev);
	struct sk_buff *skb = NULL;

	/* We have to allocate the skb, so keep trying till we succeed */
1650
	skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
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1652
	if (!skb)
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		return NULL;

1655
	alignamount = RXBUF_ALIGNMENT -
1656
		(((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1657

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	/* We need the data buffer to be aligned properly.  We will reserve
	 * as many bytes as needed to align the data properly
	 */
1661
	skb_reserve(skb, alignamount);
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	return skb;
}

1666
static inline void count_errors(unsigned short status, struct net_device *dev)
L
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{
1668
	struct gfar_private *priv = netdev_priv(dev);
1669
	struct net_device_stats *stats = &dev->stats;
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	struct gfar_extra_stats *estats = &priv->extra_stats;

	/* If the packet was truncated, none of the other errors
	 * matter */
	if (status & RXBD_TRUNCATED) {
		stats->rx_length_errors++;

		estats->rx_trunc++;

		return;
	}
	/* Count the errors, if there were any */
	if (status & (RXBD_LARGE | RXBD_SHORT)) {
		stats->rx_length_errors++;

		if (status & RXBD_LARGE)
			estats->rx_large++;
		else
			estats->rx_short++;
	}
	if (status & RXBD_NONOCTET) {
		stats->rx_frame_errors++;
		estats->rx_nonoctet++;
	}
	if (status & RXBD_CRCERR) {
		estats->rx_crcerr++;
		stats->rx_crc_errors++;
	}
	if (status & RXBD_OVERRUN) {
		estats->rx_overrun++;
		stats->rx_crc_errors++;
	}
}

1704
irqreturn_t gfar_receive(int irq, void *dev_id)
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{
1706
	gfar_schedule_cleanup((struct net_device *)dev_id);
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	return IRQ_HANDLED;
}

1710 1711 1712 1713 1714
static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
{
	/* If valid headers were found, and valid sums
	 * were verified, then we tell the kernel that no
	 * checksumming is necessary.  Otherwise, it is */
1715
	if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1716 1717 1718 1719 1720 1721
		skb->ip_summed = CHECKSUM_UNNECESSARY;
	else
		skb->ip_summed = CHECKSUM_NONE;
}


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/* gfar_process_frame() -- handle one incoming packet if skb
 * isn't NULL.  */
static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1725
			      int amount_pull)
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1726 1727
{
	struct gfar_private *priv = netdev_priv(dev);
1728
	struct rxfcb *fcb = NULL;
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1730
	int ret;
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1732 1733
	/* fcb is at the beginning if exists */
	fcb = (struct rxfcb *)skb->data;
1734

1735 1736 1737 1738
	/* Remove the FCB from the skb */
	/* Remove the padded bytes, if there are any */
	if (amount_pull)
		skb_pull(skb, amount_pull);
1739

1740 1741
	if (priv->rx_csum_enable)
		gfar_rx_checksum(skb, fcb);
1742

1743 1744
	/* Tell the skb what kind of packet this is */
	skb->protocol = eth_type_trans(skb, dev);
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1746 1747 1748 1749 1750
	/* Send the packet up the stack */
	if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
		ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
	else
		ret = netif_receive_skb(skb);
1751

1752 1753
	if (NET_RX_DROP == ret)
		priv->extra_stats.kernel_dropped++;
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	return 0;
}

/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1759
 *   until the budget/quota has been reached. Returns the number
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 *   of frames handled
 */
1762
int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
L
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{
1764
	struct rxbd8 *bdp, *base;
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1765
	struct sk_buff *skb;
1766 1767
	int pkt_len;
	int amount_pull;
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	int howmany = 0;
	struct gfar_private *priv = netdev_priv(dev);

	/* Get the first full descriptor */
	bdp = priv->cur_rx;
1773
	base = priv->rx_bd_base;
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1775 1776 1777
	amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
		priv->padding;

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	while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1779
		struct sk_buff *newskb;
1780
		rmb();
1781 1782 1783 1784

		/* Add another skb for the future */
		newskb = gfar_new_skb(dev);

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		skb = priv->rx_skbuff[priv->skb_currx];

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		dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
				priv->rx_buffer_size, DMA_FROM_DEVICE);

1790 1791 1792 1793 1794 1795 1796
		/* We drop the frame if we failed to allocate a new buffer */
		if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
				 bdp->status & RXBD_ERR)) {
			count_errors(bdp->status, dev);

			if (unlikely(!newskb))
				newskb = skb;
1797
			else if (skb)
1798 1799
				dev_kfree_skb_any(skb);
		} else {
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			/* Increment the number of packets */
1801
			dev->stats.rx_packets++;
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			howmany++;

1804 1805 1806 1807 1808
			if (likely(skb)) {
				pkt_len = bdp->length - ETH_FCS_LEN;
				/* Remove the FCS from the packet length */
				skb_put(skb, pkt_len);
				dev->stats.rx_bytes += pkt_len;
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1810 1811 1812 1813 1814 1815 1816 1817 1818
				gfar_process_frame(dev, skb, amount_pull);

			} else {
				if (netif_msg_rx_err(priv))
					printk(KERN_WARNING
					       "%s: Missing skb!\n", dev->name);
				dev->stats.rx_dropped++;
				priv->extra_stats.rx_skbmissing++;
			}
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1819 1820 1821

		}

1822
		priv->rx_skbuff[priv->skb_currx] = newskb;
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1823

1824 1825
		/* Setup the new bdp */
		gfar_new_rxbdp(dev, bdp, newskb);
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1826 1827

		/* Update to the next pointer */
1828
		bdp = next_bd(bdp, base, priv->rx_ring_size);
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		/* update to point at the next skb */
		priv->skb_currx =
1832 1833
		    (priv->skb_currx + 1) &
		    RX_RING_MOD_MASK(priv->rx_ring_size);
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	}

	/* Update the current rxbd pointer to be the next one */
	priv->cur_rx = bdp;

	return howmany;
}

1842
static int gfar_poll(struct napi_struct *napi, int budget)
L
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1843
{
1844 1845
	struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
	struct net_device *dev = priv->dev;
1846 1847
	int tx_cleaned = 0;
	int rx_cleaned = 0;
D
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1848 1849
	unsigned long flags;

1850 1851 1852 1853
	/* Clear IEVENT, so interrupts aren't called again
	 * because of the packets that have already arrived */
	gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);

D
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1854 1855
	/* If we fail to get the lock, don't bother with the TX BDs */
	if (spin_trylock_irqsave(&priv->txlock, flags)) {
1856
		tx_cleaned = gfar_clean_tx_ring(dev);
D
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1857 1858
		spin_unlock_irqrestore(&priv->txlock, flags);
	}
L
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1860
	rx_cleaned = gfar_clean_rx_ring(dev, budget);
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1862 1863 1864 1865
	if (tx_cleaned)
		return budget;

	if (rx_cleaned < budget) {
1866
		netif_rx_complete(napi);
L
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		/* Clear the halt bit in RSTAT */
		gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);

		gfar_write(&priv->regs->imask, IMASK_DEFAULT);

		/* If we are coalescing interrupts, update the timer */
		/* Otherwise, clear it */
1875 1876
		if (likely(priv->rxcoalescing)) {
			gfar_write(&priv->regs->rxic, 0);
1877
			gfar_write(&priv->regs->rxic, priv->rxic);
1878
		}
1879 1880 1881 1882
		if (likely(priv->txcoalescing)) {
			gfar_write(&priv->regs->txic, 0);
			gfar_write(&priv->regs->txic, priv->txic);
		}
L
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1883 1884
	}

1885
	return rx_cleaned;
L
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1886 1887
}

1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898
#ifdef CONFIG_NET_POLL_CONTROLLER
/*
 * Polling 'interrupt' - used by things like netconsole to send skbs
 * without having to re-enable interrupts. It's not called while
 * the interrupt routine is executing.
 */
static void gfar_netpoll(struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);

	/* If the device has multiple interrupts, run tx/rx */
1899
	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914
		disable_irq(priv->interruptTransmit);
		disable_irq(priv->interruptReceive);
		disable_irq(priv->interruptError);
		gfar_interrupt(priv->interruptTransmit, dev);
		enable_irq(priv->interruptError);
		enable_irq(priv->interruptReceive);
		enable_irq(priv->interruptTransmit);
	} else {
		disable_irq(priv->interruptTransmit);
		gfar_interrupt(priv->interruptTransmit, dev);
		enable_irq(priv->interruptTransmit);
	}
}
#endif

L
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1915
/* The interrupt handler for devices with one interrupt */
1916
static irqreturn_t gfar_interrupt(int irq, void *dev_id)
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1917 1918 1919 1920 1921 1922 1923 1924
{
	struct net_device *dev = dev_id;
	struct gfar_private *priv = netdev_priv(dev);

	/* Save ievent for future reference */
	u32 events = gfar_read(&priv->regs->ievent);

	/* Check for reception */
1925
	if (events & IEVENT_RX_MASK)
1926
		gfar_receive(irq, dev_id);
L
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1927 1928

	/* Check for transmit completion */
1929
	if (events & IEVENT_TX_MASK)
1930
		gfar_transmit(irq, dev_id);
L
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1931

1932 1933 1934
	/* Check for errors */
	if (events & IEVENT_ERR_MASK)
		gfar_error(irq, dev_id);
L
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1935 1936 1937 1938 1939 1940

	return IRQ_HANDLED;
}

/* Called every time the controller might need to be made
 * aware of new link state.  The PHY code conveys this
1941
 * information through variables in the phydev structure, and this
L
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1942 1943 1944 1945 1946 1947
 * function converts those variables into the appropriate
 * register values, and can bring down the device if needed.
 */
static void adjust_link(struct net_device *dev)
{
	struct gfar_private *priv = netdev_priv(dev);
1948
	struct gfar __iomem *regs = priv->regs;
1949 1950 1951 1952
	unsigned long flags;
	struct phy_device *phydev = priv->phydev;
	int new_state = 0;

A
Andy Fleming 已提交
1953
	spin_lock_irqsave(&priv->txlock, flags);
1954 1955
	if (phydev->link) {
		u32 tempval = gfar_read(&regs->maccfg2);
1956
		u32 ecntrl = gfar_read(&regs->ecntrl);
L
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1957 1958 1959

		/* Now we make sure that we can be in full duplex mode.
		 * If not, we operate in half-duplex mode. */
1960 1961 1962
		if (phydev->duplex != priv->oldduplex) {
			new_state = 1;
			if (!(phydev->duplex))
L
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1963
				tempval &= ~(MACCFG2_FULL_DUPLEX);
1964
			else
L
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1965 1966
				tempval |= MACCFG2_FULL_DUPLEX;

1967
			priv->oldduplex = phydev->duplex;
L
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1968 1969
		}

1970 1971 1972
		if (phydev->speed != priv->oldspeed) {
			new_state = 1;
			switch (phydev->speed) {
L
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1973 1974 1975
			case 1000:
				tempval =
				    ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1976 1977

				ecntrl &= ~(ECNTRL_R100);
L
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1978 1979 1980 1981 1982
				break;
			case 100:
			case 10:
				tempval =
				    ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1983 1984 1985 1986 1987 1988 1989

				/* Reduced mode distinguishes
				 * between 10 and 100 */
				if (phydev->speed == SPEED_100)
					ecntrl |= ECNTRL_R100;
				else
					ecntrl &= ~(ECNTRL_R100);
L
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1990 1991
				break;
			default:
1992 1993
				if (netif_msg_link(priv))
					printk(KERN_WARNING
1994 1995
						"%s: Ack!  Speed (%d) is not 10/100/1000!\n",
						dev->name, phydev->speed);
L
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1996 1997 1998
				break;
			}

1999
			priv->oldspeed = phydev->speed;
L
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2000 2001
		}

2002
		gfar_write(&regs->maccfg2, tempval);
2003
		gfar_write(&regs->ecntrl, ecntrl);
2004

L
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2005
		if (!priv->oldlink) {
2006
			new_state = 1;
L
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2007 2008
			priv->oldlink = 1;
		}
2009 2010 2011 2012 2013
	} else if (priv->oldlink) {
		new_state = 1;
		priv->oldlink = 0;
		priv->oldspeed = 0;
		priv->oldduplex = -1;
L
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2014 2015
	}

2016 2017 2018
	if (new_state && netif_msg_link(priv))
		phy_print_status(phydev);

A
Andy Fleming 已提交
2019
	spin_unlock_irqrestore(&priv->txlock, flags);
2020
}
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2021 2022 2023 2024 2025 2026 2027 2028 2029

/* Update the hash table based on the current list of multicast
 * addresses we subscribe to.  Also, change the promiscuity of
 * the device based on the flags (this function is called
 * whenever dev->flags is changed */
static void gfar_set_multi(struct net_device *dev)
{
	struct dev_mc_list *mc_ptr;
	struct gfar_private *priv = netdev_priv(dev);
2030
	struct gfar __iomem *regs = priv->regs;
L
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2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043
	u32 tempval;

	if(dev->flags & IFF_PROMISC) {
		/* Set RCTRL to PROM */
		tempval = gfar_read(&regs->rctrl);
		tempval |= RCTRL_PROM;
		gfar_write(&regs->rctrl, tempval);
	} else {
		/* Set RCTRL to not PROM */
		tempval = gfar_read(&regs->rctrl);
		tempval &= ~(RCTRL_PROM);
		gfar_write(&regs->rctrl, tempval);
	}
2044

L
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2045 2046
	if(dev->flags & IFF_ALLMULTI) {
		/* Set the hash to rx all multicast frames */
2047 2048 2049 2050 2051 2052 2053 2054
		gfar_write(&regs->igaddr0, 0xffffffff);
		gfar_write(&regs->igaddr1, 0xffffffff);
		gfar_write(&regs->igaddr2, 0xffffffff);
		gfar_write(&regs->igaddr3, 0xffffffff);
		gfar_write(&regs->igaddr4, 0xffffffff);
		gfar_write(&regs->igaddr5, 0xffffffff);
		gfar_write(&regs->igaddr6, 0xffffffff);
		gfar_write(&regs->igaddr7, 0xffffffff);
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2055 2056 2057 2058 2059 2060 2061 2062 2063
		gfar_write(&regs->gaddr0, 0xffffffff);
		gfar_write(&regs->gaddr1, 0xffffffff);
		gfar_write(&regs->gaddr2, 0xffffffff);
		gfar_write(&regs->gaddr3, 0xffffffff);
		gfar_write(&regs->gaddr4, 0xffffffff);
		gfar_write(&regs->gaddr5, 0xffffffff);
		gfar_write(&regs->gaddr6, 0xffffffff);
		gfar_write(&regs->gaddr7, 0xffffffff);
	} else {
2064 2065 2066
		int em_num;
		int idx;

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2067
		/* zero out the hash */
2068 2069 2070 2071 2072 2073 2074 2075
		gfar_write(&regs->igaddr0, 0x0);
		gfar_write(&regs->igaddr1, 0x0);
		gfar_write(&regs->igaddr2, 0x0);
		gfar_write(&regs->igaddr3, 0x0);
		gfar_write(&regs->igaddr4, 0x0);
		gfar_write(&regs->igaddr5, 0x0);
		gfar_write(&regs->igaddr6, 0x0);
		gfar_write(&regs->igaddr7, 0x0);
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2076 2077 2078 2079 2080 2081 2082 2083 2084
		gfar_write(&regs->gaddr0, 0x0);
		gfar_write(&regs->gaddr1, 0x0);
		gfar_write(&regs->gaddr2, 0x0);
		gfar_write(&regs->gaddr3, 0x0);
		gfar_write(&regs->gaddr4, 0x0);
		gfar_write(&regs->gaddr5, 0x0);
		gfar_write(&regs->gaddr6, 0x0);
		gfar_write(&regs->gaddr7, 0x0);

2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096
		/* If we have extended hash tables, we need to
		 * clear the exact match registers to prepare for
		 * setting them */
		if (priv->extended_hash) {
			em_num = GFAR_EM_NUM + 1;
			gfar_clear_exact_match(dev);
			idx = 1;
		} else {
			idx = 0;
			em_num = 0;
		}

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2097 2098 2099 2100 2101
		if(dev->mc_count == 0)
			return;

		/* Parse the list, and set the appropriate bits */
		for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2102 2103 2104 2105 2106 2107
			if (idx < em_num) {
				gfar_set_mac_for_addr(dev, idx,
						mc_ptr->dmi_addr);
				idx++;
			} else
				gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
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2108 2109 2110 2111 2112 2113
		}
	}

	return;
}

2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125

/* Clears each of the exact match registers to zero, so they
 * don't interfere with normal reception */
static void gfar_clear_exact_match(struct net_device *dev)
{
	int idx;
	u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};

	for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
		gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
}

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/* Set the appropriate hash bit for the given addr */
/* The algorithm works like so:
 * 1) Take the Destination Address (ie the multicast address), and
 * do a CRC on it (little endian), and reverse the bits of the
 * result.
 * 2) Use the 8 most significant bits as a hash into a 256-entry
 * table.  The table is controlled through 8 32-bit registers:
 * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
 * gaddr7.  This means that the 3 most significant bits in the
 * hash index which gaddr register to use, and the 5 other bits
 * indicate which bit (assuming an IBM numbering scheme, which
 * for PowerPC (tm) is usually the case) in the register holds
 * the entry. */
static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
{
	u32 tempval;
	struct gfar_private *priv = netdev_priv(dev);
	u32 result = ether_crc(MAC_ADDR_LEN, addr);
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	int width = priv->hash_width;
	u8 whichbit = (result >> (32 - width)) & 0x1f;
	u8 whichreg = result >> (32 - width + 5);
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	u32 value = (1 << (31-whichbit));

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	tempval = gfar_read(priv->hash_regs[whichreg]);
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	tempval |= value;
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	gfar_write(priv->hash_regs[whichreg], tempval);
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	return;
}

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/* There are multiple MAC Address register pairs on some controllers
 * This function sets the numth pair to a given address
 */
static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
{
	struct gfar_private *priv = netdev_priv(dev);
	int idx;
	char tmpbuf[MAC_ADDR_LEN];
	u32 tempval;
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	u32 __iomem *macptr = &priv->regs->macstnaddr1;
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	macptr += num*2;

	/* Now copy it into the mac registers backwards, cuz */
	/* little endian is silly */
	for (idx = 0; idx < MAC_ADDR_LEN; idx++)
		tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];

	gfar_write(macptr, *((u32 *) (tmpbuf)));

	tempval = *((u32 *) (tmpbuf + 4));

	gfar_write(macptr+1, tempval);
}

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/* GFAR error interrupt handler */
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static irqreturn_t gfar_error(int irq, void *dev_id)
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{
	struct net_device *dev = dev_id;
	struct gfar_private *priv = netdev_priv(dev);

	/* Save ievent for future reference */
	u32 events = gfar_read(&priv->regs->ievent);

	/* Clear IEVENT */
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	gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);

	/* Magic Packet is not an error. */
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	if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
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	    (events & IEVENT_MAG))
		events &= ~IEVENT_MAG;
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	/* Hmm... */
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	if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
		printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
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		       dev->name, events, gfar_read(&priv->regs->imask));
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	/* Update the error counters */
	if (events & IEVENT_TXE) {
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		dev->stats.tx_errors++;
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		if (events & IEVENT_LC)
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			dev->stats.tx_window_errors++;
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		if (events & IEVENT_CRL)
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			dev->stats.tx_aborted_errors++;
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		if (events & IEVENT_XFUN) {
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			if (netif_msg_tx_err(priv))
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				printk(KERN_DEBUG "%s: TX FIFO underrun, "
				       "packet dropped.\n", dev->name);
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			dev->stats.tx_dropped++;
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			priv->extra_stats.tx_underrun++;

			/* Reactivate the Tx Queues */
			gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
		}
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		if (netif_msg_tx_err(priv))
			printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
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	}
	if (events & IEVENT_BSY) {
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		dev->stats.rx_errors++;
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		priv->extra_stats.rx_bsy++;

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		gfar_receive(irq, dev_id);
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		if (netif_msg_rx_err(priv))
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			printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
			       dev->name, gfar_read(&priv->regs->rstat));
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	}
	if (events & IEVENT_BABR) {
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		dev->stats.rx_errors++;
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		priv->extra_stats.rx_babr++;

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		if (netif_msg_rx_err(priv))
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			printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
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	}
	if (events & IEVENT_EBERR) {
		priv->extra_stats.eberr++;
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		if (netif_msg_rx_err(priv))
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			printk(KERN_DEBUG "%s: bus error\n", dev->name);
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	}
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	if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
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		printk(KERN_DEBUG "%s: control frame\n", dev->name);
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	if (events & IEVENT_BABT) {
		priv->extra_stats.tx_babt++;
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		if (netif_msg_tx_err(priv))
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			printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
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	}
	return IRQ_HANDLED;
}

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/* work with hotplug and coldplug */
MODULE_ALIAS("platform:fsl-gianfar");

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static struct of_device_id gfar_match[] =
{
	{
		.type = "network",
		.compatible = "gianfar",
	},
	{},
};

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/* Structure for a device driver */
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static struct of_platform_driver gfar_driver = {
	.name = "fsl-gianfar",
	.match_table = gfar_match,

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	.probe = gfar_probe,
	.remove = gfar_remove,
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	.suspend = gfar_suspend,
	.resume = gfar_resume,
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};

static int __init gfar_init(void)
{
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	int err = gfar_mdio_init();

	if (err)
		return err;

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	err = of_register_platform_driver(&gfar_driver);
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	if (err)
		gfar_mdio_exit();
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	return err;
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}

static void __exit gfar_exit(void)
{
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	of_unregister_platform_driver(&gfar_driver);
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	gfar_mdio_exit();
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}

module_init(gfar_init);
module_exit(gfar_exit);