main.c 72.5 KB
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/*
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 * Copyright (c) 2008-2009 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/nl80211.h>
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#include "ath9k.h"
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static char *dev_info = "ath9k";

MODULE_AUTHOR("Atheros Communications");
MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
MODULE_LICENSE("Dual BSD/GPL");

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static int modparam_nohwcrypt;
module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");

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/* We use the hw_value as an index into our private channel structure */

#define CHAN2G(_freq, _idx)  { \
	.center_freq = (_freq), \
	.hw_value = (_idx), \
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	.max_power = 20, \
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}

#define CHAN5G(_freq, _idx) { \
	.band = IEEE80211_BAND_5GHZ, \
	.center_freq = (_freq), \
	.hw_value = (_idx), \
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	.max_power = 20, \
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}

/* Some 2 GHz radios are actually tunable on 2312-2732
 * on 5 MHz steps, we support the channels which we know
 * we have calibration data for all cards though to make
 * this static */
static struct ieee80211_channel ath9k_2ghz_chantable[] = {
	CHAN2G(2412, 0), /* Channel 1 */
	CHAN2G(2417, 1), /* Channel 2 */
	CHAN2G(2422, 2), /* Channel 3 */
	CHAN2G(2427, 3), /* Channel 4 */
	CHAN2G(2432, 4), /* Channel 5 */
	CHAN2G(2437, 5), /* Channel 6 */
	CHAN2G(2442, 6), /* Channel 7 */
	CHAN2G(2447, 7), /* Channel 8 */
	CHAN2G(2452, 8), /* Channel 9 */
	CHAN2G(2457, 9), /* Channel 10 */
	CHAN2G(2462, 10), /* Channel 11 */
	CHAN2G(2467, 11), /* Channel 12 */
	CHAN2G(2472, 12), /* Channel 13 */
	CHAN2G(2484, 13), /* Channel 14 */
};

/* Some 5 GHz radios are actually tunable on XXXX-YYYY
 * on 5 MHz steps, we support the channels which we know
 * we have calibration data for all cards though to make
 * this static */
static struct ieee80211_channel ath9k_5ghz_chantable[] = {
	/* _We_ call this UNII 1 */
	CHAN5G(5180, 14), /* Channel 36 */
	CHAN5G(5200, 15), /* Channel 40 */
	CHAN5G(5220, 16), /* Channel 44 */
	CHAN5G(5240, 17), /* Channel 48 */
	/* _We_ call this UNII 2 */
	CHAN5G(5260, 18), /* Channel 52 */
	CHAN5G(5280, 19), /* Channel 56 */
	CHAN5G(5300, 20), /* Channel 60 */
	CHAN5G(5320, 21), /* Channel 64 */
	/* _We_ call this "Middle band" */
	CHAN5G(5500, 22), /* Channel 100 */
	CHAN5G(5520, 23), /* Channel 104 */
	CHAN5G(5540, 24), /* Channel 108 */
	CHAN5G(5560, 25), /* Channel 112 */
	CHAN5G(5580, 26), /* Channel 116 */
	CHAN5G(5600, 27), /* Channel 120 */
	CHAN5G(5620, 28), /* Channel 124 */
	CHAN5G(5640, 29), /* Channel 128 */
	CHAN5G(5660, 30), /* Channel 132 */
	CHAN5G(5680, 31), /* Channel 136 */
	CHAN5G(5700, 32), /* Channel 140 */
	/* _We_ call this UNII 3 */
	CHAN5G(5745, 33), /* Channel 149 */
	CHAN5G(5765, 34), /* Channel 153 */
	CHAN5G(5785, 35), /* Channel 157 */
	CHAN5G(5805, 36), /* Channel 161 */
	CHAN5G(5825, 37), /* Channel 165 */
};

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static void ath_cache_conf_rate(struct ath_softc *sc,
				struct ieee80211_conf *conf)
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{
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	switch (conf->channel->band) {
	case IEEE80211_BAND_2GHZ:
		if (conf_is_ht20(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
		else if (conf_is_ht40_minus(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
		else if (conf_is_ht40_plus(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
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		else
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			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11G];
		break;
	case IEEE80211_BAND_5GHZ:
		if (conf_is_ht20(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
		else if (conf_is_ht40_minus(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
		else if (conf_is_ht40_plus(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
		else
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			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11A];
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		break;
	default:
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		BUG_ON(1);
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		break;
	}
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}

static void ath_update_txpow(struct ath_softc *sc)
{
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	struct ath_hw *ah = sc->sc_ah;
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	u32 txpow;

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	if (sc->curtxpow != sc->config.txpowlimit) {
		ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
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		/* read back in case value is clamped */
		ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
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		sc->curtxpow = txpow;
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	}
}

static u8 parse_mpdudensity(u8 mpdudensity)
{
	/*
	 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
	 *   0 for no restriction
	 *   1 for 1/4 us
	 *   2 for 1/2 us
	 *   3 for 1 us
	 *   4 for 2 us
	 *   5 for 4 us
	 *   6 for 8 us
	 *   7 for 16 us
	 */
	switch (mpdudensity) {
	case 0:
		return 0;
	case 1:
	case 2:
	case 3:
		/* Our lower layer calculations limit our precision to
		   1 microsecond */
		return 1;
	case 4:
		return 2;
	case 5:
		return 4;
	case 6:
		return 8;
	case 7:
		return 16;
	default:
		return 0;
	}
}

static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
{
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	const struct ath_rate_table *rate_table = NULL;
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	struct ieee80211_supported_band *sband;
	struct ieee80211_rate *rate;
	int i, maxrates;

	switch (band) {
	case IEEE80211_BAND_2GHZ:
		rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
		break;
	case IEEE80211_BAND_5GHZ:
		rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
		break;
	default:
		break;
	}

	if (rate_table == NULL)
		return;

	sband = &sc->sbands[band];
	rate = sc->rates[band];

	if (rate_table->rate_cnt > ATH_RATE_MAX)
		maxrates = ATH_RATE_MAX;
	else
		maxrates = rate_table->rate_cnt;

	for (i = 0; i < maxrates; i++) {
		rate[i].bitrate = rate_table->info[i].ratekbps / 100;
		rate[i].hw_value = rate_table->info[i].ratecode;
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		if (rate_table->info[i].short_preamble) {
			rate[i].hw_value_short = rate_table->info[i].ratecode |
				rate_table->info[i].short_preamble;
			rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
		}
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		sband->n_bitrates++;
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		DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
			rate[i].bitrate / 10, rate[i].hw_value);
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	}
}

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static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
						struct ieee80211_hw *hw)
{
	struct ieee80211_channel *curchan = hw->conf.channel;
	struct ath9k_channel *channel;
	u8 chan_idx;

	chan_idx = curchan->hw_value;
	channel = &sc->sc_ah->channels[chan_idx];
	ath9k_update_ichannel(sc, hw, channel);
	return channel;
}

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/*
 * Set/change channels.  If the channel is really being changed, it's done
 * by reseting the chip.  To accomplish this we must first cleanup any pending
 * DMA, then restart stuff.
*/
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int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
		    struct ath9k_channel *hchan)
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{
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	struct ath_hw *ah = sc->sc_ah;
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	bool fastcc = true, stopped;
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	struct ieee80211_channel *channel = hw->conf.channel;
	int r;
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	if (sc->sc_flags & SC_OP_INVALID)
		return -EIO;

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	ath9k_ps_wakeup(sc);

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	/*
	 * This is only performed if the channel settings have
	 * actually changed.
	 *
	 * To switch channels clear any pending DMA operations;
	 * wait long enough for the RX fifo to drain, reset the
	 * hardware at the new frequency, and then re-enable
	 * the relevant bits of the h/w.
	 */
	ath9k_hw_set_interrupts(ah, 0);
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	ath_drain_all_txq(sc, false);
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	stopped = ath_stoprecv(sc);
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	/* XXX: do not flush receive queue here. We don't want
	 * to flush data frames already in queue because of
	 * changing channel. */
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	if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
		fastcc = false;

	DPRINTF(sc, ATH_DBG_CONFIG,
		"(%u MHz) -> (%u MHz), chanwidth: %d\n",
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		sc->sc_ah->curchan->channel,
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		channel->center_freq, sc->tx_chan_width);
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	spin_lock_bh(&sc->sc_resetlock);

	r = ath9k_hw_reset(ah, hchan, fastcc);
	if (r) {
		DPRINTF(sc, ATH_DBG_FATAL,
			"Unable to reset channel (%u Mhz) "
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			"reset status %d\n",
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			channel->center_freq, r);
		spin_unlock_bh(&sc->sc_resetlock);
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		goto ps_restore;
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	}
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	spin_unlock_bh(&sc->sc_resetlock);

	sc->sc_flags &= ~SC_OP_FULL_RESET;

	if (ath_startrecv(sc) != 0) {
		DPRINTF(sc, ATH_DBG_FATAL,
			"Unable to restart recv logic\n");
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		r = -EIO;
		goto ps_restore;
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	}

	ath_cache_conf_rate(sc, &hw->conf);
	ath_update_txpow(sc);
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	ath9k_hw_set_interrupts(ah, sc->imask);
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 ps_restore:
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	ath9k_ps_restore(sc);
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	return r;
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}

/*
 *  This routine performs the periodic noise floor calibration function
 *  that is used to adjust and optimize the chip performance.  This
 *  takes environmental changes (location, temperature) into account.
 *  When the task is complete, it reschedules itself depending on the
 *  appropriate interval that was calculated.
 */
static void ath_ani_calibrate(unsigned long data)
{
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	struct ath_softc *sc = (struct ath_softc *)data;
	struct ath_hw *ah = sc->sc_ah;
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	bool longcal = false;
	bool shortcal = false;
	bool aniflag = false;
	unsigned int timestamp = jiffies_to_msecs(jiffies);
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	u32 cal_interval, short_cal_interval;
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	short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
		ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
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	/*
	* don't calibrate when we're scanning.
	* we are most likely not on our home channel.
	*/
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	spin_lock(&sc->ani_lock);
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	if (sc->sc_flags & SC_OP_SCANNING)
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		goto set_timer;
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	/* Only calibrate if awake */
	if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
		goto set_timer;

	ath9k_ps_wakeup(sc);

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	/* Long calibration runs independently of short calibration. */
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	if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
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		longcal = true;
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		DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
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		sc->ani.longcal_timer = timestamp;
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	}

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	/* Short calibration applies only while caldone is false */
	if (!sc->ani.caldone) {
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		if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
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			shortcal = true;
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			DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
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			sc->ani.shortcal_timer = timestamp;
			sc->ani.resetcal_timer = timestamp;
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		}
	} else {
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		if ((timestamp - sc->ani.resetcal_timer) >=
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		    ATH_RESTART_CALINTERVAL) {
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			sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
			if (sc->ani.caldone)
				sc->ani.resetcal_timer = timestamp;
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		}
	}

	/* Verify whether we must check ANI */
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	if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
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		aniflag = true;
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		sc->ani.checkani_timer = timestamp;
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	}

	/* Skip all processing if there's nothing to do. */
	if (longcal || shortcal || aniflag) {
		/* Call ANI routine if necessary */
		if (aniflag)
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			ath9k_hw_ani_monitor(ah, ah->curchan);
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		/* Perform calibration if necessary */
		if (longcal || shortcal) {
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			sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
						     sc->rx_chainmask, longcal);

			if (longcal)
				sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
								     ah->curchan);

			DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
				ah->curchan->channel, ah->curchan->channelFlags,
				sc->ani.noise_floor);
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		}
	}

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	ath9k_ps_restore(sc);

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set_timer:
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	spin_unlock(&sc->ani_lock);
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	/*
	* Set timer interval based on previous results.
	* The interval must be the shortest necessary to satisfy ANI,
	* short calibration and long calibration.
	*/
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	cal_interval = ATH_LONG_CALINTERVAL;
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	if (sc->sc_ah->config.enable_ani)
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		cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
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	if (!sc->ani.caldone)
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		cal_interval = min(cal_interval, (u32)short_cal_interval);
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	mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
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}

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static void ath_start_ani(struct ath_softc *sc)
{
	unsigned long timestamp = jiffies_to_msecs(jiffies);

	sc->ani.longcal_timer = timestamp;
	sc->ani.shortcal_timer = timestamp;
	sc->ani.checkani_timer = timestamp;

	mod_timer(&sc->ani.timer,
		  jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
}

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/*
 * Update tx/rx chainmask. For legacy association,
 * hard code chainmask to 1x1, for 11n association, use
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 * the chainmask configuration, for bt coexistence, use
 * the chainmask configuration even in legacy mode.
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 */
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void ath_update_chainmask(struct ath_softc *sc, int is_ht)
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{
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	if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
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	    (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
		sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
		sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
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	} else {
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		sc->tx_chainmask = 1;
		sc->rx_chainmask = 1;
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	}

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	DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
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		sc->tx_chainmask, sc->rx_chainmask);
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}

static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
{
	struct ath_node *an;

	an = (struct ath_node *)sta->drv_priv;

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	if (sc->sc_flags & SC_OP_TXAGGR) {
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		ath_tx_node_init(sc, an);
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		an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
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				     sta->ht_cap.ampdu_factor);
		an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
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		an->last_rssi = ATH_RSSI_DUMMY_MARKER;
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	}
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}

static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
{
	struct ath_node *an = (struct ath_node *)sta->drv_priv;

	if (sc->sc_flags & SC_OP_TXAGGR)
		ath_tx_node_cleanup(sc, an);
}

static void ath9k_tasklet(unsigned long data)
{
	struct ath_softc *sc = (struct ath_softc *)data;
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	u32 status = sc->intrstatus;
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	ath9k_ps_wakeup(sc);

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	if (status & ATH9K_INT_FATAL) {
		ath_reset(sc, false);
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		ath9k_ps_restore(sc);
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		return;
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	}
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	if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
		spin_lock_bh(&sc->rx.rxflushlock);
		ath_rx_tasklet(sc, 0);
		spin_unlock_bh(&sc->rx.rxflushlock);
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	}

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	if (status & ATH9K_INT_TX)
		ath_tx_tasklet(sc);

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	if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
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		/*
		 * TSF sync does not look correct; remain awake to sync with
		 * the next Beacon.
		 */
		DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
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		sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
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	}

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	/* re-enable hardware interrupt */
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	ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
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	ath9k_ps_restore(sc);
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}

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irqreturn_t ath_isr(int irq, void *dev)
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{
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#define SCHED_INTR (				\
		ATH9K_INT_FATAL |		\
		ATH9K_INT_RXORN |		\
		ATH9K_INT_RXEOL |		\
		ATH9K_INT_RX |			\
		ATH9K_INT_TX |			\
		ATH9K_INT_BMISS |		\
		ATH9K_INT_CST |			\
		ATH9K_INT_TSFOOR)

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	struct ath_softc *sc = dev;
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	struct ath_hw *ah = sc->sc_ah;
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	enum ath9k_int status;
	bool sched = false;

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	/*
	 * The hardware is not ready/present, don't
	 * touch anything. Note this can happen early
	 * on if the IRQ is shared.
	 */
	if (sc->sc_flags & SC_OP_INVALID)
		return IRQ_NONE;
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	/* shared irq, not for us */

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	if (!ath9k_hw_intrpend(ah))
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		return IRQ_NONE;

	/*
	 * Figure out the reason(s) for the interrupt.  Note
	 * that the hal returns a pseudo-ISR that may include
	 * bits we haven't explicitly enabled so we mask the
	 * value to insure we only process bits we requested.
	 */
	ath9k_hw_getisr(ah, &status);	/* NB: clears ISR too */
	status &= sc->imask;	/* discard unasked-for bits */
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554 555 556 557
	/*
	 * If there are no status bits set, then this interrupt was not
	 * for me (should have been caught above).
	 */
558
	if (!status)
559
		return IRQ_NONE;
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560

561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580
	/* Cache the status */
	sc->intrstatus = status;

	if (status & SCHED_INTR)
		sched = true;

	/*
	 * If a FATAL or RXORN interrupt is received, we have to reset the
	 * chip immediately.
	 */
	if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
		goto chip_reset;

	if (status & ATH9K_INT_SWBA)
		tasklet_schedule(&sc->bcon_tasklet);

	if (status & ATH9K_INT_TXURN)
		ath9k_hw_updatetxtriglevel(ah, true);

	if (status & ATH9K_INT_MIB) {
S
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581
		/*
582 583 584
		 * Disable interrupts until we service the MIB
		 * interrupt; otherwise it will continue to
		 * fire.
S
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585
		 */
586 587 588 589 590 591
		ath9k_hw_set_interrupts(ah, 0);
		/*
		 * Let the hal handle the event. We assume
		 * it will clear whatever condition caused
		 * the interrupt.
		 */
592
		ath9k_hw_procmibevent(ah);
593 594
		ath9k_hw_set_interrupts(ah, sc->imask);
	}
S
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595

596 597
	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
		if (status & ATH9K_INT_TIM_TIMER) {
598 599 600
			/* Clear RxAbort bit so that we can
			 * receive frames */
			ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
601
			ath9k_hw_setrxabort(sc->sc_ah, 0);
602
			sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
S
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603
		}
604 605

chip_reset:
S
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606

607 608
	ath_debug_stat_interrupt(sc, status);

S
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609 610
	if (sched) {
		/* turn off every interrupt except SWBA */
611
		ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
S
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612 613 614 615
		tasklet_schedule(&sc->intr_tq);
	}

	return IRQ_HANDLED;
616 617

#undef SCHED_INTR
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618 619
}

620
static u32 ath_get_extchanmode(struct ath_softc *sc,
621
			       struct ieee80211_channel *chan,
622
			       enum nl80211_channel_type channel_type)
623 624 625 626 627
{
	u32 chanmode = 0;

	switch (chan->band) {
	case IEEE80211_BAND_2GHZ:
628 629 630
		switch(channel_type) {
		case NL80211_CHAN_NO_HT:
		case NL80211_CHAN_HT20:
631
			chanmode = CHANNEL_G_HT20;
632 633
			break;
		case NL80211_CHAN_HT40PLUS:
634
			chanmode = CHANNEL_G_HT40PLUS;
635 636
			break;
		case NL80211_CHAN_HT40MINUS:
637
			chanmode = CHANNEL_G_HT40MINUS;
638 639
			break;
		}
640 641
		break;
	case IEEE80211_BAND_5GHZ:
642 643 644
		switch(channel_type) {
		case NL80211_CHAN_NO_HT:
		case NL80211_CHAN_HT20:
645
			chanmode = CHANNEL_A_HT20;
646 647
			break;
		case NL80211_CHAN_HT40PLUS:
648
			chanmode = CHANNEL_A_HT40PLUS;
649 650
			break;
		case NL80211_CHAN_HT40MINUS:
651
			chanmode = CHANNEL_A_HT40MINUS;
652 653
			break;
		}
654 655 656 657 658 659 660 661
		break;
	default:
		break;
	}

	return chanmode;
}

662
static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
663 664
			   struct ath9k_keyval *hk, const u8 *addr,
			   bool authenticator)
665
{
666 667
	const u8 *key_rxmic;
	const u8 *key_txmic;
668

669 670
	key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
	key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
671 672

	if (addr == NULL) {
673 674 675 676 677
		/*
		 * Group key installation - only two key cache entries are used
		 * regardless of splitmic capability since group key is only
		 * used either for TX or RX.
		 */
678 679 680 681 682 683 684
		if (authenticator) {
			memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
			memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
		} else {
			memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
			memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
		}
685
		return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
686
	}
687
	if (!sc->splitmic) {
688
		/* TX and RX keys share the same key cache entry. */
689 690
		memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
		memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
691
		return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
692
	}
693 694 695 696

	/* Separate key cache entries for TX and RX */

	/* TX key goes at first index, RX key at +32. */
697
	memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
698 699
	if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
		/* TX MIC entry failed. No need to proceed further */
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700
		DPRINTF(sc, ATH_DBG_FATAL,
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701
			"Setting TX MIC Key Failed\n");
702 703 704 705 706
		return 0;
	}

	memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
	/* XXX delete tx key on failure? */
707
	return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
708 709 710 711 712 713
}

static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
{
	int i;

714 715 716
	for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
		if (test_bit(i, sc->keymap) ||
		    test_bit(i + 64, sc->keymap))
717
			continue; /* At least one part of TKIP key allocated */
718 719 720
		if (sc->splitmic &&
		    (test_bit(i + 32, sc->keymap) ||
		     test_bit(i + 64 + 32, sc->keymap)))
721 722 723 724 725 726 727 728 729 730 731 732 733
			continue; /* At least one part of TKIP key allocated */

		/* Found a free slot for a TKIP key */
		return i;
	}
	return -1;
}

static int ath_reserve_key_cache_slot(struct ath_softc *sc)
{
	int i;

	/* First, try to find slots that would not be available for TKIP. */
734 735 736 737 738 739
	if (sc->splitmic) {
		for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
			if (!test_bit(i, sc->keymap) &&
			    (test_bit(i + 32, sc->keymap) ||
			     test_bit(i + 64, sc->keymap) ||
			     test_bit(i + 64 + 32, sc->keymap)))
740
				return i;
741 742 743 744
			if (!test_bit(i + 32, sc->keymap) &&
			    (test_bit(i, sc->keymap) ||
			     test_bit(i + 64, sc->keymap) ||
			     test_bit(i + 64 + 32, sc->keymap)))
745
				return i + 32;
746 747 748 749
			if (!test_bit(i + 64, sc->keymap) &&
			    (test_bit(i , sc->keymap) ||
			     test_bit(i + 32, sc->keymap) ||
			     test_bit(i + 64 + 32, sc->keymap)))
750
				return i + 64;
751 752 753 754
			if (!test_bit(i + 64 + 32, sc->keymap) &&
			    (test_bit(i, sc->keymap) ||
			     test_bit(i + 32, sc->keymap) ||
			     test_bit(i + 64, sc->keymap)))
755
				return i + 64 + 32;
756 757
		}
	} else {
758 759 760
		for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
			if (!test_bit(i, sc->keymap) &&
			    test_bit(i + 64, sc->keymap))
761
				return i;
762 763
			if (test_bit(i, sc->keymap) &&
			    !test_bit(i + 64, sc->keymap))
764 765 766 767 768
				return i + 64;
		}
	}

	/* No partially used TKIP slots, pick any available slot */
769
	for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
770 771 772 773 774
		/* Do not allow slots that could be needed for TKIP group keys
		 * to be used. This limitation could be removed if we know that
		 * TKIP will not be used. */
		if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
			continue;
775
		if (sc->splitmic) {
776 777 778 779 780 781
			if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
				continue;
			if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
				continue;
		}

782
		if (!test_bit(i, sc->keymap))
783 784 785 786 787
			return i; /* Found a free slot for a key */
	}

	/* No free slot found */
	return -1;
788 789 790
}

static int ath_key_config(struct ath_softc *sc,
791
			  struct ieee80211_vif *vif,
792
			  struct ieee80211_sta *sta,
793 794 795 796 797
			  struct ieee80211_key_conf *key)
{
	struct ath9k_keyval hk;
	const u8 *mac = NULL;
	int ret = 0;
798
	int idx;
799 800 801 802 803 804 805 806 807 808 809 810 811 812

	memset(&hk, 0, sizeof(hk));

	switch (key->alg) {
	case ALG_WEP:
		hk.kv_type = ATH9K_CIPHER_WEP;
		break;
	case ALG_TKIP:
		hk.kv_type = ATH9K_CIPHER_TKIP;
		break;
	case ALG_CCMP:
		hk.kv_type = ATH9K_CIPHER_AES_CCM;
		break;
	default:
813
		return -EOPNOTSUPP;
814 815
	}

816
	hk.kv_len = key->keylen;
817 818
	memcpy(hk.kv_val, key->key, key->keylen);

819 820 821 822 823
	if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
		/* For now, use the default keys for broadcast keys. This may
		 * need to change with virtual interfaces. */
		idx = key->keyidx;
	} else if (key->keyidx) {
824 825 826 827
		if (WARN_ON(!sta))
			return -EOPNOTSUPP;
		mac = sta->addr;

828 829 830 831 832 833
		if (vif->type != NL80211_IFTYPE_AP) {
			/* Only keyidx 0 should be used with unicast key, but
			 * allow this for client mode for now. */
			idx = key->keyidx;
		} else
			return -EIO;
834
	} else {
835 836 837 838
		if (WARN_ON(!sta))
			return -EOPNOTSUPP;
		mac = sta->addr;

839 840 841 842 843
		if (key->alg == ALG_TKIP)
			idx = ath_reserve_key_cache_slot_tkip(sc);
		else
			idx = ath_reserve_key_cache_slot(sc);
		if (idx < 0)
844
			return -ENOSPC; /* no free key cache entries */
845 846 847
	}

	if (key->alg == ALG_TKIP)
848 849
		ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
				      vif->type == NL80211_IFTYPE_AP);
850
	else
851
		ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
852 853 854 855

	if (!ret)
		return -EIO;

856
	set_bit(idx, sc->keymap);
857
	if (key->alg == ALG_TKIP) {
858 859 860 861
		set_bit(idx + 64, sc->keymap);
		if (sc->splitmic) {
			set_bit(idx + 32, sc->keymap);
			set_bit(idx + 64 + 32, sc->keymap);
862 863 864 865
		}
	}

	return idx;
866 867 868 869
}

static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
{
870 871 872 873
	ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
	if (key->hw_key_idx < IEEE80211_WEP_NKID)
		return;

874
	clear_bit(key->hw_key_idx, sc->keymap);
875 876
	if (key->alg != ALG_TKIP)
		return;
877

878 879 880 881
	clear_bit(key->hw_key_idx + 64, sc->keymap);
	if (sc->splitmic) {
		clear_bit(key->hw_key_idx + 32, sc->keymap);
		clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
882
	}
883 884
}

885 886
static void setup_ht_cap(struct ath_softc *sc,
			 struct ieee80211_sta_ht_cap *ht_info)
887
{
888
	u8 tx_streams, rx_streams;
889

890 891 892 893 894
	ht_info->ht_supported = true;
	ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
		       IEEE80211_HT_CAP_SM_PS |
		       IEEE80211_HT_CAP_SGI_40 |
		       IEEE80211_HT_CAP_DSSSCCK40;
895

896 897
	ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
	ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
898

899 900
	/* set up supported mcs set */
	memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
901 902 903 904 905 906 907 908 909 910
	tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
	rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;

	if (tx_streams != rx_streams) {
		DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
			tx_streams, rx_streams);
		ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
		ht_info->mcs.tx_params |= ((tx_streams - 1) <<
				IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
	}
911

912 913
	ht_info->mcs.rx_mask[0] = 0xff;
	if (rx_streams >= 2)
914 915
		ht_info->mcs.rx_mask[1] = 0xff;

916
	ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
917 918
}

919
static void ath9k_bss_assoc_info(struct ath_softc *sc,
S
Sujith 已提交
920
				 struct ieee80211_vif *vif,
921
				 struct ieee80211_bss_conf *bss_conf)
922 923
{

924
	if (bss_conf->assoc) {
925
		DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
926
			bss_conf->aid, sc->curbssid);
927

928
		/* New association, store aid */
929 930 931 932 933 934 935 936 937
		sc->curaid = bss_conf->aid;
		ath9k_hw_write_associd(sc);

		/*
		 * Request a re-configuration of Beacon related timers
		 * on the receipt of the first Beacon frame (i.e.,
		 * after time sync with the AP).
		 */
		sc->sc_flags |= SC_OP_BEACON_SYNC;
938

939
		/* Configure the beacon */
940
		ath_beacon_config(sc, vif);
941

942
		/* Reset rssi stats */
943
		sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
944

S
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945
		ath_start_ani(sc);
946
	} else {
947
		DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
948
		sc->curaid = 0;
949 950
		/* Stop ANI */
		del_timer_sync(&sc->ani.timer);
951
	}
952
}
953

954 955 956
/********************************/
/*	 LED functions		*/
/********************************/
957

958 959 960 961 962 963 964
static void ath_led_blink_work(struct work_struct *work)
{
	struct ath_softc *sc = container_of(work, struct ath_softc,
					    ath_led_blink_work.work);

	if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
		return;
965 966 967

	if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
	    (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
968
		ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
969
	else
970
		ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
971
				  (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
972

973 974 975 976 977
	ieee80211_queue_delayed_work(sc->hw,
				     &sc->ath_led_blink_work,
				     (sc->sc_flags & SC_OP_LED_ON) ?
					msecs_to_jiffies(sc->led_off_duration) :
					msecs_to_jiffies(sc->led_on_duration));
978

979 980 981 982 983 984
	sc->led_on_duration = sc->led_on_cnt ?
			max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
			ATH_LED_ON_DURATION_IDLE;
	sc->led_off_duration = sc->led_off_cnt ?
			max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
			ATH_LED_OFF_DURATION_IDLE;
985 986 987 988 989 990 991
	sc->led_on_cnt = sc->led_off_cnt = 0;
	if (sc->sc_flags & SC_OP_LED_ON)
		sc->sc_flags &= ~SC_OP_LED_ON;
	else
		sc->sc_flags |= SC_OP_LED_ON;
}

992 993 994 995 996
static void ath_led_brightness(struct led_classdev *led_cdev,
			       enum led_brightness brightness)
{
	struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
	struct ath_softc *sc = led->sc;
997

998 999 1000
	switch (brightness) {
	case LED_OFF:
		if (led->led_type == ATH_LED_ASSOC ||
1001
		    led->led_type == ATH_LED_RADIO) {
1002
			ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1003
				(led->led_type == ATH_LED_RADIO));
1004
			sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1005 1006 1007 1008 1009
			if (led->led_type == ATH_LED_RADIO)
				sc->sc_flags &= ~SC_OP_LED_ON;
		} else {
			sc->led_off_cnt++;
		}
1010 1011
		break;
	case LED_FULL:
1012
		if (led->led_type == ATH_LED_ASSOC) {
1013
			sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1014 1015
			ieee80211_queue_delayed_work(sc->hw,
						     &sc->ath_led_blink_work, 0);
1016
		} else if (led->led_type == ATH_LED_RADIO) {
1017
			ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1018 1019 1020 1021
			sc->sc_flags |= SC_OP_LED_ON;
		} else {
			sc->led_on_cnt++;
		}
1022 1023 1024
		break;
	default:
		break;
1025
	}
1026
}
1027

1028 1029 1030 1031
static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
			    char *trigger)
{
	int ret;
1032

1033 1034 1035 1036
	led->sc = sc;
	led->led_cdev.name = led->name;
	led->led_cdev.default_trigger = trigger;
	led->led_cdev.brightness_set = ath_led_brightness;
1037

1038 1039 1040 1041 1042 1043 1044 1045
	ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
	if (ret)
		DPRINTF(sc, ATH_DBG_FATAL,
			"Failed to register led:%s", led->name);
	else
		led->registered = 1;
	return ret;
}
1046

1047 1048 1049 1050 1051
static void ath_unregister_led(struct ath_led *led)
{
	if (led->registered) {
		led_classdev_unregister(&led->led_cdev);
		led->registered = 0;
1052 1053 1054
	}
}

1055
static void ath_deinit_leds(struct ath_softc *sc)
1056
{
1057 1058 1059 1060 1061
	ath_unregister_led(&sc->assoc_led);
	sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
	ath_unregister_led(&sc->tx_led);
	ath_unregister_led(&sc->rx_led);
	ath_unregister_led(&sc->radio_led);
1062
	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1063
}
1064

1065 1066 1067 1068
static void ath_init_leds(struct ath_softc *sc)
{
	char *trigger;
	int ret;
1069

1070 1071 1072 1073 1074
	if (AR_SREV_9287(sc->sc_ah))
		sc->sc_ah->led_pin = ATH_LED_PIN_9287;
	else
		sc->sc_ah->led_pin = ATH_LED_PIN_DEF;

1075
	/* Configure gpio 1 for output */
1076
	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1077 1078
			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
	/* LED off, active low */
1079
	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
S
Sujith 已提交
1080

1081 1082
	INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);

1083 1084
	trigger = ieee80211_get_radio_led_name(sc->hw);
	snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
D
Danny Kukawka 已提交
1085
		"ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1086 1087 1088 1089
	ret = ath_register_led(sc, &sc->radio_led, trigger);
	sc->radio_led.led_type = ATH_LED_RADIO;
	if (ret)
		goto fail;
S
Sujith 已提交
1090

1091 1092
	trigger = ieee80211_get_assoc_led_name(sc->hw);
	snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
D
Danny Kukawka 已提交
1093
		"ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1094 1095 1096 1097
	ret = ath_register_led(sc, &sc->assoc_led, trigger);
	sc->assoc_led.led_type = ATH_LED_ASSOC;
	if (ret)
		goto fail;
1098

1099 1100
	trigger = ieee80211_get_tx_led_name(sc->hw);
	snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
D
Danny Kukawka 已提交
1101
		"ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1102 1103 1104 1105
	ret = ath_register_led(sc, &sc->tx_led, trigger);
	sc->tx_led.led_type = ATH_LED_TX;
	if (ret)
		goto fail;
1106

1107 1108
	trigger = ieee80211_get_rx_led_name(sc->hw);
	snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
D
Danny Kukawka 已提交
1109
		"ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1110 1111 1112 1113
	ret = ath_register_led(sc, &sc->rx_led, trigger);
	sc->rx_led.led_type = ATH_LED_RX;
	if (ret)
		goto fail;
1114

1115 1116 1117
	return;

fail:
1118
	cancel_delayed_work_sync(&sc->ath_led_blink_work);
1119
	ath_deinit_leds(sc);
1120 1121
}

1122
void ath_radio_enable(struct ath_softc *sc)
1123
{
1124
	struct ath_hw *ah = sc->sc_ah;
1125 1126
	struct ieee80211_channel *channel = sc->hw->conf.channel;
	int r;
1127

1128
	ath9k_ps_wakeup(sc);
1129
	ath9k_hw_configpcipowersave(ah, 0);
1130

1131 1132 1133
	if (!ah->curchan)
		ah->curchan = ath_get_curchannel(sc, sc->hw);

1134
	spin_lock_bh(&sc->sc_resetlock);
1135
	r = ath9k_hw_reset(ah, ah->curchan, false);
1136
	if (r) {
1137
		DPRINTF(sc, ATH_DBG_FATAL,
1138
			"Unable to reset channel %u (%uMhz) ",
1139
			"reset status %d\n",
1140
			channel->center_freq, r);
1141 1142 1143 1144 1145 1146
	}
	spin_unlock_bh(&sc->sc_resetlock);

	ath_update_txpow(sc);
	if (ath_startrecv(sc) != 0) {
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1147
			"Unable to restart recv logic\n");
1148 1149 1150 1151
		return;
	}

	if (sc->sc_flags & SC_OP_BEACONS)
1152
		ath_beacon_config(sc, NULL);	/* restart beacons */
1153 1154

	/* Re-Enable  interrupts */
1155
	ath9k_hw_set_interrupts(ah, sc->imask);
1156 1157

	/* Enable LED */
1158
	ath9k_hw_cfg_output(ah, ah->led_pin,
1159
			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1160
	ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1161 1162

	ieee80211_wake_queues(sc->hw);
1163
	ath9k_ps_restore(sc);
1164 1165
}

1166
void ath_radio_disable(struct ath_softc *sc)
1167
{
1168
	struct ath_hw *ah = sc->sc_ah;
1169 1170
	struct ieee80211_channel *channel = sc->hw->conf.channel;
	int r;
1171

1172
	ath9k_ps_wakeup(sc);
1173 1174 1175
	ieee80211_stop_queues(sc->hw);

	/* Disable LED */
1176 1177
	ath9k_hw_set_gpio(ah, ah->led_pin, 1);
	ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1178 1179 1180 1181

	/* Disable interrupts */
	ath9k_hw_set_interrupts(ah, 0);

1182
	ath_drain_all_txq(sc, false);	/* clear pending tx frames */
1183 1184 1185
	ath_stoprecv(sc);		/* turn off frame recv */
	ath_flushrecv(sc);		/* flush recv queue */

1186 1187 1188
	if (!ah->curchan)
		ah->curchan = ath_get_curchannel(sc, sc->hw);

1189
	spin_lock_bh(&sc->sc_resetlock);
1190
	r = ath9k_hw_reset(ah, ah->curchan, false);
1191
	if (r) {
1192
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1193
			"Unable to reset channel %u (%uMhz) "
1194
			"reset status %d\n",
1195
			channel->center_freq, r);
1196 1197 1198 1199
	}
	spin_unlock_bh(&sc->sc_resetlock);

	ath9k_hw_phy_disable(ah);
1200
	ath9k_hw_configpcipowersave(ah, 1);
1201
	ath9k_ps_restore(sc);
1202
	ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1203 1204
}

1205 1206 1207 1208
/*******************/
/*	Rfkill	   */
/*******************/

1209 1210
static bool ath_is_rfkill_set(struct ath_softc *sc)
{
1211
	struct ath_hw *ah = sc->sc_ah;
1212

1213 1214
	return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
				  ah->rfkill_polarity;
1215 1216
}

1217
static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1218
{
1219 1220
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
J
Johannes Berg 已提交
1221
	bool blocked = !!ath_is_rfkill_set(sc);
1222

1223 1224 1225
	wiphy_rfkill_set_hw_state(hw->wiphy, blocked);

	if (blocked)
J
Johannes Berg 已提交
1226 1227 1228
		ath_radio_disable(sc);
	else
		ath_radio_enable(sc);
1229 1230
}

1231
static void ath_start_rfkill_poll(struct ath_softc *sc)
1232
{
1233
	struct ath_hw *ah = sc->sc_ah;
S
Sujith 已提交
1234

1235 1236
	if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
		wiphy_rfkill_start_polling(sc->hw->wiphy);
S
Sujith 已提交
1237
}
1238

1239
void ath_cleanup(struct ath_softc *sc)
1240 1241 1242 1243
{
	ath_detach(sc);
	free_irq(sc->irq, sc);
	ath_bus_cleanup(sc);
1244
	kfree(sc->sec_wiphy);
1245 1246 1247
	ieee80211_free_hw(sc->hw);
}

1248
void ath_detach(struct ath_softc *sc)
1249
{
1250
	struct ieee80211_hw *hw = sc->hw;
S
Sujith 已提交
1251
	int i = 0;
1252

1253 1254
	ath9k_ps_wakeup(sc);

S
Sujith 已提交
1255
	DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1256

1257 1258
	ath_deinit_leds(sc);

1259 1260 1261 1262 1263 1264 1265 1266
	for (i = 0; i < sc->num_sec_wiphy; i++) {
		struct ath_wiphy *aphy = sc->sec_wiphy[i];
		if (aphy == NULL)
			continue;
		sc->sec_wiphy[i] = NULL;
		ieee80211_unregister_hw(aphy->hw);
		ieee80211_free_hw(aphy->hw);
	}
1267
	ieee80211_unregister_hw(hw);
1268 1269
	ath_rx_cleanup(sc);
	ath_tx_cleanup(sc);
1270

S
Sujith 已提交
1271 1272
	tasklet_kill(&sc->intr_tq);
	tasklet_kill(&sc->bcon_tasklet);
1273

S
Sujith 已提交
1274 1275
	if (!(sc->sc_flags & SC_OP_INVALID))
		ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1276

S
Sujith 已提交
1277 1278 1279
	/* cleanup tx queues */
	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
		if (ATH_TXQ_SETUP(sc, i))
S
Sujith 已提交
1280
			ath_tx_cleanupq(sc, &sc->tx.txq[i]);
S
Sujith 已提交
1281 1282

	ath9k_hw_detach(sc->sc_ah);
1283
	sc->sc_ah = NULL;
1284
	ath9k_exit_debug(sc);
1285 1286
}

1287 1288 1289 1290 1291 1292
static int ath9k_reg_notifier(struct wiphy *wiphy,
			      struct regulatory_request *request)
{
	struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
1293
	struct ath_regulatory *reg = &sc->common.regulatory;
1294 1295 1296 1297

	return ath_reg_notifier_apply(wiphy, request, reg);
}

1298 1299 1300 1301 1302 1303 1304
/*
 * Initialize and fill ath_softc, ath_sofct is the
 * "Software Carrier" struct. Historically it has existed
 * to allow the separation between hardware specific
 * variables (now in ath_hw) and driver specific variables.
 */
static int ath_init_softc(u16 devid, struct ath_softc *sc)
S
Sujith 已提交
1305
{
1306
	struct ath_hw *ah = NULL;
1307
	int r = 0, i;
S
Sujith 已提交
1308 1309 1310 1311
	int csz = 0;

	/* XXX: hardware will not be ready until ath_open() being called */
	sc->sc_flags |= SC_OP_INVALID;
1312

1313 1314
	if (ath9k_init_debug(sc) < 0)
		printk(KERN_ERR "Unable to create debugfs files\n");
S
Sujith 已提交
1315

1316
	spin_lock_init(&sc->wiphy_lock);
S
Sujith 已提交
1317
	spin_lock_init(&sc->sc_resetlock);
1318
	spin_lock_init(&sc->sc_serial_rw);
1319
	spin_lock_init(&sc->ani_lock);
1320
	spin_lock_init(&sc->sc_pm_lock);
1321
	mutex_init(&sc->mutex);
S
Sujith 已提交
1322
	tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
S
Sujith 已提交
1323
	tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
S
Sujith 已提交
1324 1325 1326 1327 1328 1329
		     (unsigned long)sc);

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
1330
	ath_read_cachesize(sc, &csz);
S
Sujith 已提交
1331
	/* XXX assert csz is non-zero */
1332
	sc->common.cachelsz = csz << 2;	/* convert to bytes */
S
Sujith 已提交
1333

1334 1335 1336 1337 1338 1339 1340
	ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
	if (!ah) {
		r = -ENOMEM;
		goto bad_no_ah;
	}

	ah->ah_sc = sc;
1341
	ah->hw_version.devid = devid;
1342
	sc->sc_ah = ah;
1343

1344
	r = ath9k_hw_init(ah);
1345
	if (r) {
S
Sujith 已提交
1346
		DPRINTF(sc, ATH_DBG_FATAL,
1347
			"Unable to initialize hardware; "
1348
			"initialization status: %d\n", r);
S
Sujith 已提交
1349 1350 1351 1352
		goto bad;
	}

	/* Get the hardware key cache size. */
1353
	sc->keymax = ah->caps.keycache_size;
1354
	if (sc->keymax > ATH_KEYMAX) {
S
Sujith 已提交
1355
		DPRINTF(sc, ATH_DBG_ANY,
S
Sujith 已提交
1356
			"Warning, using only %u entries in %u key cache\n",
1357 1358
			ATH_KEYMAX, sc->keymax);
		sc->keymax = ATH_KEYMAX;
S
Sujith 已提交
1359 1360 1361 1362 1363 1364
	}

	/*
	 * Reset the key cache since some parts do not
	 * reset the contents on initial power up.
	 */
1365
	for (i = 0; i < sc->keymax; i++)
S
Sujith 已提交
1366 1367 1368
		ath9k_hw_keyreset(ah, (u16) i);

	/* default to MONITOR mode */
1369
	sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1370

S
Sujith 已提交
1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382
	/* Setup rate tables */

	ath_rate_attach(sc);
	ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
	ath_setup_rates(sc, IEEE80211_BAND_5GHZ);

	/*
	 * Allocate hardware transmit queues: one queue for
	 * beacon frames and one data queue for each QoS
	 * priority.  Note that the hal handles reseting
	 * these queues at the needed time.
	 */
S
Sujith 已提交
1383 1384
	sc->beacon.beaconq = ath_beaconq_setup(ah);
	if (sc->beacon.beaconq == -1) {
S
Sujith 已提交
1385
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1386
			"Unable to setup a beacon xmit queue\n");
1387
		r = -EIO;
S
Sujith 已提交
1388 1389
		goto bad2;
	}
S
Sujith 已提交
1390 1391
	sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
	if (sc->beacon.cabq == NULL) {
S
Sujith 已提交
1392
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1393
			"Unable to setup CAB xmit queue\n");
1394
		r = -EIO;
S
Sujith 已提交
1395 1396 1397
		goto bad2;
	}

1398
	sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
S
Sujith 已提交
1399 1400
	ath_cabq_update(sc);

S
Sujith 已提交
1401 1402
	for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
		sc->tx.hwq_map[i] = -1;
S
Sujith 已提交
1403 1404 1405 1406 1407

	/* Setup data queues */
	/* NB: ensure BK queue is the lowest priority h/w queue */
	if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1408
			"Unable to setup xmit queue for BK traffic\n");
1409
		r = -EIO;
S
Sujith 已提交
1410 1411 1412 1413 1414
		goto bad2;
	}

	if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1415
			"Unable to setup xmit queue for BE traffic\n");
1416
		r = -EIO;
S
Sujith 已提交
1417 1418 1419 1420
		goto bad2;
	}
	if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1421
			"Unable to setup xmit queue for VI traffic\n");
1422
		r = -EIO;
S
Sujith 已提交
1423 1424 1425 1426
		goto bad2;
	}
	if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1427
			"Unable to setup xmit queue for VO traffic\n");
1428
		r = -EIO;
S
Sujith 已提交
1429 1430 1431 1432 1433 1434
		goto bad2;
	}

	/* Initializes the noise floor to a reasonable default value.
	 * Later on this will be updated during ANI processing. */

1435 1436
	sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
	setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
S
Sujith 已提交
1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461

	if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
				   ATH9K_CIPHER_TKIP, NULL)) {
		/*
		 * Whether we should enable h/w TKIP MIC.
		 * XXX: if we don't support WME TKIP MIC, then we wouldn't
		 * report WMM capable, so it's always safe to turn on
		 * TKIP MIC in this case.
		 */
		ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
				       0, 1, NULL);
	}

	/*
	 * Check whether the separate key cache entries
	 * are required to handle both tx+rx MIC keys.
	 * With split mic keys the number of stations is limited
	 * to 27 otherwise 59.
	 */
	if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
				   ATH9K_CIPHER_TKIP, NULL)
	    && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
				      ATH9K_CIPHER_MIC, NULL)
	    && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
				      0, NULL))
1462
		sc->splitmic = 1;
S
Sujith 已提交
1463 1464 1465 1466 1467 1468

	/* turn on mcast key search if possible */
	if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
		(void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
					     1, NULL);

1469
	sc->config.txpowlimit = ATH_TXPOWER_MAX;
S
Sujith 已提交
1470 1471

	/* 11n Capabilities */
1472
	if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
S
Sujith 已提交
1473 1474 1475 1476
		sc->sc_flags |= SC_OP_TXAGGR;
		sc->sc_flags |= SC_OP_RXAGGR;
	}

1477 1478
	sc->tx_chainmask = ah->caps.tx_chainmask;
	sc->rx_chainmask = ah->caps.rx_chainmask;
S
Sujith 已提交
1479 1480

	ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
S
Sujith 已提交
1481
	sc->rx.defant = ath9k_hw_getdefantenna(ah);
S
Sujith 已提交
1482

1483
	if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1484
		memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
S
Sujith 已提交
1485

S
Sujith 已提交
1486
	sc->beacon.slottime = ATH9K_SLOT_TIME_9;	/* default to short slot time */
S
Sujith 已提交
1487 1488

	/* initialize beacon slots */
1489
	for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1490
		sc->beacon.bslot[i] = NULL;
1491 1492
		sc->beacon.bslot_aphy[i] = NULL;
	}
S
Sujith 已提交
1493 1494 1495

	/* setup channels and rates */

1496
	sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
S
Sujith 已提交
1497 1498 1499
	sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
		sc->rates[IEEE80211_BAND_2GHZ];
	sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1500 1501
	sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
		ARRAY_SIZE(ath9k_2ghz_chantable);
S
Sujith 已提交
1502

1503
	if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1504
		sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
S
Sujith 已提交
1505 1506 1507
		sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
			sc->rates[IEEE80211_BAND_5GHZ];
		sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1508 1509
		sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
			ARRAY_SIZE(ath9k_5ghz_chantable);
S
Sujith 已提交
1510 1511
	}

1512
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1513 1514
		ath9k_hw_btcoex_enable(sc->sc_ah);

S
Sujith 已提交
1515 1516 1517 1518 1519
	return 0;
bad2:
	/* cleanup tx queues */
	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
		if (ATH_TXQ_SETUP(sc, i))
S
Sujith 已提交
1520
			ath_tx_cleanupq(sc, &sc->tx.txq[i]);
S
Sujith 已提交
1521
bad:
1522
	ath9k_hw_detach(ah);
1523
	sc->sc_ah = NULL;
1524
bad_no_ah:
1525
	ath9k_exit_debug(sc);
S
Sujith 已提交
1526

1527
	return r;
S
Sujith 已提交
1528 1529
}

1530
void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1531
{
S
Sujith 已提交
1532 1533 1534
	hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
		IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
		IEEE80211_HW_SIGNAL_DBM |
1535 1536
		IEEE80211_HW_AMPDU_AGGREGATION |
		IEEE80211_HW_SUPPORTS_PS |
1537 1538
		IEEE80211_HW_PS_NULLFUNC_STACK |
		IEEE80211_HW_SPECTRUM_MGMT;
1539

1540
	if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1541 1542
		hw->flags |= IEEE80211_HW_MFP_CAPABLE;

S
Sujith 已提交
1543 1544 1545
	hw->wiphy->interface_modes =
		BIT(NL80211_IFTYPE_AP) |
		BIT(NL80211_IFTYPE_STATION) |
1546 1547
		BIT(NL80211_IFTYPE_ADHOC) |
		BIT(NL80211_IFTYPE_MESH_POINT);
1548

1549
	hw->queues = 4;
S
Sujith 已提交
1550
	hw->max_rates = 4;
1551
	hw->channel_change_time = 5000;
1552
	hw->max_listen_interval = 10;
1553 1554
	/* Hardware supports 10 but we use 4 */
	hw->max_rate_tries = 4;
1555
	hw->sta_data_size = sizeof(struct ath_node);
1556
	hw->vif_data_size = sizeof(struct ath_vif);
1557

1558
	hw->rate_control_algorithm = "ath9k_rate_control";
1559

1560 1561 1562 1563 1564 1565 1566
	hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
		&sc->sbands[IEEE80211_BAND_2GHZ];
	if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
		hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
			&sc->sbands[IEEE80211_BAND_5GHZ];
}

1567 1568
/* Device driver core initialization */
int ath_init_device(u16 devid, struct ath_softc *sc)
1569 1570 1571
{
	struct ieee80211_hw *hw = sc->hw;
	int error = 0, i;
1572
	struct ath_regulatory *reg;
1573 1574 1575

	DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");

1576
	error = ath_init_softc(devid, sc);
1577 1578 1579 1580 1581 1582 1583 1584 1585
	if (error != 0)
		return error;

	/* get mac address from hardware and set in mac80211 */

	SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);

	ath_set_hw_capab(sc, hw);

1586
	error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
1587 1588 1589 1590
			      ath9k_reg_notifier);
	if (error)
		return error;

1591
	reg = &sc->common.regulatory;
1592

1593
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1594
		setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1595
		if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1596
			setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
S
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1597 1598
	}

1599 1600 1601
	/* initialize tx/rx engine */
	error = ath_tx_init(sc, ATH_TXBUF);
	if (error != 0)
1602
		goto error_attach;
1603

1604 1605
	error = ath_rx_init(sc, ATH_RXBUF);
	if (error != 0)
1606
		goto error_attach;
1607

1608
	INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1609 1610
	INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
	sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1611

1612
	error = ieee80211_register_hw(hw);
1613

1614
	if (!ath_is_world_regd(reg)) {
1615
		error = regulatory_hint(hw->wiphy, reg->alpha2);
1616 1617 1618
		if (error)
			goto error_attach;
	}
1619

1620 1621
	/* Initialize LED control */
	ath_init_leds(sc);
1622

1623
	ath_start_rfkill_poll(sc);
1624

1625
	return 0;
1626 1627 1628 1629 1630 1631 1632 1633

error_attach:
	/* cleanup tx queues */
	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
		if (ATH_TXQ_SETUP(sc, i))
			ath_tx_cleanupq(sc, &sc->tx.txq[i]);

	ath9k_hw_detach(sc->sc_ah);
1634
	sc->sc_ah = NULL;
1635 1636
	ath9k_exit_debug(sc);

1637
	return error;
1638 1639
}

S
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1640 1641
int ath_reset(struct ath_softc *sc, bool retry_tx)
{
1642
	struct ath_hw *ah = sc->sc_ah;
1643
	struct ieee80211_hw *hw = sc->hw;
1644
	int r;
S
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1645 1646

	ath9k_hw_set_interrupts(ah, 0);
1647
	ath_drain_all_txq(sc, retry_tx);
S
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1648 1649 1650 1651
	ath_stoprecv(sc);
	ath_flushrecv(sc);

	spin_lock_bh(&sc->sc_resetlock);
1652
	r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1653
	if (r)
S
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1654
		DPRINTF(sc, ATH_DBG_FATAL,
1655
			"Unable to reset hardware; reset status %d\n", r);
S
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1656 1657 1658
	spin_unlock_bh(&sc->sc_resetlock);

	if (ath_startrecv(sc) != 0)
S
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1659
		DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
S
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1660 1661 1662 1663 1664 1665

	/*
	 * We may be doing a reset in response to a request
	 * that changes the channel so update any state that
	 * might change as a result.
	 */
1666
	ath_cache_conf_rate(sc, &hw->conf);
S
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1667 1668 1669 1670

	ath_update_txpow(sc);

	if (sc->sc_flags & SC_OP_BEACONS)
1671
		ath_beacon_config(sc, NULL);	/* restart beacons */
S
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1672

1673
	ath9k_hw_set_interrupts(ah, sc->imask);
S
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1674 1675 1676 1677 1678

	if (retry_tx) {
		int i;
		for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
			if (ATH_TXQ_SETUP(sc, i)) {
S
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1679 1680 1681
				spin_lock_bh(&sc->tx.txq[i].axq_lock);
				ath_txq_schedule(sc, &sc->tx.txq[i]);
				spin_unlock_bh(&sc->tx.txq[i].axq_lock);
S
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1682 1683 1684 1685
			}
		}
	}

1686
	return r;
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1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706
}

/*
 *  This function will allocate both the DMA descriptor structure, and the
 *  buffers it contains.  These are used to contain the descriptors used
 *  by the system.
*/
int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
		      struct list_head *head, const char *name,
		      int nbuf, int ndesc)
{
#define	DS2PHYS(_dd, _ds)						\
	((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)

	struct ath_desc *ds;
	struct ath_buf *bf;
	int i, bsize, error;

S
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1707 1708
	DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
		name, nbuf, ndesc);
S
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1709

1710
	INIT_LIST_HEAD(head);
S
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1711 1712
	/* ath_desc must be a multiple of DWORDs */
	if ((sizeof(struct ath_desc) % 4) != 0) {
S
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1713
		DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
S
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1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725
		ASSERT((sizeof(struct ath_desc) % 4) == 0);
		error = -ENOMEM;
		goto fail;
	}

	dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;

	/*
	 * Need additional DMA memory because we can't use
	 * descriptors that cross the 4K page boundary. Assume
	 * one skipped descriptor per 4K page.
	 */
1726
	if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
S
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1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739
		u32 ndesc_skipped =
			ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
		u32 dma_len;

		while (ndesc_skipped) {
			dma_len = ndesc_skipped * sizeof(struct ath_desc);
			dd->dd_desc_len += dma_len;

			ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
		};
	}

	/* allocate descriptors */
1740
	dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1741
					 &dd->dd_desc_paddr, GFP_KERNEL);
S
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1742 1743 1744 1745 1746
	if (dd->dd_desc == NULL) {
		error = -ENOMEM;
		goto fail;
	}
	ds = dd->dd_desc;
S
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1747
	DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1748
		name, ds, (u32) dd->dd_desc_len,
S
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1749 1750 1751 1752
		ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);

	/* allocate buffers */
	bsize = sizeof(struct ath_buf) * nbuf;
1753
	bf = kzalloc(bsize, GFP_KERNEL);
S
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1754 1755 1756 1757 1758 1759 1760 1761 1762 1763
	if (bf == NULL) {
		error = -ENOMEM;
		goto fail2;
	}
	dd->dd_bufptr = bf;

	for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
		bf->bf_desc = ds;
		bf->bf_daddr = DS2PHYS(dd, ds);

1764
		if (!(sc->sc_ah->caps.hw_caps &
S
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1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784
		      ATH9K_HW_CAP_4KB_SPLITTRANS)) {
			/*
			 * Skip descriptor addresses which can cause 4KB
			 * boundary crossing (addr + length) with a 32 dword
			 * descriptor fetch.
			 */
			while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
				ASSERT((caddr_t) bf->bf_desc <
				       ((caddr_t) dd->dd_desc +
					dd->dd_desc_len));

				ds += ndesc;
				bf->bf_desc = ds;
				bf->bf_daddr = DS2PHYS(dd, ds);
			}
		}
		list_add_tail(&bf->list, head);
	}
	return 0;
fail2:
1785 1786
	dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
			  dd->dd_desc_paddr);
S
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1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798
fail:
	memset(dd, 0, sizeof(*dd));
	return error;
#undef ATH_DESC_4KB_BOUND_CHECK
#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
#undef DS2PHYS
}

void ath_descdma_cleanup(struct ath_softc *sc,
			 struct ath_descdma *dd,
			 struct list_head *head)
{
1799 1800
	dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
			  dd->dd_desc_paddr);
S
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1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812

	INIT_LIST_HEAD(head);
	kfree(dd->dd_bufptr);
	memset(dd, 0, sizeof(*dd));
}

int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
{
	int qnum;

	switch (queue) {
	case 0:
S
Sujith 已提交
1813
		qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
S
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1814 1815
		break;
	case 1:
S
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1816
		qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
S
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1817 1818
		break;
	case 2:
S
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1819
		qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
S
Sujith 已提交
1820 1821
		break;
	case 3:
S
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1822
		qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
S
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1823 1824
		break;
	default:
S
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1825
		qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
S
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1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856
		break;
	}

	return qnum;
}

int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
{
	int qnum;

	switch (queue) {
	case ATH9K_WME_AC_VO:
		qnum = 0;
		break;
	case ATH9K_WME_AC_VI:
		qnum = 1;
		break;
	case ATH9K_WME_AC_BE:
		qnum = 2;
		break;
	case ATH9K_WME_AC_BK:
		qnum = 3;
		break;
	default:
		qnum = -1;
		break;
	}

	return qnum;
}

1857 1858
/* XXX: Remove me once we don't depend on ath9k_channel for all
 * this redundant data */
1859 1860
void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
			   struct ath9k_channel *ichan)
1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886
{
	struct ieee80211_channel *chan = hw->conf.channel;
	struct ieee80211_conf *conf = &hw->conf;

	ichan->channel = chan->center_freq;
	ichan->chan = chan;

	if (chan->band == IEEE80211_BAND_2GHZ) {
		ichan->chanmode = CHANNEL_G;
		ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
	} else {
		ichan->chanmode = CHANNEL_A;
		ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
	}

	sc->tx_chan_width = ATH9K_HT_MACMODE_20;

	if (conf_is_ht(conf)) {
		if (conf_is_ht40(conf))
			sc->tx_chan_width = ATH9K_HT_MACMODE_2040;

		ichan->chanmode = ath_get_extchanmode(sc, chan,
					    conf->channel_type);
	}
}

S
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1887 1888 1889 1890
/**********************/
/* mac80211 callbacks */
/**********************/

1891
static int ath9k_start(struct ieee80211_hw *hw)
1892
{
1893 1894
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
1895
	struct ieee80211_channel *curchan = hw->conf.channel;
S
Sujith 已提交
1896
	struct ath9k_channel *init_channel;
1897
	int r;
1898

S
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1899 1900
	DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
		"initial channel: %d MHz\n", curchan->center_freq);
1901

1902 1903
	mutex_lock(&sc->mutex);

1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924
	if (ath9k_wiphy_started(sc)) {
		if (sc->chan_idx == curchan->hw_value) {
			/*
			 * Already on the operational channel, the new wiphy
			 * can be marked active.
			 */
			aphy->state = ATH_WIPHY_ACTIVE;
			ieee80211_wake_queues(hw);
		} else {
			/*
			 * Another wiphy is on another channel, start the new
			 * wiphy in paused state.
			 */
			aphy->state = ATH_WIPHY_PAUSED;
			ieee80211_stop_queues(hw);
		}
		mutex_unlock(&sc->mutex);
		return 0;
	}
	aphy->state = ATH_WIPHY_ACTIVE;

1925
	/* setup initial channel */
1926

1927
	sc->chan_idx = curchan->hw_value;
1928

1929
	init_channel = ath_get_curchannel(sc, hw);
S
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1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941

	/* Reset SERDES registers */
	ath9k_hw_configpcipowersave(sc->sc_ah, 0);

	/*
	 * The basic interface to setting the hardware in a good
	 * state is ``reset''.  On return the hardware is known to
	 * be powered up and with interrupts disabled.  This must
	 * be followed by initialization of the appropriate bits
	 * and then setup of the interrupt mask.
	 */
	spin_lock_bh(&sc->sc_resetlock);
1942 1943
	r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
	if (r) {
S
Sujith 已提交
1944
		DPRINTF(sc, ATH_DBG_FATAL,
1945
			"Unable to reset hardware; reset status %d "
1946 1947
			"(freq %u MHz)\n", r,
			curchan->center_freq);
S
Sujith 已提交
1948
		spin_unlock_bh(&sc->sc_resetlock);
1949
		goto mutex_unlock;
S
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1950 1951 1952 1953 1954 1955 1956 1957
	}
	spin_unlock_bh(&sc->sc_resetlock);

	/*
	 * This is needed only to setup initial state
	 * but it's best done after a reset.
	 */
	ath_update_txpow(sc);
1958

S
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1959 1960 1961 1962 1963 1964 1965 1966
	/*
	 * Setup the hardware after reset:
	 * The receive engine is set going.
	 * Frame transmit is handled entirely
	 * in the frame output path; there's nothing to do
	 * here except setup the interrupt mask.
	 */
	if (ath_startrecv(sc) != 0) {
1967
		DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1968 1969
		r = -EIO;
		goto mutex_unlock;
1970
	}
1971

S
Sujith 已提交
1972
	/* Setup our intr mask. */
1973
	sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
S
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1974 1975 1976
		| ATH9K_INT_RXEOL | ATH9K_INT_RXORN
		| ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;

1977
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1978
		sc->imask |= ATH9K_INT_GTT;
S
Sujith 已提交
1979

1980
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1981
		sc->imask |= ATH9K_INT_CST;
S
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1982

1983
	ath_cache_conf_rate(sc, &hw->conf);
S
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1984 1985 1986 1987

	sc->sc_flags &= ~SC_OP_INVALID;

	/* Disable BMISS interrupt when we're not associated */
1988 1989
	sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
	ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
S
Sujith 已提交
1990

1991
	ieee80211_wake_queues(hw);
S
Sujith 已提交
1992

1993
	ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
1994

1995 1996 1997
mutex_unlock:
	mutex_unlock(&sc->mutex);

1998
	return r;
1999 2000
}

2001 2002
static int ath9k_tx(struct ieee80211_hw *hw,
		    struct sk_buff *skb)
2003
{
2004
	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2005 2006
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2007
	struct ath_tx_control txctl;
2008
	int hdrlen, padsize;
2009

2010
	if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2011 2012 2013 2014 2015
		printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
		       "%d\n", wiphy_name(hw->wiphy), aphy->state);
		goto exit;
	}

2016
	if (sc->ps_enabled) {
2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030
		struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
		/*
		 * mac80211 does not set PM field for normal data frames, so we
		 * need to update that based on the current PS mode.
		 */
		if (ieee80211_is_data(hdr->frame_control) &&
		    !ieee80211_is_nullfunc(hdr->frame_control) &&
		    !ieee80211_has_pm(hdr->frame_control)) {
			DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
				"while in PS mode\n");
			hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
		}
	}

2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055
	if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
		/*
		 * We are using PS-Poll and mac80211 can request TX while in
		 * power save mode. Need to wake up hardware for the TX to be
		 * completed and if needed, also for RX of buffered frames.
		 */
		struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
		ath9k_ps_wakeup(sc);
		ath9k_hw_setrxabort(sc->sc_ah, 0);
		if (ieee80211_is_pspoll(hdr->frame_control)) {
			DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
				"buffered frame\n");
			sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
		} else {
			DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
			sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
		}
		/*
		 * The actual restore operation will happen only after
		 * the sc_flags bit is cleared. We are just dropping
		 * the ps_usecount here.
		 */
		ath9k_ps_restore(sc);
	}

2056
	memset(&txctl, 0, sizeof(struct ath_tx_control));
2057

2058 2059 2060 2061 2062 2063 2064 2065
	/*
	 * As a temporary workaround, assign seq# here; this will likely need
	 * to be cleaned up to work better with Beacon transmission and virtual
	 * BSSes.
	 */
	if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
		struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
		if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
S
Sujith 已提交
2066
			sc->tx.seq_no += 0x10;
2067
		hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
S
Sujith 已提交
2068
		hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2069
	}
2070

2071 2072 2073 2074 2075 2076 2077 2078 2079 2080
	/* Add the padding after the header if this is not already done */
	hdrlen = ieee80211_get_hdrlen_from_skb(skb);
	if (hdrlen & 3) {
		padsize = hdrlen % 4;
		if (skb_headroom(skb) < padsize)
			return -1;
		skb_push(skb, padsize);
		memmove(skb->data, skb->data + padsize, hdrlen);
	}

2081 2082 2083 2084 2085 2086
	/* Check if a tx queue is available */

	txctl.txq = ath_test_get_txq(sc, skb);
	if (!txctl.txq)
		goto exit;

S
Sujith 已提交
2087
	DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2088

2089
	if (ath_tx_start(hw, skb, &txctl) != 0) {
S
Sujith 已提交
2090
		DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2091
		goto exit;
2092 2093
	}

2094 2095 2096
	return 0;
exit:
	dev_kfree_skb_any(skb);
2097
	return 0;
2098 2099
}

2100
static void ath9k_stop(struct ieee80211_hw *hw)
2101
{
2102 2103
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2104

S
Sujith 已提交
2105 2106
	mutex_lock(&sc->mutex);

2107 2108
	aphy->state = ATH_WIPHY_INACTIVE;

2109 2110 2111 2112 2113 2114 2115 2116
	cancel_delayed_work_sync(&sc->ath_led_blink_work);
	cancel_delayed_work_sync(&sc->tx_complete_work);

	if (!sc->num_sec_wiphy) {
		cancel_delayed_work_sync(&sc->wiphy_work);
		cancel_work_sync(&sc->chan_work);
	}

S
Sujith 已提交
2117
	if (sc->sc_flags & SC_OP_INVALID) {
S
Sujith 已提交
2118
		DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
S
Sujith 已提交
2119
		mutex_unlock(&sc->mutex);
S
Sujith 已提交
2120 2121
		return;
	}
2122

2123 2124 2125 2126 2127
	if (ath9k_wiphy_started(sc)) {
		mutex_unlock(&sc->mutex);
		return; /* another wiphy still in use */
	}

S
Sujith 已提交
2128 2129 2130 2131 2132
	/* make sure h/w will not generate any interrupt
	 * before setting the invalid flag. */
	ath9k_hw_set_interrupts(sc->sc_ah, 0);

	if (!(sc->sc_flags & SC_OP_INVALID)) {
2133
		ath_drain_all_txq(sc, false);
S
Sujith 已提交
2134 2135 2136
		ath_stoprecv(sc);
		ath9k_hw_phy_disable(sc->sc_ah);
	} else
S
Sujith 已提交
2137
		sc->rx.rxlink = NULL;
S
Sujith 已提交
2138

2139
	wiphy_rfkill_stop_polling(sc->hw->wiphy);
J
Johannes Berg 已提交
2140

S
Sujith 已提交
2141 2142 2143
	/* disable HAL and put h/w to sleep */
	ath9k_hw_disable(sc->sc_ah);
	ath9k_hw_configpcipowersave(sc->sc_ah, 1);
S
Sujith 已提交
2144
	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
S
Sujith 已提交
2145 2146

	sc->sc_flags |= SC_OP_INVALID;
2147

2148 2149
	mutex_unlock(&sc->mutex);

S
Sujith 已提交
2150
	DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2151 2152
}

2153 2154
static int ath9k_add_interface(struct ieee80211_hw *hw,
			       struct ieee80211_if_init_conf *conf)
2155
{
2156 2157
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2158
	struct ath_vif *avp = (void *)conf->vif->drv_priv;
2159
	enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2160
	int ret = 0;
2161

2162 2163
	mutex_lock(&sc->mutex);

2164 2165 2166 2167 2168 2169
	if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
	    sc->nvifs > 0) {
		ret = -ENOBUFS;
		goto out;
	}

2170
	switch (conf->type) {
2171
	case NL80211_IFTYPE_STATION:
2172
		ic_opmode = NL80211_IFTYPE_STATION;
2173
		break;
2174 2175
	case NL80211_IFTYPE_ADHOC:
	case NL80211_IFTYPE_AP:
2176
	case NL80211_IFTYPE_MESH_POINT:
2177 2178 2179 2180
		if (sc->nbcnvifs >= ATH_BCBUF) {
			ret = -ENOBUFS;
			goto out;
		}
2181
		ic_opmode = conf->type;
2182 2183 2184
		break;
	default:
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
2185
			"Interface type %d not yet supported\n", conf->type);
2186 2187
		ret = -EOPNOTSUPP;
		goto out;
2188 2189
	}

2190
	DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2191

2192
	/* Set the VIF opmode */
S
Sujith 已提交
2193 2194 2195
	avp->av_opmode = ic_opmode;
	avp->av_bslot = -1;

2196
	sc->nvifs++;
2197 2198 2199 2200

	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
		ath9k_set_bssid_mask(hw);

2201 2202 2203
	if (sc->nvifs > 1)
		goto out; /* skip global settings for secondary vif */

2204
	if (ic_opmode == NL80211_IFTYPE_AP) {
S
Sujith 已提交
2205
		ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2206 2207
		sc->sc_flags |= SC_OP_TSF_RESET;
	}
S
Sujith 已提交
2208 2209

	/* Set the device opmode */
2210
	sc->sc_ah->opmode = ic_opmode;
S
Sujith 已提交
2211

2212 2213 2214 2215
	/*
	 * Enable MIB interrupts when there are hardware phy counters.
	 * Note we only do this (at the moment) for station mode.
	 */
2216
	if ((conf->type == NL80211_IFTYPE_STATION) ||
2217 2218
	    (conf->type == NL80211_IFTYPE_ADHOC) ||
	    (conf->type == NL80211_IFTYPE_MESH_POINT)) {
S
Sujith 已提交
2219
		sc->imask |= ATH9K_INT_MIB;
2220 2221 2222
		sc->imask |= ATH9K_INT_TSFOOR;
	}

2223
	ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2224

2225 2226 2227
	if (conf->type == NL80211_IFTYPE_AP    ||
	    conf->type == NL80211_IFTYPE_ADHOC ||
	    conf->type == NL80211_IFTYPE_MONITOR)
S
Sujith 已提交
2228
		ath_start_ani(sc);
2229

2230
out:
2231
	mutex_unlock(&sc->mutex);
2232
	return ret;
2233 2234
}

2235 2236
static void ath9k_remove_interface(struct ieee80211_hw *hw,
				   struct ieee80211_if_init_conf *conf)
2237
{
2238 2239
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2240
	struct ath_vif *avp = (void *)conf->vif->drv_priv;
2241
	int i;
2242

S
Sujith 已提交
2243
	DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2244

2245 2246
	mutex_lock(&sc->mutex);

2247
	/* Stop ANI */
2248
	del_timer_sync(&sc->ani.timer);
2249

2250
	/* Reclaim beacon resources */
2251 2252 2253
	if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
	    (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
	    (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
S
Sujith 已提交
2254
		ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2255
		ath_beacon_return(sc, avp);
2256
	}
2257

2258
	sc->sc_flags &= ~SC_OP_BEACONS;
2259

2260 2261 2262 2263 2264
	for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
		if (sc->beacon.bslot[i] == conf->vif) {
			printk(KERN_DEBUG "%s: vif had allocated beacon "
			       "slot\n", __func__);
			sc->beacon.bslot[i] = NULL;
2265
			sc->beacon.bslot_aphy[i] = NULL;
2266 2267 2268
		}
	}

2269
	sc->nvifs--;
2270 2271

	mutex_unlock(&sc->mutex);
2272 2273
}

2274
static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2275
{
2276 2277
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2278
	struct ieee80211_conf *conf = &hw->conf;
2279
	struct ath_hw *ah = sc->sc_ah;
2280
	bool all_wiphys_idle = false, disable_radio = false;
2281

2282
	mutex_lock(&sc->mutex);
2283

2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301
	/* Leave this as the first check */
	if (changed & IEEE80211_CONF_CHANGE_IDLE) {

		spin_lock_bh(&sc->wiphy_lock);
		all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
		spin_unlock_bh(&sc->wiphy_lock);

		if (conf->flags & IEEE80211_CONF_IDLE){
			if (all_wiphys_idle)
				disable_radio = true;
		}
		else if (all_wiphys_idle) {
			ath_radio_enable(sc);
			DPRINTF(sc, ATH_DBG_CONFIG,
				"not-idle: enabling radio\n");
		}
	}

2302 2303
	if (changed & IEEE80211_CONF_CHANGE_PS) {
		if (conf->flags & IEEE80211_CONF_PS) {
2304 2305 2306 2307 2308 2309 2310 2311
			if (!(ah->caps.hw_caps &
			      ATH9K_HW_CAP_AUTOSLEEP)) {
				if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
					sc->imask |= ATH9K_INT_TIM_TIMER;
					ath9k_hw_set_interrupts(sc->sc_ah,
							sc->imask);
				}
				ath9k_hw_setrxabort(sc->sc_ah, 1);
2312
			}
2313
			sc->ps_enabled = true;
2314
		} else {
2315
			sc->ps_enabled = false;
2316
			ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2317 2318 2319
			if (!(ah->caps.hw_caps &
			      ATH9K_HW_CAP_AUTOSLEEP)) {
				ath9k_hw_setrxabort(sc->sc_ah, 0);
2320 2321 2322 2323
				sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
						  SC_OP_WAIT_FOR_CAB |
						  SC_OP_WAIT_FOR_PSPOLL_DATA |
						  SC_OP_WAIT_FOR_TX_ACK);
2324 2325 2326 2327 2328
				if (sc->imask & ATH9K_INT_TIM_TIMER) {
					sc->imask &= ~ATH9K_INT_TIM_TIMER;
					ath9k_hw_set_interrupts(sc->sc_ah,
							sc->imask);
				}
2329 2330 2331 2332
			}
		}
	}

2333
	if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2334
		struct ieee80211_channel *curchan = hw->conf.channel;
2335
		int pos = curchan->hw_value;
2336

2337 2338 2339
		aphy->chan_idx = pos;
		aphy->chan_is_ht = conf_is_ht(conf);

2340 2341 2342 2343 2344 2345 2346 2347 2348 2349
		if (aphy->state == ATH_WIPHY_SCAN ||
		    aphy->state == ATH_WIPHY_ACTIVE)
			ath9k_wiphy_pause_all_forced(sc, aphy);
		else {
			/*
			 * Do not change operational channel based on a paused
			 * wiphy changes.
			 */
			goto skip_chan_change;
		}
2350

S
Sujith 已提交
2351 2352
		DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
			curchan->center_freq);
2353

2354
		/* XXX: remove me eventualy */
2355
		ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2356

2357
		ath_update_chainmask(sc, conf_is_ht(conf));
2358

2359
		if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
S
Sujith 已提交
2360
			DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2361
			mutex_unlock(&sc->mutex);
2362 2363
			return -EINVAL;
		}
2364
	}
2365

2366
skip_chan_change:
2367
	if (changed & IEEE80211_CONF_CHANGE_POWER)
2368
		sc->config.txpowlimit = 2 * conf->power_level;
2369

2370 2371 2372 2373 2374
	if (disable_radio) {
		DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
		ath_radio_disable(sc);
	}

2375
	mutex_unlock(&sc->mutex);
2376

2377 2378 2379
	return 0;
}

2380 2381 2382 2383
#define SUPPORTED_FILTERS			\
	(FIF_PROMISC_IN_BSS |			\
	FIF_ALLMULTI |				\
	FIF_CONTROL |				\
2384
	FIF_PSPOLL |				\
2385 2386 2387
	FIF_OTHER_BSS |				\
	FIF_BCN_PRBRESP_PROMISC |		\
	FIF_FCSFAIL)
2388

2389 2390 2391 2392
/* FIXME: sc->sc_full_reset ? */
static void ath9k_configure_filter(struct ieee80211_hw *hw,
				   unsigned int changed_flags,
				   unsigned int *total_flags,
2393
				   u64 multicast)
2394
{
2395 2396
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2397
	u32 rfilt;
2398

2399 2400
	changed_flags &= SUPPORTED_FILTERS;
	*total_flags &= SUPPORTED_FILTERS;
2401

S
Sujith 已提交
2402
	sc->rx.rxfilter = *total_flags;
2403
	ath9k_ps_wakeup(sc);
2404 2405
	rfilt = ath_calcrxfilter(sc);
	ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2406
	ath9k_ps_restore(sc);
2407

S
Sujith 已提交
2408
	DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2409
}
2410

2411 2412 2413
static void ath9k_sta_notify(struct ieee80211_hw *hw,
			     struct ieee80211_vif *vif,
			     enum sta_notify_cmd cmd,
2414
			     struct ieee80211_sta *sta)
2415
{
2416 2417
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2418

2419 2420
	switch (cmd) {
	case STA_NOTIFY_ADD:
S
Sujith 已提交
2421
		ath_node_attach(sc, sta);
2422 2423
		break;
	case STA_NOTIFY_REMOVE:
S
Sujith 已提交
2424
		ath_node_detach(sc, sta);
2425 2426 2427 2428
		break;
	default:
		break;
	}
2429 2430
}

2431
static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2432
			 const struct ieee80211_tx_queue_params *params)
2433
{
2434 2435
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2436 2437
	struct ath9k_tx_queue_info qi;
	int ret = 0, qnum;
2438

2439 2440
	if (queue >= WME_NUM_AC)
		return 0;
2441

2442 2443
	mutex_lock(&sc->mutex);

2444 2445
	memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));

2446 2447 2448 2449 2450
	qi.tqi_aifs = params->aifs;
	qi.tqi_cwmin = params->cw_min;
	qi.tqi_cwmax = params->cw_max;
	qi.tqi_burstTime = params->txop;
	qnum = ath_get_hal_qnum(queue, sc);
2451

2452
	DPRINTF(sc, ATH_DBG_CONFIG,
S
Sujith 已提交
2453
		"Configure tx [queue/halq] [%d/%d],  "
2454
		"aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
S
Sujith 已提交
2455 2456
		queue, qnum, params->aifs, params->cw_min,
		params->cw_max, params->txop);
2457

2458 2459
	ret = ath_txq_update(sc, qnum, &qi);
	if (ret)
S
Sujith 已提交
2460
		DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2461

2462 2463
	mutex_unlock(&sc->mutex);

2464 2465
	return ret;
}
2466

2467 2468
static int ath9k_set_key(struct ieee80211_hw *hw,
			 enum set_key_cmd cmd,
2469 2470
			 struct ieee80211_vif *vif,
			 struct ieee80211_sta *sta,
2471 2472
			 struct ieee80211_key_conf *key)
{
2473 2474
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2475
	int ret = 0;
2476

2477 2478 2479
	if (modparam_nohwcrypt)
		return -ENOSPC;

2480
	mutex_lock(&sc->mutex);
2481
	ath9k_ps_wakeup(sc);
S
Sujith 已提交
2482
	DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2483

2484 2485
	switch (cmd) {
	case SET_KEY:
2486
		ret = ath_key_config(sc, vif, sta, key);
2487 2488
		if (ret >= 0) {
			key->hw_key_idx = ret;
2489 2490 2491 2492
			/* push IV and Michael MIC generation to stack */
			key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
			if (key->alg == ALG_TKIP)
				key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2493 2494
			if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
				key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2495
			ret = 0;
2496 2497 2498 2499 2500 2501 2502 2503
		}
		break;
	case DISABLE_KEY:
		ath_key_delete(sc, key);
		break;
	default:
		ret = -EINVAL;
	}
2504

2505
	ath9k_ps_restore(sc);
2506 2507
	mutex_unlock(&sc->mutex);

2508 2509
	return ret;
}
2510

2511 2512 2513 2514 2515
static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
				   struct ieee80211_vif *vif,
				   struct ieee80211_bss_conf *bss_conf,
				   u32 changed)
{
2516 2517
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2518 2519 2520 2521
	struct ath_hw *ah = sc->sc_ah;
	struct ath_vif *avp = (void *)vif->drv_priv;
	u32 rfilt = 0;
	int error, i;
2522

2523 2524
	mutex_lock(&sc->mutex);

2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603
	/*
	 * TODO: Need to decide which hw opmode to use for
	 *       multi-interface cases
	 * XXX: This belongs into add_interface!
	 */
	if (vif->type == NL80211_IFTYPE_AP &&
	    ah->opmode != NL80211_IFTYPE_AP) {
		ah->opmode = NL80211_IFTYPE_STATION;
		ath9k_hw_setopmode(ah);
		memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
		sc->curaid = 0;
		ath9k_hw_write_associd(sc);
		/* Request full reset to get hw opmode changed properly */
		sc->sc_flags |= SC_OP_FULL_RESET;
	}

	if ((changed & BSS_CHANGED_BSSID) &&
	    !is_zero_ether_addr(bss_conf->bssid)) {
		switch (vif->type) {
		case NL80211_IFTYPE_STATION:
		case NL80211_IFTYPE_ADHOC:
		case NL80211_IFTYPE_MESH_POINT:
			/* Set BSSID */
			memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
			memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
			sc->curaid = 0;
			ath9k_hw_write_associd(sc);

			/* Set aggregation protection mode parameters */
			sc->config.ath_aggr_prot = 0;

			DPRINTF(sc, ATH_DBG_CONFIG,
				"RX filter 0x%x bssid %pM aid 0x%x\n",
				rfilt, sc->curbssid, sc->curaid);

			/* need to reconfigure the beacon */
			sc->sc_flags &= ~SC_OP_BEACONS ;

			break;
		default:
			break;
		}
	}

	if ((vif->type == NL80211_IFTYPE_ADHOC) ||
	    (vif->type == NL80211_IFTYPE_AP) ||
	    (vif->type == NL80211_IFTYPE_MESH_POINT)) {
		if ((changed & BSS_CHANGED_BEACON) ||
		    (changed & BSS_CHANGED_BEACON_ENABLED &&
		     bss_conf->enable_beacon)) {
			/*
			 * Allocate and setup the beacon frame.
			 *
			 * Stop any previous beacon DMA.  This may be
			 * necessary, for example, when an ibss merge
			 * causes reconfiguration; we may be called
			 * with beacon transmission active.
			 */
			ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);

			error = ath_beacon_alloc(aphy, vif);
			if (!error)
				ath_beacon_config(sc, vif);
		}
	}

	/* Check for WLAN_CAPABILITY_PRIVACY ? */
	if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
		for (i = 0; i < IEEE80211_WEP_NKID; i++)
			if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
				ath9k_hw_keysetmac(sc->sc_ah,
						   (u16)i,
						   sc->curbssid);
	}

	/* Only legacy IBSS for now */
	if (vif->type == NL80211_IFTYPE_ADHOC)
		ath_update_chainmask(sc, 0);

2604
	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
S
Sujith 已提交
2605
		DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2606 2607 2608 2609 2610 2611
			bss_conf->use_short_preamble);
		if (bss_conf->use_short_preamble)
			sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
		else
			sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
	}
2612

2613
	if (changed & BSS_CHANGED_ERP_CTS_PROT) {
S
Sujith 已提交
2614
		DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2615 2616 2617 2618 2619 2620 2621
			bss_conf->use_cts_prot);
		if (bss_conf->use_cts_prot &&
		    hw->conf.channel->band != IEEE80211_BAND_5GHZ)
			sc->sc_flags |= SC_OP_PROTECT_ENABLE;
		else
			sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
	}
2622

2623
	if (changed & BSS_CHANGED_ASSOC) {
S
Sujith 已提交
2624
		DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2625
			bss_conf->assoc);
S
Sujith 已提交
2626
		ath9k_bss_assoc_info(sc, vif, bss_conf);
2627
	}
2628

2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640
	/*
	 * The HW TSF has to be reset when the beacon interval changes.
	 * We set the flag here, and ath_beacon_config_ap() would take this
	 * into account when it gets called through the subsequent
	 * config_interface() call - with IFCC_BEACON in the changed field.
	 */

	if (changed & BSS_CHANGED_BEACON_INT) {
		sc->sc_flags |= SC_OP_TSF_RESET;
		sc->beacon_interval = bss_conf->beacon_int;
	}

2641
	mutex_unlock(&sc->mutex);
2642
}
2643

2644 2645 2646
static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
{
	u64 tsf;
2647 2648
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2649

2650 2651 2652
	mutex_lock(&sc->mutex);
	tsf = ath9k_hw_gettsf64(sc->sc_ah);
	mutex_unlock(&sc->mutex);
2653

2654 2655
	return tsf;
}
2656

2657 2658
static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
{
2659 2660
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2661

2662 2663 2664
	mutex_lock(&sc->mutex);
	ath9k_hw_settsf64(sc->sc_ah, tsf);
	mutex_unlock(&sc->mutex);
2665 2666
}

2667 2668
static void ath9k_reset_tsf(struct ieee80211_hw *hw)
{
2669 2670
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2671

2672 2673 2674
	mutex_lock(&sc->mutex);
	ath9k_hw_reset_tsf(sc->sc_ah);
	mutex_unlock(&sc->mutex);
2675
}
2676

2677
static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2678 2679 2680
			      enum ieee80211_ampdu_mlme_action action,
			      struct ieee80211_sta *sta,
			      u16 tid, u16 *ssn)
2681
{
2682 2683
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2684
	int ret = 0;
2685

2686 2687
	switch (action) {
	case IEEE80211_AMPDU_RX_START:
2688 2689
		if (!(sc->sc_flags & SC_OP_RXAGGR))
			ret = -ENOTSUPP;
2690 2691 2692 2693
		break;
	case IEEE80211_AMPDU_RX_STOP:
		break;
	case IEEE80211_AMPDU_TX_START:
S
Sujith 已提交
2694 2695
		ath_tx_aggr_start(sc, sta, tid, ssn);
		ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2696 2697
		break;
	case IEEE80211_AMPDU_TX_STOP:
S
Sujith 已提交
2698
		ath_tx_aggr_stop(sc, sta, tid);
2699
		ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2700
		break;
2701
	case IEEE80211_AMPDU_TX_OPERATIONAL:
2702 2703
		ath_tx_aggr_resume(sc, sta, tid);
		break;
2704
	default:
S
Sujith 已提交
2705
		DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2706 2707 2708
	}

	return ret;
2709 2710
}

2711 2712
static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
{
2713 2714
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2715

2716
	mutex_lock(&sc->mutex);
2717 2718 2719 2720 2721 2722 2723
	if (ath9k_wiphy_scanning(sc)) {
		printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
		       "same time\n");
		/*
		 * Do not allow the concurrent scanning state for now. This
		 * could be improved with scanning control moved into ath9k.
		 */
2724
		mutex_unlock(&sc->mutex);
2725 2726 2727 2728 2729 2730
		return;
	}

	aphy->state = ATH_WIPHY_SCAN;
	ath9k_wiphy_pause_all_forced(sc, aphy);

2731
	spin_lock_bh(&sc->ani_lock);
2732
	sc->sc_flags |= SC_OP_SCANNING;
2733
	spin_unlock_bh(&sc->ani_lock);
2734
	mutex_unlock(&sc->mutex);
2735 2736 2737 2738
}

static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
{
2739 2740
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2741

2742
	mutex_lock(&sc->mutex);
2743
	spin_lock_bh(&sc->ani_lock);
2744
	aphy->state = ATH_WIPHY_ACTIVE;
2745
	sc->sc_flags &= ~SC_OP_SCANNING;
2746
	sc->sc_flags |= SC_OP_FULL_RESET;
2747
	spin_unlock_bh(&sc->ani_lock);
2748
	mutex_unlock(&sc->mutex);
2749 2750
}

2751
struct ieee80211_ops ath9k_ops = {
2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763
	.tx 		    = ath9k_tx,
	.start 		    = ath9k_start,
	.stop 		    = ath9k_stop,
	.add_interface 	    = ath9k_add_interface,
	.remove_interface   = ath9k_remove_interface,
	.config 	    = ath9k_config,
	.configure_filter   = ath9k_configure_filter,
	.sta_notify         = ath9k_sta_notify,
	.conf_tx 	    = ath9k_conf_tx,
	.bss_info_changed   = ath9k_bss_info_changed,
	.set_key            = ath9k_set_key,
	.get_tsf 	    = ath9k_get_tsf,
2764
	.set_tsf 	    = ath9k_set_tsf,
2765
	.reset_tsf 	    = ath9k_reset_tsf,
2766
	.ampdu_action       = ath9k_ampdu_action,
2767 2768
	.sw_scan_start      = ath9k_sw_scan_start,
	.sw_scan_complete   = ath9k_sw_scan_complete,
2769
	.rfkill_poll        = ath9k_rfkill_poll_state,
2770 2771
};

2772 2773 2774 2775 2776 2777 2778 2779 2780
static struct {
	u32 version;
	const char * name;
} ath_mac_bb_names[] = {
	{ AR_SREV_VERSION_5416_PCI,	"5416" },
	{ AR_SREV_VERSION_5416_PCIE,	"5418" },
	{ AR_SREV_VERSION_9100,		"9100" },
	{ AR_SREV_VERSION_9160,		"9160" },
	{ AR_SREV_VERSION_9280,		"9280" },
2781 2782
	{ AR_SREV_VERSION_9285,		"9285" },
	{ AR_SREV_VERSION_9287,         "9287" }
2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798
};

static struct {
	u16 version;
	const char * name;
} ath_rf_names[] = {
	{ 0,				"5133" },
	{ AR_RAD5133_SREV_MAJOR,	"5133" },
	{ AR_RAD5122_SREV_MAJOR,	"5122" },
	{ AR_RAD2133_SREV_MAJOR,	"2133" },
	{ AR_RAD2122_SREV_MAJOR,	"2122" }
};

/*
 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
 */
2799
const char *
2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815
ath_mac_bb_name(u32 mac_bb_version)
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
		if (ath_mac_bb_names[i].version == mac_bb_version) {
			return ath_mac_bb_names[i].name;
		}
	}

	return "????";
}

/*
 * Return the RF name. "????" is returned if the RF is unknown.
 */
2816
const char *
2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829
ath_rf_name(u16 rf_version)
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
		if (ath_rf_names[i].version == rf_version) {
			return ath_rf_names[i].name;
		}
	}

	return "????";
}

2830
static int __init ath9k_init(void)
2831
{
2832 2833 2834 2835 2836 2837
	int error;

	/* Register rate control algorithm */
	error = ath_rate_control_register();
	if (error != 0) {
		printk(KERN_ERR
2838 2839
			"ath9k: Unable to register rate control "
			"algorithm: %d\n",
2840
			error);
2841
		goto err_out;
2842 2843
	}

2844 2845 2846 2847 2848 2849 2850 2851
	error = ath9k_debug_create_root();
	if (error) {
		printk(KERN_ERR
			"ath9k: Unable to create debugfs root: %d\n",
			error);
		goto err_rate_unregister;
	}

2852 2853
	error = ath_pci_init();
	if (error < 0) {
2854
		printk(KERN_ERR
2855
			"ath9k: No PCI devices found, driver not installed.\n");
2856
		error = -ENODEV;
2857
		goto err_remove_root;
2858 2859
	}

2860 2861 2862 2863 2864 2865
	error = ath_ahb_init();
	if (error < 0) {
		error = -ENODEV;
		goto err_pci_exit;
	}

2866
	return 0;
2867

2868 2869 2870
 err_pci_exit:
	ath_pci_exit();

2871 2872
 err_remove_root:
	ath9k_debug_remove_root();
2873 2874 2875 2876
 err_rate_unregister:
	ath_rate_control_unregister();
 err_out:
	return error;
2877
}
2878
module_init(ath9k_init);
2879

2880
static void __exit ath9k_exit(void)
2881
{
2882
	ath_ahb_exit();
2883
	ath_pci_exit();
2884
	ath9k_debug_remove_root();
2885
	ath_rate_control_unregister();
S
Sujith 已提交
2886
	printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2887
}
2888
module_exit(ath9k_exit);
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