main.c 72.5 KB
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/*
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 * Copyright (c) 2008-2009 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/nl80211.h>
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#include "ath9k.h"
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static char *dev_info = "ath9k";

MODULE_AUTHOR("Atheros Communications");
MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
MODULE_LICENSE("Dual BSD/GPL");

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static int modparam_nohwcrypt;
module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");

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/* We use the hw_value as an index into our private channel structure */

#define CHAN2G(_freq, _idx)  { \
	.center_freq = (_freq), \
	.hw_value = (_idx), \
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	.max_power = 20, \
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}

#define CHAN5G(_freq, _idx) { \
	.band = IEEE80211_BAND_5GHZ, \
	.center_freq = (_freq), \
	.hw_value = (_idx), \
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	.max_power = 20, \
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}

/* Some 2 GHz radios are actually tunable on 2312-2732
 * on 5 MHz steps, we support the channels which we know
 * we have calibration data for all cards though to make
 * this static */
static struct ieee80211_channel ath9k_2ghz_chantable[] = {
	CHAN2G(2412, 0), /* Channel 1 */
	CHAN2G(2417, 1), /* Channel 2 */
	CHAN2G(2422, 2), /* Channel 3 */
	CHAN2G(2427, 3), /* Channel 4 */
	CHAN2G(2432, 4), /* Channel 5 */
	CHAN2G(2437, 5), /* Channel 6 */
	CHAN2G(2442, 6), /* Channel 7 */
	CHAN2G(2447, 7), /* Channel 8 */
	CHAN2G(2452, 8), /* Channel 9 */
	CHAN2G(2457, 9), /* Channel 10 */
	CHAN2G(2462, 10), /* Channel 11 */
	CHAN2G(2467, 11), /* Channel 12 */
	CHAN2G(2472, 12), /* Channel 13 */
	CHAN2G(2484, 13), /* Channel 14 */
};

/* Some 5 GHz radios are actually tunable on XXXX-YYYY
 * on 5 MHz steps, we support the channels which we know
 * we have calibration data for all cards though to make
 * this static */
static struct ieee80211_channel ath9k_5ghz_chantable[] = {
	/* _We_ call this UNII 1 */
	CHAN5G(5180, 14), /* Channel 36 */
	CHAN5G(5200, 15), /* Channel 40 */
	CHAN5G(5220, 16), /* Channel 44 */
	CHAN5G(5240, 17), /* Channel 48 */
	/* _We_ call this UNII 2 */
	CHAN5G(5260, 18), /* Channel 52 */
	CHAN5G(5280, 19), /* Channel 56 */
	CHAN5G(5300, 20), /* Channel 60 */
	CHAN5G(5320, 21), /* Channel 64 */
	/* _We_ call this "Middle band" */
	CHAN5G(5500, 22), /* Channel 100 */
	CHAN5G(5520, 23), /* Channel 104 */
	CHAN5G(5540, 24), /* Channel 108 */
	CHAN5G(5560, 25), /* Channel 112 */
	CHAN5G(5580, 26), /* Channel 116 */
	CHAN5G(5600, 27), /* Channel 120 */
	CHAN5G(5620, 28), /* Channel 124 */
	CHAN5G(5640, 29), /* Channel 128 */
	CHAN5G(5660, 30), /* Channel 132 */
	CHAN5G(5680, 31), /* Channel 136 */
	CHAN5G(5700, 32), /* Channel 140 */
	/* _We_ call this UNII 3 */
	CHAN5G(5745, 33), /* Channel 149 */
	CHAN5G(5765, 34), /* Channel 153 */
	CHAN5G(5785, 35), /* Channel 157 */
	CHAN5G(5805, 36), /* Channel 161 */
	CHAN5G(5825, 37), /* Channel 165 */
};

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static void ath_cache_conf_rate(struct ath_softc *sc,
				struct ieee80211_conf *conf)
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{
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	switch (conf->channel->band) {
	case IEEE80211_BAND_2GHZ:
		if (conf_is_ht20(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
		else if (conf_is_ht40_minus(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
		else if (conf_is_ht40_plus(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
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		else
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			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11G];
		break;
	case IEEE80211_BAND_5GHZ:
		if (conf_is_ht20(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
		else if (conf_is_ht40_minus(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
		else if (conf_is_ht40_plus(conf))
			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
		else
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			sc->cur_rate_table =
			  sc->hw_rate_table[ATH9K_MODE_11A];
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		break;
	default:
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		BUG_ON(1);
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		break;
	}
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}

static void ath_update_txpow(struct ath_softc *sc)
{
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	struct ath_hw *ah = sc->sc_ah;
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	u32 txpow;

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	if (sc->curtxpow != sc->config.txpowlimit) {
		ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
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		/* read back in case value is clamped */
		ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
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		sc->curtxpow = txpow;
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	}
}

static u8 parse_mpdudensity(u8 mpdudensity)
{
	/*
	 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
	 *   0 for no restriction
	 *   1 for 1/4 us
	 *   2 for 1/2 us
	 *   3 for 1 us
	 *   4 for 2 us
	 *   5 for 4 us
	 *   6 for 8 us
	 *   7 for 16 us
	 */
	switch (mpdudensity) {
	case 0:
		return 0;
	case 1:
	case 2:
	case 3:
		/* Our lower layer calculations limit our precision to
		   1 microsecond */
		return 1;
	case 4:
		return 2;
	case 5:
		return 4;
	case 6:
		return 8;
	case 7:
		return 16;
	default:
		return 0;
	}
}

static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
{
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	const struct ath_rate_table *rate_table = NULL;
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	struct ieee80211_supported_band *sband;
	struct ieee80211_rate *rate;
	int i, maxrates;

	switch (band) {
	case IEEE80211_BAND_2GHZ:
		rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
		break;
	case IEEE80211_BAND_5GHZ:
		rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
		break;
	default:
		break;
	}

	if (rate_table == NULL)
		return;

	sband = &sc->sbands[band];
	rate = sc->rates[band];

	if (rate_table->rate_cnt > ATH_RATE_MAX)
		maxrates = ATH_RATE_MAX;
	else
		maxrates = rate_table->rate_cnt;

	for (i = 0; i < maxrates; i++) {
		rate[i].bitrate = rate_table->info[i].ratekbps / 100;
		rate[i].hw_value = rate_table->info[i].ratecode;
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		if (rate_table->info[i].short_preamble) {
			rate[i].hw_value_short = rate_table->info[i].ratecode |
				rate_table->info[i].short_preamble;
			rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
		}
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		sband->n_bitrates++;
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		DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
			rate[i].bitrate / 10, rate[i].hw_value);
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	}
}

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static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
						struct ieee80211_hw *hw)
{
	struct ieee80211_channel *curchan = hw->conf.channel;
	struct ath9k_channel *channel;
	u8 chan_idx;

	chan_idx = curchan->hw_value;
	channel = &sc->sc_ah->channels[chan_idx];
	ath9k_update_ichannel(sc, hw, channel);
	return channel;
}

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/*
 * Set/change channels.  If the channel is really being changed, it's done
 * by reseting the chip.  To accomplish this we must first cleanup any pending
 * DMA, then restart stuff.
*/
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int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
		    struct ath9k_channel *hchan)
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{
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	struct ath_hw *ah = sc->sc_ah;
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	bool fastcc = true, stopped;
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	struct ieee80211_channel *channel = hw->conf.channel;
	int r;
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	if (sc->sc_flags & SC_OP_INVALID)
		return -EIO;

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	ath9k_ps_wakeup(sc);

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	/*
	 * This is only performed if the channel settings have
	 * actually changed.
	 *
	 * To switch channels clear any pending DMA operations;
	 * wait long enough for the RX fifo to drain, reset the
	 * hardware at the new frequency, and then re-enable
	 * the relevant bits of the h/w.
	 */
	ath9k_hw_set_interrupts(ah, 0);
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	ath_drain_all_txq(sc, false);
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	stopped = ath_stoprecv(sc);
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	/* XXX: do not flush receive queue here. We don't want
	 * to flush data frames already in queue because of
	 * changing channel. */
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	if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
		fastcc = false;

	DPRINTF(sc, ATH_DBG_CONFIG,
		"(%u MHz) -> (%u MHz), chanwidth: %d\n",
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		sc->sc_ah->curchan->channel,
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		channel->center_freq, sc->tx_chan_width);
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	spin_lock_bh(&sc->sc_resetlock);

	r = ath9k_hw_reset(ah, hchan, fastcc);
	if (r) {
		DPRINTF(sc, ATH_DBG_FATAL,
			"Unable to reset channel (%u Mhz) "
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			"reset status %d\n",
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			channel->center_freq, r);
		spin_unlock_bh(&sc->sc_resetlock);
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		goto ps_restore;
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	}
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	spin_unlock_bh(&sc->sc_resetlock);

	sc->sc_flags &= ~SC_OP_FULL_RESET;

	if (ath_startrecv(sc) != 0) {
		DPRINTF(sc, ATH_DBG_FATAL,
			"Unable to restart recv logic\n");
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		r = -EIO;
		goto ps_restore;
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	}

	ath_cache_conf_rate(sc, &hw->conf);
	ath_update_txpow(sc);
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	ath9k_hw_set_interrupts(ah, sc->imask);
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 ps_restore:
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	ath9k_ps_restore(sc);
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	return r;
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}

/*
 *  This routine performs the periodic noise floor calibration function
 *  that is used to adjust and optimize the chip performance.  This
 *  takes environmental changes (location, temperature) into account.
 *  When the task is complete, it reschedules itself depending on the
 *  appropriate interval that was calculated.
 */
static void ath_ani_calibrate(unsigned long data)
{
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	struct ath_softc *sc = (struct ath_softc *)data;
	struct ath_hw *ah = sc->sc_ah;
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	bool longcal = false;
	bool shortcal = false;
	bool aniflag = false;
	unsigned int timestamp = jiffies_to_msecs(jiffies);
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	u32 cal_interval, short_cal_interval;
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	short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
		ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
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	/*
	* don't calibrate when we're scanning.
	* we are most likely not on our home channel.
	*/
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	spin_lock(&sc->ani_lock);
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	if (sc->sc_flags & SC_OP_SCANNING)
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		goto set_timer;
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	/* Only calibrate if awake */
	if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
		goto set_timer;

	ath9k_ps_wakeup(sc);

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	/* Long calibration runs independently of short calibration. */
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	if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
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		longcal = true;
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		DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
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		sc->ani.longcal_timer = timestamp;
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	}

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	/* Short calibration applies only while caldone is false */
	if (!sc->ani.caldone) {
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		if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
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			shortcal = true;
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			DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
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			sc->ani.shortcal_timer = timestamp;
			sc->ani.resetcal_timer = timestamp;
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		}
	} else {
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		if ((timestamp - sc->ani.resetcal_timer) >=
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		    ATH_RESTART_CALINTERVAL) {
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			sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
			if (sc->ani.caldone)
				sc->ani.resetcal_timer = timestamp;
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		}
	}

	/* Verify whether we must check ANI */
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	if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
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		aniflag = true;
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		sc->ani.checkani_timer = timestamp;
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	}

	/* Skip all processing if there's nothing to do. */
	if (longcal || shortcal || aniflag) {
		/* Call ANI routine if necessary */
		if (aniflag)
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			ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
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		/* Perform calibration if necessary */
		if (longcal || shortcal) {
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			sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
						     sc->rx_chainmask, longcal);

			if (longcal)
				sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
								     ah->curchan);

			DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
				ah->curchan->channel, ah->curchan->channelFlags,
				sc->ani.noise_floor);
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		}
	}

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	ath9k_ps_restore(sc);

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set_timer:
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	spin_unlock(&sc->ani_lock);
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	/*
	* Set timer interval based on previous results.
	* The interval must be the shortest necessary to satisfy ANI,
	* short calibration and long calibration.
	*/
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	cal_interval = ATH_LONG_CALINTERVAL;
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	if (sc->sc_ah->config.enable_ani)
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		cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
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	if (!sc->ani.caldone)
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		cal_interval = min(cal_interval, (u32)short_cal_interval);
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	mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
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}

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static void ath_start_ani(struct ath_softc *sc)
{
	unsigned long timestamp = jiffies_to_msecs(jiffies);

	sc->ani.longcal_timer = timestamp;
	sc->ani.shortcal_timer = timestamp;
	sc->ani.checkani_timer = timestamp;

	mod_timer(&sc->ani.timer,
		  jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
}

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/*
 * Update tx/rx chainmask. For legacy association,
 * hard code chainmask to 1x1, for 11n association, use
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 * the chainmask configuration, for bt coexistence, use
 * the chainmask configuration even in legacy mode.
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 */
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void ath_update_chainmask(struct ath_softc *sc, int is_ht)
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{
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	if (is_ht ||
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	    (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
		sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
		sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
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	} else {
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		sc->tx_chainmask = 1;
		sc->rx_chainmask = 1;
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	}

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	DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
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		sc->tx_chainmask, sc->rx_chainmask);
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}

static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
{
	struct ath_node *an;

	an = (struct ath_node *)sta->drv_priv;

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	if (sc->sc_flags & SC_OP_TXAGGR) {
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		ath_tx_node_init(sc, an);
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		an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
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				     sta->ht_cap.ampdu_factor);
		an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
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		an->last_rssi = ATH_RSSI_DUMMY_MARKER;
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	}
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}

static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
{
	struct ath_node *an = (struct ath_node *)sta->drv_priv;

	if (sc->sc_flags & SC_OP_TXAGGR)
		ath_tx_node_cleanup(sc, an);
}

static void ath9k_tasklet(unsigned long data)
{
	struct ath_softc *sc = (struct ath_softc *)data;
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	u32 status = sc->intrstatus;
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	ath9k_ps_wakeup(sc);

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	if (status & ATH9K_INT_FATAL) {
		ath_reset(sc, false);
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		ath9k_ps_restore(sc);
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		return;
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	}
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	if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
		spin_lock_bh(&sc->rx.rxflushlock);
		ath_rx_tasklet(sc, 0);
		spin_unlock_bh(&sc->rx.rxflushlock);
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	}

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	if (status & ATH9K_INT_TX)
		ath_tx_tasklet(sc);

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	if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
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		/*
		 * TSF sync does not look correct; remain awake to sync with
		 * the next Beacon.
		 */
		DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
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		sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
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	}

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	/* re-enable hardware interrupt */
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	ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
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	ath9k_ps_restore(sc);
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}

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irqreturn_t ath_isr(int irq, void *dev)
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{
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#define SCHED_INTR (				\
		ATH9K_INT_FATAL |		\
		ATH9K_INT_RXORN |		\
		ATH9K_INT_RXEOL |		\
		ATH9K_INT_RX |			\
		ATH9K_INT_TX |			\
		ATH9K_INT_BMISS |		\
		ATH9K_INT_CST |			\
		ATH9K_INT_TSFOOR)

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	struct ath_softc *sc = dev;
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	struct ath_hw *ah = sc->sc_ah;
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	enum ath9k_int status;
	bool sched = false;

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	/*
	 * The hardware is not ready/present, don't
	 * touch anything. Note this can happen early
	 * on if the IRQ is shared.
	 */
	if (sc->sc_flags & SC_OP_INVALID)
		return IRQ_NONE;
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	/* shared irq, not for us */

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	if (!ath9k_hw_intrpend(ah))
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		return IRQ_NONE;

	/*
	 * Figure out the reason(s) for the interrupt.  Note
	 * that the hal returns a pseudo-ISR that may include
	 * bits we haven't explicitly enabled so we mask the
	 * value to insure we only process bits we requested.
	 */
	ath9k_hw_getisr(ah, &status);	/* NB: clears ISR too */
	status &= sc->imask;	/* discard unasked-for bits */
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554 555 556 557
	/*
	 * If there are no status bits set, then this interrupt was not
	 * for me (should have been caught above).
	 */
558
	if (!status)
559
		return IRQ_NONE;
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560

561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580
	/* Cache the status */
	sc->intrstatus = status;

	if (status & SCHED_INTR)
		sched = true;

	/*
	 * If a FATAL or RXORN interrupt is received, we have to reset the
	 * chip immediately.
	 */
	if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
		goto chip_reset;

	if (status & ATH9K_INT_SWBA)
		tasklet_schedule(&sc->bcon_tasklet);

	if (status & ATH9K_INT_TXURN)
		ath9k_hw_updatetxtriglevel(ah, true);

	if (status & ATH9K_INT_MIB) {
S
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581
		/*
582 583 584
		 * Disable interrupts until we service the MIB
		 * interrupt; otherwise it will continue to
		 * fire.
S
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585
		 */
586 587 588 589 590 591 592 593 594
		ath9k_hw_set_interrupts(ah, 0);
		/*
		 * Let the hal handle the event. We assume
		 * it will clear whatever condition caused
		 * the interrupt.
		 */
		ath9k_hw_procmibevent(ah, &sc->nodestats);
		ath9k_hw_set_interrupts(ah, sc->imask);
	}
S
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595

596 597
	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
		if (status & ATH9K_INT_TIM_TIMER) {
598 599 600
			/* Clear RxAbort bit so that we can
			 * receive frames */
			ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
601
			ath9k_hw_setrxabort(sc->sc_ah, 0);
602
			sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
S
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603
		}
604 605

chip_reset:
S
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606

607 608
	ath_debug_stat_interrupt(sc, status);

S
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609 610
	if (sched) {
		/* turn off every interrupt except SWBA */
611
		ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
S
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612 613 614 615
		tasklet_schedule(&sc->intr_tq);
	}

	return IRQ_HANDLED;
616 617

#undef SCHED_INTR
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618 619
}

620
static u32 ath_get_extchanmode(struct ath_softc *sc,
621
			       struct ieee80211_channel *chan,
622
			       enum nl80211_channel_type channel_type)
623 624 625 626 627
{
	u32 chanmode = 0;

	switch (chan->band) {
	case IEEE80211_BAND_2GHZ:
628 629 630
		switch(channel_type) {
		case NL80211_CHAN_NO_HT:
		case NL80211_CHAN_HT20:
631
			chanmode = CHANNEL_G_HT20;
632 633
			break;
		case NL80211_CHAN_HT40PLUS:
634
			chanmode = CHANNEL_G_HT40PLUS;
635 636
			break;
		case NL80211_CHAN_HT40MINUS:
637
			chanmode = CHANNEL_G_HT40MINUS;
638 639
			break;
		}
640 641
		break;
	case IEEE80211_BAND_5GHZ:
642 643 644
		switch(channel_type) {
		case NL80211_CHAN_NO_HT:
		case NL80211_CHAN_HT20:
645
			chanmode = CHANNEL_A_HT20;
646 647
			break;
		case NL80211_CHAN_HT40PLUS:
648
			chanmode = CHANNEL_A_HT40PLUS;
649 650
			break;
		case NL80211_CHAN_HT40MINUS:
651
			chanmode = CHANNEL_A_HT40MINUS;
652 653
			break;
		}
654 655 656 657 658 659 660 661
		break;
	default:
		break;
	}

	return chanmode;
}

662
static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
663 664
			   struct ath9k_keyval *hk, const u8 *addr,
			   bool authenticator)
665
{
666 667
	const u8 *key_rxmic;
	const u8 *key_txmic;
668

669 670
	key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
	key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
671 672

	if (addr == NULL) {
673 674 675 676 677
		/*
		 * Group key installation - only two key cache entries are used
		 * regardless of splitmic capability since group key is only
		 * used either for TX or RX.
		 */
678 679 680 681 682 683 684
		if (authenticator) {
			memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
			memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
		} else {
			memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
			memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
		}
685
		return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
686
	}
687
	if (!sc->splitmic) {
688
		/* TX and RX keys share the same key cache entry. */
689 690
		memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
		memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
691
		return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
692
	}
693 694 695 696

	/* Separate key cache entries for TX and RX */

	/* TX key goes at first index, RX key at +32. */
697
	memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
698 699
	if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
		/* TX MIC entry failed. No need to proceed further */
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700
		DPRINTF(sc, ATH_DBG_FATAL,
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701
			"Setting TX MIC Key Failed\n");
702 703 704 705 706
		return 0;
	}

	memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
	/* XXX delete tx key on failure? */
707
	return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
708 709 710 711 712 713
}

static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
{
	int i;

714 715 716
	for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
		if (test_bit(i, sc->keymap) ||
		    test_bit(i + 64, sc->keymap))
717
			continue; /* At least one part of TKIP key allocated */
718 719 720
		if (sc->splitmic &&
		    (test_bit(i + 32, sc->keymap) ||
		     test_bit(i + 64 + 32, sc->keymap)))
721 722 723 724 725 726 727 728 729 730 731 732 733
			continue; /* At least one part of TKIP key allocated */

		/* Found a free slot for a TKIP key */
		return i;
	}
	return -1;
}

static int ath_reserve_key_cache_slot(struct ath_softc *sc)
{
	int i;

	/* First, try to find slots that would not be available for TKIP. */
734 735 736 737 738 739
	if (sc->splitmic) {
		for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
			if (!test_bit(i, sc->keymap) &&
			    (test_bit(i + 32, sc->keymap) ||
			     test_bit(i + 64, sc->keymap) ||
			     test_bit(i + 64 + 32, sc->keymap)))
740
				return i;
741 742 743 744
			if (!test_bit(i + 32, sc->keymap) &&
			    (test_bit(i, sc->keymap) ||
			     test_bit(i + 64, sc->keymap) ||
			     test_bit(i + 64 + 32, sc->keymap)))
745
				return i + 32;
746 747 748 749
			if (!test_bit(i + 64, sc->keymap) &&
			    (test_bit(i , sc->keymap) ||
			     test_bit(i + 32, sc->keymap) ||
			     test_bit(i + 64 + 32, sc->keymap)))
750
				return i + 64;
751 752 753 754
			if (!test_bit(i + 64 + 32, sc->keymap) &&
			    (test_bit(i, sc->keymap) ||
			     test_bit(i + 32, sc->keymap) ||
			     test_bit(i + 64, sc->keymap)))
755
				return i + 64 + 32;
756 757
		}
	} else {
758 759 760
		for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
			if (!test_bit(i, sc->keymap) &&
			    test_bit(i + 64, sc->keymap))
761
				return i;
762 763
			if (test_bit(i, sc->keymap) &&
			    !test_bit(i + 64, sc->keymap))
764 765 766 767 768
				return i + 64;
		}
	}

	/* No partially used TKIP slots, pick any available slot */
769
	for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
770 771 772 773 774
		/* Do not allow slots that could be needed for TKIP group keys
		 * to be used. This limitation could be removed if we know that
		 * TKIP will not be used. */
		if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
			continue;
775
		if (sc->splitmic) {
776 777 778 779 780 781
			if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
				continue;
			if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
				continue;
		}

782
		if (!test_bit(i, sc->keymap))
783 784 785 786 787
			return i; /* Found a free slot for a key */
	}

	/* No free slot found */
	return -1;
788 789 790
}

static int ath_key_config(struct ath_softc *sc,
791
			  struct ieee80211_vif *vif,
792
			  struct ieee80211_sta *sta,
793 794 795 796 797
			  struct ieee80211_key_conf *key)
{
	struct ath9k_keyval hk;
	const u8 *mac = NULL;
	int ret = 0;
798
	int idx;
799 800 801 802 803 804 805 806 807 808 809 810 811 812

	memset(&hk, 0, sizeof(hk));

	switch (key->alg) {
	case ALG_WEP:
		hk.kv_type = ATH9K_CIPHER_WEP;
		break;
	case ALG_TKIP:
		hk.kv_type = ATH9K_CIPHER_TKIP;
		break;
	case ALG_CCMP:
		hk.kv_type = ATH9K_CIPHER_AES_CCM;
		break;
	default:
813
		return -EOPNOTSUPP;
814 815
	}

816
	hk.kv_len = key->keylen;
817 818
	memcpy(hk.kv_val, key->key, key->keylen);

819 820 821 822 823
	if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
		/* For now, use the default keys for broadcast keys. This may
		 * need to change with virtual interfaces. */
		idx = key->keyidx;
	} else if (key->keyidx) {
824 825 826 827
		if (WARN_ON(!sta))
			return -EOPNOTSUPP;
		mac = sta->addr;

828 829 830 831 832 833
		if (vif->type != NL80211_IFTYPE_AP) {
			/* Only keyidx 0 should be used with unicast key, but
			 * allow this for client mode for now. */
			idx = key->keyidx;
		} else
			return -EIO;
834
	} else {
835 836 837 838
		if (WARN_ON(!sta))
			return -EOPNOTSUPP;
		mac = sta->addr;

839 840 841 842 843
		if (key->alg == ALG_TKIP)
			idx = ath_reserve_key_cache_slot_tkip(sc);
		else
			idx = ath_reserve_key_cache_slot(sc);
		if (idx < 0)
844
			return -ENOSPC; /* no free key cache entries */
845 846 847
	}

	if (key->alg == ALG_TKIP)
848 849
		ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
				      vif->type == NL80211_IFTYPE_AP);
850
	else
851
		ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
852 853 854 855

	if (!ret)
		return -EIO;

856
	set_bit(idx, sc->keymap);
857
	if (key->alg == ALG_TKIP) {
858 859 860 861
		set_bit(idx + 64, sc->keymap);
		if (sc->splitmic) {
			set_bit(idx + 32, sc->keymap);
			set_bit(idx + 64 + 32, sc->keymap);
862 863 864 865
		}
	}

	return idx;
866 867 868 869
}

static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
{
870 871 872 873
	ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
	if (key->hw_key_idx < IEEE80211_WEP_NKID)
		return;

874
	clear_bit(key->hw_key_idx, sc->keymap);
875 876
	if (key->alg != ALG_TKIP)
		return;
877

878 879 880 881
	clear_bit(key->hw_key_idx + 64, sc->keymap);
	if (sc->splitmic) {
		clear_bit(key->hw_key_idx + 32, sc->keymap);
		clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
882
	}
883 884
}

885 886
static void setup_ht_cap(struct ath_softc *sc,
			 struct ieee80211_sta_ht_cap *ht_info)
887
{
888
	u8 tx_streams, rx_streams;
889

890 891 892 893 894
	ht_info->ht_supported = true;
	ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
		       IEEE80211_HT_CAP_SM_PS |
		       IEEE80211_HT_CAP_SGI_40 |
		       IEEE80211_HT_CAP_DSSSCCK40;
895

896 897
	ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
	ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
898

899 900
	/* set up supported mcs set */
	memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
901 902 903 904 905 906 907 908 909 910
	tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
	rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;

	if (tx_streams != rx_streams) {
		DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
			tx_streams, rx_streams);
		ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
		ht_info->mcs.tx_params |= ((tx_streams - 1) <<
				IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
	}
911

912 913
	ht_info->mcs.rx_mask[0] = 0xff;
	if (rx_streams >= 2)
914 915
		ht_info->mcs.rx_mask[1] = 0xff;

916
	ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
917 918
}

919
static void ath9k_bss_assoc_info(struct ath_softc *sc,
S
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920
				 struct ieee80211_vif *vif,
921
				 struct ieee80211_bss_conf *bss_conf)
922 923
{

924
	if (bss_conf->assoc) {
925
		DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
926
			bss_conf->aid, sc->curbssid);
927

928
		/* New association, store aid */
929 930 931 932 933 934 935 936 937
		sc->curaid = bss_conf->aid;
		ath9k_hw_write_associd(sc);

		/*
		 * Request a re-configuration of Beacon related timers
		 * on the receipt of the first Beacon frame (i.e.,
		 * after time sync with the AP).
		 */
		sc->sc_flags |= SC_OP_BEACON_SYNC;
938

939
		/* Configure the beacon */
940
		ath_beacon_config(sc, vif);
941

942
		/* Reset rssi stats */
943 944 945 946
		sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
		sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
		sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
		sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
947

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948
		ath_start_ani(sc);
949
	} else {
950
		DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
951
		sc->curaid = 0;
952 953
		/* Stop ANI */
		del_timer_sync(&sc->ani.timer);
954
	}
955
}
956

957 958 959
/********************************/
/*	 LED functions		*/
/********************************/
960

961 962 963 964 965 966 967
static void ath_led_blink_work(struct work_struct *work)
{
	struct ath_softc *sc = container_of(work, struct ath_softc,
					    ath_led_blink_work.work);

	if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
		return;
968 969 970

	if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
	    (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
971
		ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
972
	else
973
		ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
974
				  (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
975

976 977 978 979 980
	ieee80211_queue_delayed_work(sc->hw,
				     &sc->ath_led_blink_work,
				     (sc->sc_flags & SC_OP_LED_ON) ?
					msecs_to_jiffies(sc->led_off_duration) :
					msecs_to_jiffies(sc->led_on_duration));
981

982 983 984 985 986 987
	sc->led_on_duration = sc->led_on_cnt ?
			max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
			ATH_LED_ON_DURATION_IDLE;
	sc->led_off_duration = sc->led_off_cnt ?
			max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
			ATH_LED_OFF_DURATION_IDLE;
988 989 990 991 992 993 994
	sc->led_on_cnt = sc->led_off_cnt = 0;
	if (sc->sc_flags & SC_OP_LED_ON)
		sc->sc_flags &= ~SC_OP_LED_ON;
	else
		sc->sc_flags |= SC_OP_LED_ON;
}

995 996 997 998 999
static void ath_led_brightness(struct led_classdev *led_cdev,
			       enum led_brightness brightness)
{
	struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
	struct ath_softc *sc = led->sc;
1000

1001 1002 1003
	switch (brightness) {
	case LED_OFF:
		if (led->led_type == ATH_LED_ASSOC ||
1004
		    led->led_type == ATH_LED_RADIO) {
1005
			ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1006
				(led->led_type == ATH_LED_RADIO));
1007
			sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1008 1009 1010 1011 1012
			if (led->led_type == ATH_LED_RADIO)
				sc->sc_flags &= ~SC_OP_LED_ON;
		} else {
			sc->led_off_cnt++;
		}
1013 1014
		break;
	case LED_FULL:
1015
		if (led->led_type == ATH_LED_ASSOC) {
1016
			sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1017 1018
			ieee80211_queue_delayed_work(sc->hw,
						     &sc->ath_led_blink_work, 0);
1019
		} else if (led->led_type == ATH_LED_RADIO) {
1020
			ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1021 1022 1023 1024
			sc->sc_flags |= SC_OP_LED_ON;
		} else {
			sc->led_on_cnt++;
		}
1025 1026 1027
		break;
	default:
		break;
1028
	}
1029
}
1030

1031 1032 1033 1034
static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
			    char *trigger)
{
	int ret;
1035

1036 1037 1038 1039
	led->sc = sc;
	led->led_cdev.name = led->name;
	led->led_cdev.default_trigger = trigger;
	led->led_cdev.brightness_set = ath_led_brightness;
1040

1041 1042 1043 1044 1045 1046 1047 1048
	ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
	if (ret)
		DPRINTF(sc, ATH_DBG_FATAL,
			"Failed to register led:%s", led->name);
	else
		led->registered = 1;
	return ret;
}
1049

1050 1051 1052 1053 1054
static void ath_unregister_led(struct ath_led *led)
{
	if (led->registered) {
		led_classdev_unregister(&led->led_cdev);
		led->registered = 0;
1055 1056 1057
	}
}

1058
static void ath_deinit_leds(struct ath_softc *sc)
1059
{
1060 1061 1062 1063 1064
	ath_unregister_led(&sc->assoc_led);
	sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
	ath_unregister_led(&sc->tx_led);
	ath_unregister_led(&sc->rx_led);
	ath_unregister_led(&sc->radio_led);
1065
	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1066
}
1067

1068 1069 1070 1071
static void ath_init_leds(struct ath_softc *sc)
{
	char *trigger;
	int ret;
1072

1073 1074 1075 1076 1077
	if (AR_SREV_9287(sc->sc_ah))
		sc->sc_ah->led_pin = ATH_LED_PIN_9287;
	else
		sc->sc_ah->led_pin = ATH_LED_PIN_DEF;

1078
	/* Configure gpio 1 for output */
1079
	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1080 1081
			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
	/* LED off, active low */
1082
	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
S
Sujith 已提交
1083

1084 1085
	INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);

1086 1087
	trigger = ieee80211_get_radio_led_name(sc->hw);
	snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
D
Danny Kukawka 已提交
1088
		"ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1089 1090 1091 1092
	ret = ath_register_led(sc, &sc->radio_led, trigger);
	sc->radio_led.led_type = ATH_LED_RADIO;
	if (ret)
		goto fail;
S
Sujith 已提交
1093

1094 1095
	trigger = ieee80211_get_assoc_led_name(sc->hw);
	snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
D
Danny Kukawka 已提交
1096
		"ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1097 1098 1099 1100
	ret = ath_register_led(sc, &sc->assoc_led, trigger);
	sc->assoc_led.led_type = ATH_LED_ASSOC;
	if (ret)
		goto fail;
1101

1102 1103
	trigger = ieee80211_get_tx_led_name(sc->hw);
	snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
D
Danny Kukawka 已提交
1104
		"ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1105 1106 1107 1108
	ret = ath_register_led(sc, &sc->tx_led, trigger);
	sc->tx_led.led_type = ATH_LED_TX;
	if (ret)
		goto fail;
1109

1110 1111
	trigger = ieee80211_get_rx_led_name(sc->hw);
	snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
D
Danny Kukawka 已提交
1112
		"ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1113 1114 1115 1116
	ret = ath_register_led(sc, &sc->rx_led, trigger);
	sc->rx_led.led_type = ATH_LED_RX;
	if (ret)
		goto fail;
1117

1118 1119 1120
	return;

fail:
1121
	cancel_delayed_work_sync(&sc->ath_led_blink_work);
1122
	ath_deinit_leds(sc);
1123 1124
}

1125
void ath_radio_enable(struct ath_softc *sc)
1126
{
1127
	struct ath_hw *ah = sc->sc_ah;
1128 1129
	struct ieee80211_channel *channel = sc->hw->conf.channel;
	int r;
1130

1131
	ath9k_ps_wakeup(sc);
1132
	ath9k_hw_configpcipowersave(ah, 0);
1133

1134 1135 1136
	if (!ah->curchan)
		ah->curchan = ath_get_curchannel(sc, sc->hw);

1137
	spin_lock_bh(&sc->sc_resetlock);
1138
	r = ath9k_hw_reset(ah, ah->curchan, false);
1139
	if (r) {
1140
		DPRINTF(sc, ATH_DBG_FATAL,
1141
			"Unable to reset channel %u (%uMhz) ",
1142
			"reset status %d\n",
1143
			channel->center_freq, r);
1144 1145 1146 1147 1148 1149
	}
	spin_unlock_bh(&sc->sc_resetlock);

	ath_update_txpow(sc);
	if (ath_startrecv(sc) != 0) {
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1150
			"Unable to restart recv logic\n");
1151 1152 1153 1154
		return;
	}

	if (sc->sc_flags & SC_OP_BEACONS)
1155
		ath_beacon_config(sc, NULL);	/* restart beacons */
1156 1157

	/* Re-Enable  interrupts */
1158
	ath9k_hw_set_interrupts(ah, sc->imask);
1159 1160

	/* Enable LED */
1161
	ath9k_hw_cfg_output(ah, ah->led_pin,
1162
			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1163
	ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1164 1165

	ieee80211_wake_queues(sc->hw);
1166
	ath9k_ps_restore(sc);
1167 1168
}

1169
void ath_radio_disable(struct ath_softc *sc)
1170
{
1171
	struct ath_hw *ah = sc->sc_ah;
1172 1173
	struct ieee80211_channel *channel = sc->hw->conf.channel;
	int r;
1174

1175
	ath9k_ps_wakeup(sc);
1176 1177 1178
	ieee80211_stop_queues(sc->hw);

	/* Disable LED */
1179 1180
	ath9k_hw_set_gpio(ah, ah->led_pin, 1);
	ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1181 1182 1183 1184

	/* Disable interrupts */
	ath9k_hw_set_interrupts(ah, 0);

1185
	ath_drain_all_txq(sc, false);	/* clear pending tx frames */
1186 1187 1188
	ath_stoprecv(sc);		/* turn off frame recv */
	ath_flushrecv(sc);		/* flush recv queue */

1189 1190 1191
	if (!ah->curchan)
		ah->curchan = ath_get_curchannel(sc, sc->hw);

1192
	spin_lock_bh(&sc->sc_resetlock);
1193
	r = ath9k_hw_reset(ah, ah->curchan, false);
1194
	if (r) {
1195
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1196
			"Unable to reset channel %u (%uMhz) "
1197
			"reset status %d\n",
1198
			channel->center_freq, r);
1199 1200 1201 1202
	}
	spin_unlock_bh(&sc->sc_resetlock);

	ath9k_hw_phy_disable(ah);
1203
	ath9k_hw_configpcipowersave(ah, 1);
1204
	ath9k_ps_restore(sc);
1205
	ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1206 1207
}

1208 1209 1210 1211
/*******************/
/*	Rfkill	   */
/*******************/

1212 1213
static bool ath_is_rfkill_set(struct ath_softc *sc)
{
1214
	struct ath_hw *ah = sc->sc_ah;
1215

1216 1217
	return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
				  ah->rfkill_polarity;
1218 1219
}

1220
static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1221
{
1222 1223
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
J
Johannes Berg 已提交
1224
	bool blocked = !!ath_is_rfkill_set(sc);
1225

1226 1227 1228
	wiphy_rfkill_set_hw_state(hw->wiphy, blocked);

	if (blocked)
J
Johannes Berg 已提交
1229 1230 1231
		ath_radio_disable(sc);
	else
		ath_radio_enable(sc);
1232 1233
}

1234
static void ath_start_rfkill_poll(struct ath_softc *sc)
1235
{
1236
	struct ath_hw *ah = sc->sc_ah;
S
Sujith 已提交
1237

1238 1239
	if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
		wiphy_rfkill_start_polling(sc->hw->wiphy);
S
Sujith 已提交
1240
}
1241

1242
void ath_cleanup(struct ath_softc *sc)
1243 1244 1245 1246
{
	ath_detach(sc);
	free_irq(sc->irq, sc);
	ath_bus_cleanup(sc);
1247
	kfree(sc->sec_wiphy);
1248 1249 1250
	ieee80211_free_hw(sc->hw);
}

1251
void ath_detach(struct ath_softc *sc)
1252
{
1253
	struct ieee80211_hw *hw = sc->hw;
S
Sujith 已提交
1254
	int i = 0;
1255

1256 1257
	ath9k_ps_wakeup(sc);

S
Sujith 已提交
1258
	DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1259

1260 1261
	ath_deinit_leds(sc);

1262 1263 1264 1265 1266 1267 1268 1269
	for (i = 0; i < sc->num_sec_wiphy; i++) {
		struct ath_wiphy *aphy = sc->sec_wiphy[i];
		if (aphy == NULL)
			continue;
		sc->sec_wiphy[i] = NULL;
		ieee80211_unregister_hw(aphy->hw);
		ieee80211_free_hw(aphy->hw);
	}
1270
	ieee80211_unregister_hw(hw);
1271 1272
	ath_rx_cleanup(sc);
	ath_tx_cleanup(sc);
1273

S
Sujith 已提交
1274 1275
	tasklet_kill(&sc->intr_tq);
	tasklet_kill(&sc->bcon_tasklet);
1276

S
Sujith 已提交
1277 1278
	if (!(sc->sc_flags & SC_OP_INVALID))
		ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1279

S
Sujith 已提交
1280 1281 1282
	/* cleanup tx queues */
	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
		if (ATH_TXQ_SETUP(sc, i))
S
Sujith 已提交
1283
			ath_tx_cleanupq(sc, &sc->tx.txq[i]);
S
Sujith 已提交
1284 1285

	ath9k_hw_detach(sc->sc_ah);
1286
	sc->sc_ah = NULL;
1287
	ath9k_exit_debug(sc);
1288 1289
}

1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300
static int ath9k_reg_notifier(struct wiphy *wiphy,
			      struct regulatory_request *request)
{
	struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
	struct ath_regulatory *reg = &sc->sc_ah->regulatory;

	return ath_reg_notifier_apply(wiphy, request, reg);
}

1301 1302 1303 1304 1305 1306 1307
/*
 * Initialize and fill ath_softc, ath_sofct is the
 * "Software Carrier" struct. Historically it has existed
 * to allow the separation between hardware specific
 * variables (now in ath_hw) and driver specific variables.
 */
static int ath_init_softc(u16 devid, struct ath_softc *sc)
S
Sujith 已提交
1308
{
1309
	struct ath_hw *ah = NULL;
1310
	int r = 0, i;
S
Sujith 已提交
1311 1312 1313 1314
	int csz = 0;

	/* XXX: hardware will not be ready until ath_open() being called */
	sc->sc_flags |= SC_OP_INVALID;
1315

1316 1317
	if (ath9k_init_debug(sc) < 0)
		printk(KERN_ERR "Unable to create debugfs files\n");
S
Sujith 已提交
1318

1319
	spin_lock_init(&sc->wiphy_lock);
S
Sujith 已提交
1320
	spin_lock_init(&sc->sc_resetlock);
1321
	spin_lock_init(&sc->sc_serial_rw);
1322
	spin_lock_init(&sc->ani_lock);
1323
	spin_lock_init(&sc->sc_pm_lock);
1324
	mutex_init(&sc->mutex);
S
Sujith 已提交
1325
	tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
S
Sujith 已提交
1326
	tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
S
Sujith 已提交
1327 1328 1329 1330 1331 1332
		     (unsigned long)sc);

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
1333
	ath_read_cachesize(sc, &csz);
S
Sujith 已提交
1334
	/* XXX assert csz is non-zero */
1335
	sc->common.cachelsz = csz << 2;	/* convert to bytes */
S
Sujith 已提交
1336

1337 1338 1339 1340 1341 1342 1343
	ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
	if (!ah) {
		r = -ENOMEM;
		goto bad_no_ah;
	}

	ah->ah_sc = sc;
1344
	ah->hw_version.devid = devid;
1345
	sc->sc_ah = ah;
1346

1347
	r = ath9k_hw_init(ah);
1348
	if (r) {
S
Sujith 已提交
1349
		DPRINTF(sc, ATH_DBG_FATAL,
1350
			"Unable to initialize hardware; "
1351
			"initialization status: %d\n", r);
S
Sujith 已提交
1352 1353 1354 1355
		goto bad;
	}

	/* Get the hardware key cache size. */
1356
	sc->keymax = ah->caps.keycache_size;
1357
	if (sc->keymax > ATH_KEYMAX) {
S
Sujith 已提交
1358
		DPRINTF(sc, ATH_DBG_ANY,
S
Sujith 已提交
1359
			"Warning, using only %u entries in %u key cache\n",
1360 1361
			ATH_KEYMAX, sc->keymax);
		sc->keymax = ATH_KEYMAX;
S
Sujith 已提交
1362 1363 1364 1365 1366 1367
	}

	/*
	 * Reset the key cache since some parts do not
	 * reset the contents on initial power up.
	 */
1368
	for (i = 0; i < sc->keymax; i++)
S
Sujith 已提交
1369 1370 1371
		ath9k_hw_keyreset(ah, (u16) i);

	/* default to MONITOR mode */
1372
	sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1373

S
Sujith 已提交
1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385
	/* Setup rate tables */

	ath_rate_attach(sc);
	ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
	ath_setup_rates(sc, IEEE80211_BAND_5GHZ);

	/*
	 * Allocate hardware transmit queues: one queue for
	 * beacon frames and one data queue for each QoS
	 * priority.  Note that the hal handles reseting
	 * these queues at the needed time.
	 */
S
Sujith 已提交
1386 1387
	sc->beacon.beaconq = ath_beaconq_setup(ah);
	if (sc->beacon.beaconq == -1) {
S
Sujith 已提交
1388
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1389
			"Unable to setup a beacon xmit queue\n");
1390
		r = -EIO;
S
Sujith 已提交
1391 1392
		goto bad2;
	}
S
Sujith 已提交
1393 1394
	sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
	if (sc->beacon.cabq == NULL) {
S
Sujith 已提交
1395
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1396
			"Unable to setup CAB xmit queue\n");
1397
		r = -EIO;
S
Sujith 已提交
1398 1399 1400
		goto bad2;
	}

1401
	sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
S
Sujith 已提交
1402 1403
	ath_cabq_update(sc);

S
Sujith 已提交
1404 1405
	for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
		sc->tx.hwq_map[i] = -1;
S
Sujith 已提交
1406 1407 1408 1409 1410

	/* Setup data queues */
	/* NB: ensure BK queue is the lowest priority h/w queue */
	if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1411
			"Unable to setup xmit queue for BK traffic\n");
1412
		r = -EIO;
S
Sujith 已提交
1413 1414 1415 1416 1417
		goto bad2;
	}

	if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1418
			"Unable to setup xmit queue for BE traffic\n");
1419
		r = -EIO;
S
Sujith 已提交
1420 1421 1422 1423
		goto bad2;
	}
	if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1424
			"Unable to setup xmit queue for VI traffic\n");
1425
		r = -EIO;
S
Sujith 已提交
1426 1427 1428 1429
		goto bad2;
	}
	if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
1430
			"Unable to setup xmit queue for VO traffic\n");
1431
		r = -EIO;
S
Sujith 已提交
1432 1433 1434 1435 1436 1437
		goto bad2;
	}

	/* Initializes the noise floor to a reasonable default value.
	 * Later on this will be updated during ANI processing. */

1438 1439
	sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
	setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
S
Sujith 已提交
1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464

	if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
				   ATH9K_CIPHER_TKIP, NULL)) {
		/*
		 * Whether we should enable h/w TKIP MIC.
		 * XXX: if we don't support WME TKIP MIC, then we wouldn't
		 * report WMM capable, so it's always safe to turn on
		 * TKIP MIC in this case.
		 */
		ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
				       0, 1, NULL);
	}

	/*
	 * Check whether the separate key cache entries
	 * are required to handle both tx+rx MIC keys.
	 * With split mic keys the number of stations is limited
	 * to 27 otherwise 59.
	 */
	if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
				   ATH9K_CIPHER_TKIP, NULL)
	    && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
				      ATH9K_CIPHER_MIC, NULL)
	    && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
				      0, NULL))
1465
		sc->splitmic = 1;
S
Sujith 已提交
1466 1467 1468 1469 1470 1471

	/* turn on mcast key search if possible */
	if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
		(void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
					     1, NULL);

1472
	sc->config.txpowlimit = ATH_TXPOWER_MAX;
S
Sujith 已提交
1473 1474

	/* 11n Capabilities */
1475
	if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
S
Sujith 已提交
1476 1477 1478 1479
		sc->sc_flags |= SC_OP_TXAGGR;
		sc->sc_flags |= SC_OP_RXAGGR;
	}

1480 1481
	sc->tx_chainmask = ah->caps.tx_chainmask;
	sc->rx_chainmask = ah->caps.rx_chainmask;
S
Sujith 已提交
1482 1483

	ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
S
Sujith 已提交
1484
	sc->rx.defant = ath9k_hw_getdefantenna(ah);
S
Sujith 已提交
1485

1486
	if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1487
		memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
S
Sujith 已提交
1488

S
Sujith 已提交
1489
	sc->beacon.slottime = ATH9K_SLOT_TIME_9;	/* default to short slot time */
S
Sujith 已提交
1490 1491

	/* initialize beacon slots */
1492
	for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1493
		sc->beacon.bslot[i] = NULL;
1494 1495
		sc->beacon.bslot_aphy[i] = NULL;
	}
S
Sujith 已提交
1496 1497 1498

	/* setup channels and rates */

1499
	sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
S
Sujith 已提交
1500 1501 1502
	sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
		sc->rates[IEEE80211_BAND_2GHZ];
	sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1503 1504
	sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
		ARRAY_SIZE(ath9k_2ghz_chantable);
S
Sujith 已提交
1505

1506
	if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1507
		sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
S
Sujith 已提交
1508 1509 1510
		sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
			sc->rates[IEEE80211_BAND_5GHZ];
		sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1511 1512
		sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
			ARRAY_SIZE(ath9k_5ghz_chantable);
S
Sujith 已提交
1513 1514
	}

1515
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1516 1517
		ath9k_hw_btcoex_enable(sc->sc_ah);

S
Sujith 已提交
1518 1519 1520 1521 1522
	return 0;
bad2:
	/* cleanup tx queues */
	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
		if (ATH_TXQ_SETUP(sc, i))
S
Sujith 已提交
1523
			ath_tx_cleanupq(sc, &sc->tx.txq[i]);
S
Sujith 已提交
1524
bad:
1525
	ath9k_hw_detach(ah);
1526
	sc->sc_ah = NULL;
1527
bad_no_ah:
1528
	ath9k_exit_debug(sc);
S
Sujith 已提交
1529

1530
	return r;
S
Sujith 已提交
1531 1532
}

1533
void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1534
{
S
Sujith 已提交
1535 1536 1537
	hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
		IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
		IEEE80211_HW_SIGNAL_DBM |
1538 1539
		IEEE80211_HW_AMPDU_AGGREGATION |
		IEEE80211_HW_SUPPORTS_PS |
1540 1541
		IEEE80211_HW_PS_NULLFUNC_STACK |
		IEEE80211_HW_SPECTRUM_MGMT;
1542

1543
	if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1544 1545
		hw->flags |= IEEE80211_HW_MFP_CAPABLE;

S
Sujith 已提交
1546 1547 1548
	hw->wiphy->interface_modes =
		BIT(NL80211_IFTYPE_AP) |
		BIT(NL80211_IFTYPE_STATION) |
1549 1550
		BIT(NL80211_IFTYPE_ADHOC) |
		BIT(NL80211_IFTYPE_MESH_POINT);
1551

1552
	hw->queues = 4;
S
Sujith 已提交
1553
	hw->max_rates = 4;
1554
	hw->channel_change_time = 5000;
1555
	hw->max_listen_interval = 10;
1556 1557
	/* Hardware supports 10 but we use 4 */
	hw->max_rate_tries = 4;
1558
	hw->sta_data_size = sizeof(struct ath_node);
1559
	hw->vif_data_size = sizeof(struct ath_vif);
1560

1561
	hw->rate_control_algorithm = "ath9k_rate_control";
1562

1563 1564 1565 1566 1567 1568 1569
	hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
		&sc->sbands[IEEE80211_BAND_2GHZ];
	if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
		hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
			&sc->sbands[IEEE80211_BAND_5GHZ];
}

1570 1571
/* Device driver core initialization */
int ath_init_device(u16 devid, struct ath_softc *sc)
1572 1573 1574
{
	struct ieee80211_hw *hw = sc->hw;
	int error = 0, i;
1575
	struct ath_regulatory *reg;
1576 1577 1578

	DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");

1579
	error = ath_init_softc(devid, sc);
1580 1581 1582 1583 1584 1585 1586 1587 1588
	if (error != 0)
		return error;

	/* get mac address from hardware and set in mac80211 */

	SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);

	ath_set_hw_capab(sc, hw);

1589 1590 1591 1592 1593 1594 1595
	error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
			      ath9k_reg_notifier);
	if (error)
		return error;

	reg = &sc->sc_ah->regulatory;

1596
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1597
		setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1598
		if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1599
			setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
S
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1600 1601
	}

1602 1603 1604
	/* initialize tx/rx engine */
	error = ath_tx_init(sc, ATH_TXBUF);
	if (error != 0)
1605
		goto error_attach;
1606

1607 1608
	error = ath_rx_init(sc, ATH_RXBUF);
	if (error != 0)
1609
		goto error_attach;
1610

1611
	INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1612 1613
	INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
	sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1614

1615
	error = ieee80211_register_hw(hw);
1616

1617
	if (!ath_is_world_regd(reg)) {
1618
		error = regulatory_hint(hw->wiphy, reg->alpha2);
1619 1620 1621
		if (error)
			goto error_attach;
	}
1622

1623 1624
	/* Initialize LED control */
	ath_init_leds(sc);
1625

1626
	ath_start_rfkill_poll(sc);
1627

1628
	return 0;
1629 1630 1631 1632 1633 1634 1635 1636

error_attach:
	/* cleanup tx queues */
	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
		if (ATH_TXQ_SETUP(sc, i))
			ath_tx_cleanupq(sc, &sc->tx.txq[i]);

	ath9k_hw_detach(sc->sc_ah);
1637
	sc->sc_ah = NULL;
1638 1639
	ath9k_exit_debug(sc);

1640
	return error;
1641 1642
}

S
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1643 1644
int ath_reset(struct ath_softc *sc, bool retry_tx)
{
1645
	struct ath_hw *ah = sc->sc_ah;
1646
	struct ieee80211_hw *hw = sc->hw;
1647
	int r;
S
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1648 1649

	ath9k_hw_set_interrupts(ah, 0);
1650
	ath_drain_all_txq(sc, retry_tx);
S
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1651 1652 1653 1654
	ath_stoprecv(sc);
	ath_flushrecv(sc);

	spin_lock_bh(&sc->sc_resetlock);
1655
	r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1656
	if (r)
S
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1657
		DPRINTF(sc, ATH_DBG_FATAL,
1658
			"Unable to reset hardware; reset status %d\n", r);
S
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1659 1660 1661
	spin_unlock_bh(&sc->sc_resetlock);

	if (ath_startrecv(sc) != 0)
S
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1662
		DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
S
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1663 1664 1665 1666 1667 1668

	/*
	 * We may be doing a reset in response to a request
	 * that changes the channel so update any state that
	 * might change as a result.
	 */
1669
	ath_cache_conf_rate(sc, &hw->conf);
S
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1670 1671 1672 1673

	ath_update_txpow(sc);

	if (sc->sc_flags & SC_OP_BEACONS)
1674
		ath_beacon_config(sc, NULL);	/* restart beacons */
S
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1675

1676
	ath9k_hw_set_interrupts(ah, sc->imask);
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1677 1678 1679 1680 1681

	if (retry_tx) {
		int i;
		for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
			if (ATH_TXQ_SETUP(sc, i)) {
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1682 1683 1684
				spin_lock_bh(&sc->tx.txq[i].axq_lock);
				ath_txq_schedule(sc, &sc->tx.txq[i]);
				spin_unlock_bh(&sc->tx.txq[i].axq_lock);
S
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1685 1686 1687 1688
			}
		}
	}

1689
	return r;
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}

/*
 *  This function will allocate both the DMA descriptor structure, and the
 *  buffers it contains.  These are used to contain the descriptors used
 *  by the system.
*/
int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
		      struct list_head *head, const char *name,
		      int nbuf, int ndesc)
{
#define	DS2PHYS(_dd, _ds)						\
	((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)

	struct ath_desc *ds;
	struct ath_buf *bf;
	int i, bsize, error;

S
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1710 1711
	DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
		name, nbuf, ndesc);
S
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1712

1713
	INIT_LIST_HEAD(head);
S
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1714 1715
	/* ath_desc must be a multiple of DWORDs */
	if ((sizeof(struct ath_desc) % 4) != 0) {
S
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1716
		DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
S
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1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728
		ASSERT((sizeof(struct ath_desc) % 4) == 0);
		error = -ENOMEM;
		goto fail;
	}

	dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;

	/*
	 * Need additional DMA memory because we can't use
	 * descriptors that cross the 4K page boundary. Assume
	 * one skipped descriptor per 4K page.
	 */
1729
	if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
S
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1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742
		u32 ndesc_skipped =
			ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
		u32 dma_len;

		while (ndesc_skipped) {
			dma_len = ndesc_skipped * sizeof(struct ath_desc);
			dd->dd_desc_len += dma_len;

			ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
		};
	}

	/* allocate descriptors */
1743
	dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1744
					 &dd->dd_desc_paddr, GFP_KERNEL);
S
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1745 1746 1747 1748 1749
	if (dd->dd_desc == NULL) {
		error = -ENOMEM;
		goto fail;
	}
	ds = dd->dd_desc;
S
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1750
	DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1751
		name, ds, (u32) dd->dd_desc_len,
S
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1752 1753 1754 1755
		ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);

	/* allocate buffers */
	bsize = sizeof(struct ath_buf) * nbuf;
1756
	bf = kzalloc(bsize, GFP_KERNEL);
S
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1757 1758 1759 1760 1761 1762 1763 1764 1765 1766
	if (bf == NULL) {
		error = -ENOMEM;
		goto fail2;
	}
	dd->dd_bufptr = bf;

	for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
		bf->bf_desc = ds;
		bf->bf_daddr = DS2PHYS(dd, ds);

1767
		if (!(sc->sc_ah->caps.hw_caps &
S
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1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787
		      ATH9K_HW_CAP_4KB_SPLITTRANS)) {
			/*
			 * Skip descriptor addresses which can cause 4KB
			 * boundary crossing (addr + length) with a 32 dword
			 * descriptor fetch.
			 */
			while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
				ASSERT((caddr_t) bf->bf_desc <
				       ((caddr_t) dd->dd_desc +
					dd->dd_desc_len));

				ds += ndesc;
				bf->bf_desc = ds;
				bf->bf_daddr = DS2PHYS(dd, ds);
			}
		}
		list_add_tail(&bf->list, head);
	}
	return 0;
fail2:
1788 1789
	dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
			  dd->dd_desc_paddr);
S
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1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801
fail:
	memset(dd, 0, sizeof(*dd));
	return error;
#undef ATH_DESC_4KB_BOUND_CHECK
#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
#undef DS2PHYS
}

void ath_descdma_cleanup(struct ath_softc *sc,
			 struct ath_descdma *dd,
			 struct list_head *head)
{
1802 1803
	dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
			  dd->dd_desc_paddr);
S
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1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815

	INIT_LIST_HEAD(head);
	kfree(dd->dd_bufptr);
	memset(dd, 0, sizeof(*dd));
}

int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
{
	int qnum;

	switch (queue) {
	case 0:
S
Sujith 已提交
1816
		qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
S
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1817 1818
		break;
	case 1:
S
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1819
		qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
S
Sujith 已提交
1820 1821
		break;
	case 2:
S
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1822
		qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
S
Sujith 已提交
1823 1824
		break;
	case 3:
S
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1825
		qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
S
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1826 1827
		break;
	default:
S
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1828
		qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
S
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1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859
		break;
	}

	return qnum;
}

int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
{
	int qnum;

	switch (queue) {
	case ATH9K_WME_AC_VO:
		qnum = 0;
		break;
	case ATH9K_WME_AC_VI:
		qnum = 1;
		break;
	case ATH9K_WME_AC_BE:
		qnum = 2;
		break;
	case ATH9K_WME_AC_BK:
		qnum = 3;
		break;
	default:
		qnum = -1;
		break;
	}

	return qnum;
}

1860 1861
/* XXX: Remove me once we don't depend on ath9k_channel for all
 * this redundant data */
1862 1863
void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
			   struct ath9k_channel *ichan)
1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889
{
	struct ieee80211_channel *chan = hw->conf.channel;
	struct ieee80211_conf *conf = &hw->conf;

	ichan->channel = chan->center_freq;
	ichan->chan = chan;

	if (chan->band == IEEE80211_BAND_2GHZ) {
		ichan->chanmode = CHANNEL_G;
		ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
	} else {
		ichan->chanmode = CHANNEL_A;
		ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
	}

	sc->tx_chan_width = ATH9K_HT_MACMODE_20;

	if (conf_is_ht(conf)) {
		if (conf_is_ht40(conf))
			sc->tx_chan_width = ATH9K_HT_MACMODE_2040;

		ichan->chanmode = ath_get_extchanmode(sc, chan,
					    conf->channel_type);
	}
}

S
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1890 1891 1892 1893
/**********************/
/* mac80211 callbacks */
/**********************/

1894
static int ath9k_start(struct ieee80211_hw *hw)
1895
{
1896 1897
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
1898
	struct ieee80211_channel *curchan = hw->conf.channel;
S
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1899
	struct ath9k_channel *init_channel;
1900
	int r;
1901

S
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1902 1903
	DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
		"initial channel: %d MHz\n", curchan->center_freq);
1904

1905 1906
	mutex_lock(&sc->mutex);

1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927
	if (ath9k_wiphy_started(sc)) {
		if (sc->chan_idx == curchan->hw_value) {
			/*
			 * Already on the operational channel, the new wiphy
			 * can be marked active.
			 */
			aphy->state = ATH_WIPHY_ACTIVE;
			ieee80211_wake_queues(hw);
		} else {
			/*
			 * Another wiphy is on another channel, start the new
			 * wiphy in paused state.
			 */
			aphy->state = ATH_WIPHY_PAUSED;
			ieee80211_stop_queues(hw);
		}
		mutex_unlock(&sc->mutex);
		return 0;
	}
	aphy->state = ATH_WIPHY_ACTIVE;

1928
	/* setup initial channel */
1929

1930
	sc->chan_idx = curchan->hw_value;
1931

1932
	init_channel = ath_get_curchannel(sc, hw);
S
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1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944

	/* Reset SERDES registers */
	ath9k_hw_configpcipowersave(sc->sc_ah, 0);

	/*
	 * The basic interface to setting the hardware in a good
	 * state is ``reset''.  On return the hardware is known to
	 * be powered up and with interrupts disabled.  This must
	 * be followed by initialization of the appropriate bits
	 * and then setup of the interrupt mask.
	 */
	spin_lock_bh(&sc->sc_resetlock);
1945 1946
	r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
	if (r) {
S
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1947
		DPRINTF(sc, ATH_DBG_FATAL,
1948
			"Unable to reset hardware; reset status %d "
1949 1950
			"(freq %u MHz)\n", r,
			curchan->center_freq);
S
Sujith 已提交
1951
		spin_unlock_bh(&sc->sc_resetlock);
1952
		goto mutex_unlock;
S
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1953 1954 1955 1956 1957 1958 1959 1960
	}
	spin_unlock_bh(&sc->sc_resetlock);

	/*
	 * This is needed only to setup initial state
	 * but it's best done after a reset.
	 */
	ath_update_txpow(sc);
1961

S
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1962 1963 1964 1965 1966 1967 1968 1969
	/*
	 * Setup the hardware after reset:
	 * The receive engine is set going.
	 * Frame transmit is handled entirely
	 * in the frame output path; there's nothing to do
	 * here except setup the interrupt mask.
	 */
	if (ath_startrecv(sc) != 0) {
1970
		DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1971 1972
		r = -EIO;
		goto mutex_unlock;
1973
	}
1974

S
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1975
	/* Setup our intr mask. */
1976
	sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
S
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1977 1978 1979
		| ATH9K_INT_RXEOL | ATH9K_INT_RXORN
		| ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;

1980
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1981
		sc->imask |= ATH9K_INT_GTT;
S
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1982

1983
	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1984
		sc->imask |= ATH9K_INT_CST;
S
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1985

1986
	ath_cache_conf_rate(sc, &hw->conf);
S
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1987 1988 1989 1990

	sc->sc_flags &= ~SC_OP_INVALID;

	/* Disable BMISS interrupt when we're not associated */
1991 1992
	sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
	ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
S
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1993

1994
	ieee80211_wake_queues(hw);
S
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1995

1996
	ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
1997

1998 1999 2000
mutex_unlock:
	mutex_unlock(&sc->mutex);

2001
	return r;
2002 2003
}

2004 2005
static int ath9k_tx(struct ieee80211_hw *hw,
		    struct sk_buff *skb)
2006
{
2007
	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2008 2009
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2010
	struct ath_tx_control txctl;
2011
	int hdrlen, padsize;
2012

2013
	if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2014 2015 2016 2017 2018
		printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
		       "%d\n", wiphy_name(hw->wiphy), aphy->state);
		goto exit;
	}

2019
	if (sc->ps_enabled) {
2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033
		struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
		/*
		 * mac80211 does not set PM field for normal data frames, so we
		 * need to update that based on the current PS mode.
		 */
		if (ieee80211_is_data(hdr->frame_control) &&
		    !ieee80211_is_nullfunc(hdr->frame_control) &&
		    !ieee80211_has_pm(hdr->frame_control)) {
			DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
				"while in PS mode\n");
			hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
		}
	}

2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058
	if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
		/*
		 * We are using PS-Poll and mac80211 can request TX while in
		 * power save mode. Need to wake up hardware for the TX to be
		 * completed and if needed, also for RX of buffered frames.
		 */
		struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
		ath9k_ps_wakeup(sc);
		ath9k_hw_setrxabort(sc->sc_ah, 0);
		if (ieee80211_is_pspoll(hdr->frame_control)) {
			DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
				"buffered frame\n");
			sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
		} else {
			DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
			sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
		}
		/*
		 * The actual restore operation will happen only after
		 * the sc_flags bit is cleared. We are just dropping
		 * the ps_usecount here.
		 */
		ath9k_ps_restore(sc);
	}

2059
	memset(&txctl, 0, sizeof(struct ath_tx_control));
2060

2061 2062 2063 2064 2065 2066 2067 2068
	/*
	 * As a temporary workaround, assign seq# here; this will likely need
	 * to be cleaned up to work better with Beacon transmission and virtual
	 * BSSes.
	 */
	if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
		struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
		if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
S
Sujith 已提交
2069
			sc->tx.seq_no += 0x10;
2070
		hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
S
Sujith 已提交
2071
		hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2072
	}
2073

2074 2075 2076 2077 2078 2079 2080 2081 2082 2083
	/* Add the padding after the header if this is not already done */
	hdrlen = ieee80211_get_hdrlen_from_skb(skb);
	if (hdrlen & 3) {
		padsize = hdrlen % 4;
		if (skb_headroom(skb) < padsize)
			return -1;
		skb_push(skb, padsize);
		memmove(skb->data, skb->data + padsize, hdrlen);
	}

2084 2085 2086 2087 2088 2089
	/* Check if a tx queue is available */

	txctl.txq = ath_test_get_txq(sc, skb);
	if (!txctl.txq)
		goto exit;

S
Sujith 已提交
2090
	DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2091

2092
	if (ath_tx_start(hw, skb, &txctl) != 0) {
S
Sujith 已提交
2093
		DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2094
		goto exit;
2095 2096
	}

2097 2098 2099
	return 0;
exit:
	dev_kfree_skb_any(skb);
2100
	return 0;
2101 2102
}

2103
static void ath9k_stop(struct ieee80211_hw *hw)
2104
{
2105 2106
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2107

2108 2109
	aphy->state = ATH_WIPHY_INACTIVE;

2110 2111 2112 2113 2114 2115 2116 2117
	cancel_delayed_work_sync(&sc->ath_led_blink_work);
	cancel_delayed_work_sync(&sc->tx_complete_work);

	if (!sc->num_sec_wiphy) {
		cancel_delayed_work_sync(&sc->wiphy_work);
		cancel_work_sync(&sc->chan_work);
	}

S
Sujith 已提交
2118
	if (sc->sc_flags & SC_OP_INVALID) {
S
Sujith 已提交
2119
		DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
S
Sujith 已提交
2120 2121
		return;
	}
2122

2123
	mutex_lock(&sc->mutex);
S
Sujith 已提交
2124

2125 2126
	cancel_delayed_work_sync(&sc->tx_complete_work);

2127 2128 2129 2130 2131
	if (ath9k_wiphy_started(sc)) {
		mutex_unlock(&sc->mutex);
		return; /* another wiphy still in use */
	}

S
Sujith 已提交
2132 2133 2134 2135 2136
	/* make sure h/w will not generate any interrupt
	 * before setting the invalid flag. */
	ath9k_hw_set_interrupts(sc->sc_ah, 0);

	if (!(sc->sc_flags & SC_OP_INVALID)) {
2137
		ath_drain_all_txq(sc, false);
S
Sujith 已提交
2138 2139 2140
		ath_stoprecv(sc);
		ath9k_hw_phy_disable(sc->sc_ah);
	} else
S
Sujith 已提交
2141
		sc->rx.rxlink = NULL;
S
Sujith 已提交
2142

2143
	wiphy_rfkill_stop_polling(sc->hw->wiphy);
J
Johannes Berg 已提交
2144

S
Sujith 已提交
2145 2146 2147
	/* disable HAL and put h/w to sleep */
	ath9k_hw_disable(sc->sc_ah);
	ath9k_hw_configpcipowersave(sc->sc_ah, 1);
S
Sujith 已提交
2148
	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
S
Sujith 已提交
2149 2150

	sc->sc_flags |= SC_OP_INVALID;
2151

2152 2153
	mutex_unlock(&sc->mutex);

S
Sujith 已提交
2154
	DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2155 2156
}

2157 2158
static int ath9k_add_interface(struct ieee80211_hw *hw,
			       struct ieee80211_if_init_conf *conf)
2159
{
2160 2161
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2162
	struct ath_vif *avp = (void *)conf->vif->drv_priv;
2163
	enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2164
	int ret = 0;
2165

2166 2167
	mutex_lock(&sc->mutex);

2168 2169 2170 2171 2172 2173
	if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
	    sc->nvifs > 0) {
		ret = -ENOBUFS;
		goto out;
	}

2174
	switch (conf->type) {
2175
	case NL80211_IFTYPE_STATION:
2176
		ic_opmode = NL80211_IFTYPE_STATION;
2177
		break;
2178 2179
	case NL80211_IFTYPE_ADHOC:
	case NL80211_IFTYPE_AP:
2180
	case NL80211_IFTYPE_MESH_POINT:
2181 2182 2183 2184
		if (sc->nbcnvifs >= ATH_BCBUF) {
			ret = -ENOBUFS;
			goto out;
		}
2185
		ic_opmode = conf->type;
2186 2187 2188
		break;
	default:
		DPRINTF(sc, ATH_DBG_FATAL,
S
Sujith 已提交
2189
			"Interface type %d not yet supported\n", conf->type);
2190 2191
		ret = -EOPNOTSUPP;
		goto out;
2192 2193
	}

2194
	DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2195

2196
	/* Set the VIF opmode */
S
Sujith 已提交
2197 2198 2199
	avp->av_opmode = ic_opmode;
	avp->av_bslot = -1;

2200
	sc->nvifs++;
2201 2202 2203 2204

	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
		ath9k_set_bssid_mask(hw);

2205 2206 2207
	if (sc->nvifs > 1)
		goto out; /* skip global settings for secondary vif */

2208
	if (ic_opmode == NL80211_IFTYPE_AP) {
S
Sujith 已提交
2209
		ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2210 2211
		sc->sc_flags |= SC_OP_TSF_RESET;
	}
S
Sujith 已提交
2212 2213

	/* Set the device opmode */
2214
	sc->sc_ah->opmode = ic_opmode;
S
Sujith 已提交
2215

2216 2217 2218 2219
	/*
	 * Enable MIB interrupts when there are hardware phy counters.
	 * Note we only do this (at the moment) for station mode.
	 */
2220
	if ((conf->type == NL80211_IFTYPE_STATION) ||
2221 2222
	    (conf->type == NL80211_IFTYPE_ADHOC) ||
	    (conf->type == NL80211_IFTYPE_MESH_POINT)) {
S
Sujith 已提交
2223
		sc->imask |= ATH9K_INT_MIB;
2224 2225 2226
		sc->imask |= ATH9K_INT_TSFOOR;
	}

2227
	ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2228

2229 2230 2231
	if (conf->type == NL80211_IFTYPE_AP    ||
	    conf->type == NL80211_IFTYPE_ADHOC ||
	    conf->type == NL80211_IFTYPE_MONITOR)
S
Sujith 已提交
2232
		ath_start_ani(sc);
2233

2234
out:
2235
	mutex_unlock(&sc->mutex);
2236
	return ret;
2237 2238
}

2239 2240
static void ath9k_remove_interface(struct ieee80211_hw *hw,
				   struct ieee80211_if_init_conf *conf)
2241
{
2242 2243
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2244
	struct ath_vif *avp = (void *)conf->vif->drv_priv;
2245
	int i;
2246

S
Sujith 已提交
2247
	DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2248

2249 2250
	mutex_lock(&sc->mutex);

2251
	/* Stop ANI */
2252
	del_timer_sync(&sc->ani.timer);
2253

2254
	/* Reclaim beacon resources */
2255 2256 2257
	if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
	    (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
	    (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
S
Sujith 已提交
2258
		ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2259
		ath_beacon_return(sc, avp);
2260
	}
2261

2262
	sc->sc_flags &= ~SC_OP_BEACONS;
2263

2264 2265 2266 2267 2268
	for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
		if (sc->beacon.bslot[i] == conf->vif) {
			printk(KERN_DEBUG "%s: vif had allocated beacon "
			       "slot\n", __func__);
			sc->beacon.bslot[i] = NULL;
2269
			sc->beacon.bslot_aphy[i] = NULL;
2270 2271 2272
		}
	}

2273
	sc->nvifs--;
2274 2275

	mutex_unlock(&sc->mutex);
2276 2277
}

2278
static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2279
{
2280 2281
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2282
	struct ieee80211_conf *conf = &hw->conf;
2283
	struct ath_hw *ah = sc->sc_ah;
2284
	bool all_wiphys_idle = false, disable_radio = false;
2285

2286
	mutex_lock(&sc->mutex);
2287

2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305
	/* Leave this as the first check */
	if (changed & IEEE80211_CONF_CHANGE_IDLE) {

		spin_lock_bh(&sc->wiphy_lock);
		all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
		spin_unlock_bh(&sc->wiphy_lock);

		if (conf->flags & IEEE80211_CONF_IDLE){
			if (all_wiphys_idle)
				disable_radio = true;
		}
		else if (all_wiphys_idle) {
			ath_radio_enable(sc);
			DPRINTF(sc, ATH_DBG_CONFIG,
				"not-idle: enabling radio\n");
		}
	}

2306 2307
	if (changed & IEEE80211_CONF_CHANGE_PS) {
		if (conf->flags & IEEE80211_CONF_PS) {
2308 2309 2310 2311 2312 2313 2314 2315
			if (!(ah->caps.hw_caps &
			      ATH9K_HW_CAP_AUTOSLEEP)) {
				if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
					sc->imask |= ATH9K_INT_TIM_TIMER;
					ath9k_hw_set_interrupts(sc->sc_ah,
							sc->imask);
				}
				ath9k_hw_setrxabort(sc->sc_ah, 1);
2316
			}
2317
			sc->ps_enabled = true;
2318
		} else {
2319
			sc->ps_enabled = false;
2320
			ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2321 2322 2323
			if (!(ah->caps.hw_caps &
			      ATH9K_HW_CAP_AUTOSLEEP)) {
				ath9k_hw_setrxabort(sc->sc_ah, 0);
2324 2325 2326 2327
				sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
						  SC_OP_WAIT_FOR_CAB |
						  SC_OP_WAIT_FOR_PSPOLL_DATA |
						  SC_OP_WAIT_FOR_TX_ACK);
2328 2329 2330 2331 2332
				if (sc->imask & ATH9K_INT_TIM_TIMER) {
					sc->imask &= ~ATH9K_INT_TIM_TIMER;
					ath9k_hw_set_interrupts(sc->sc_ah,
							sc->imask);
				}
2333 2334 2335 2336
			}
		}
	}

2337
	if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2338
		struct ieee80211_channel *curchan = hw->conf.channel;
2339
		int pos = curchan->hw_value;
2340

2341 2342 2343
		aphy->chan_idx = pos;
		aphy->chan_is_ht = conf_is_ht(conf);

2344 2345 2346 2347 2348 2349 2350 2351 2352 2353
		if (aphy->state == ATH_WIPHY_SCAN ||
		    aphy->state == ATH_WIPHY_ACTIVE)
			ath9k_wiphy_pause_all_forced(sc, aphy);
		else {
			/*
			 * Do not change operational channel based on a paused
			 * wiphy changes.
			 */
			goto skip_chan_change;
		}
2354

S
Sujith 已提交
2355 2356
		DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
			curchan->center_freq);
2357

2358
		/* XXX: remove me eventualy */
2359
		ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2360

2361
		ath_update_chainmask(sc, conf_is_ht(conf));
2362

2363
		if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
S
Sujith 已提交
2364
			DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2365
			mutex_unlock(&sc->mutex);
2366 2367
			return -EINVAL;
		}
2368
	}
2369

2370
skip_chan_change:
2371
	if (changed & IEEE80211_CONF_CHANGE_POWER)
2372
		sc->config.txpowlimit = 2 * conf->power_level;
2373

2374 2375 2376 2377 2378
	if (disable_radio) {
		DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
		ath_radio_disable(sc);
	}

2379
	mutex_unlock(&sc->mutex);
2380

2381 2382 2383
	return 0;
}

2384 2385 2386 2387
#define SUPPORTED_FILTERS			\
	(FIF_PROMISC_IN_BSS |			\
	FIF_ALLMULTI |				\
	FIF_CONTROL |				\
2388
	FIF_PSPOLL |				\
2389 2390 2391
	FIF_OTHER_BSS |				\
	FIF_BCN_PRBRESP_PROMISC |		\
	FIF_FCSFAIL)
2392

2393 2394 2395 2396
/* FIXME: sc->sc_full_reset ? */
static void ath9k_configure_filter(struct ieee80211_hw *hw,
				   unsigned int changed_flags,
				   unsigned int *total_flags,
2397
				   u64 multicast)
2398
{
2399 2400
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2401
	u32 rfilt;
2402

2403 2404
	changed_flags &= SUPPORTED_FILTERS;
	*total_flags &= SUPPORTED_FILTERS;
2405

S
Sujith 已提交
2406
	sc->rx.rxfilter = *total_flags;
2407
	ath9k_ps_wakeup(sc);
2408 2409
	rfilt = ath_calcrxfilter(sc);
	ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2410
	ath9k_ps_restore(sc);
2411

S
Sujith 已提交
2412
	DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2413
}
2414

2415 2416 2417
static void ath9k_sta_notify(struct ieee80211_hw *hw,
			     struct ieee80211_vif *vif,
			     enum sta_notify_cmd cmd,
2418
			     struct ieee80211_sta *sta)
2419
{
2420 2421
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2422

2423 2424
	switch (cmd) {
	case STA_NOTIFY_ADD:
S
Sujith 已提交
2425
		ath_node_attach(sc, sta);
2426 2427
		break;
	case STA_NOTIFY_REMOVE:
S
Sujith 已提交
2428
		ath_node_detach(sc, sta);
2429 2430 2431 2432
		break;
	default:
		break;
	}
2433 2434
}

2435
static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2436
			 const struct ieee80211_tx_queue_params *params)
2437
{
2438 2439
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2440 2441
	struct ath9k_tx_queue_info qi;
	int ret = 0, qnum;
2442

2443 2444
	if (queue >= WME_NUM_AC)
		return 0;
2445

2446 2447
	mutex_lock(&sc->mutex);

2448 2449
	memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));

2450 2451 2452 2453 2454
	qi.tqi_aifs = params->aifs;
	qi.tqi_cwmin = params->cw_min;
	qi.tqi_cwmax = params->cw_max;
	qi.tqi_burstTime = params->txop;
	qnum = ath_get_hal_qnum(queue, sc);
2455

2456
	DPRINTF(sc, ATH_DBG_CONFIG,
S
Sujith 已提交
2457
		"Configure tx [queue/halq] [%d/%d],  "
2458
		"aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
S
Sujith 已提交
2459 2460
		queue, qnum, params->aifs, params->cw_min,
		params->cw_max, params->txop);
2461

2462 2463
	ret = ath_txq_update(sc, qnum, &qi);
	if (ret)
S
Sujith 已提交
2464
		DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2465

2466 2467
	mutex_unlock(&sc->mutex);

2468 2469
	return ret;
}
2470

2471 2472
static int ath9k_set_key(struct ieee80211_hw *hw,
			 enum set_key_cmd cmd,
2473 2474
			 struct ieee80211_vif *vif,
			 struct ieee80211_sta *sta,
2475 2476
			 struct ieee80211_key_conf *key)
{
2477 2478
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2479
	int ret = 0;
2480

2481 2482 2483
	if (modparam_nohwcrypt)
		return -ENOSPC;

2484
	mutex_lock(&sc->mutex);
2485
	ath9k_ps_wakeup(sc);
S
Sujith 已提交
2486
	DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2487

2488 2489
	switch (cmd) {
	case SET_KEY:
2490
		ret = ath_key_config(sc, vif, sta, key);
2491 2492
		if (ret >= 0) {
			key->hw_key_idx = ret;
2493 2494 2495 2496
			/* push IV and Michael MIC generation to stack */
			key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
			if (key->alg == ALG_TKIP)
				key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2497 2498
			if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
				key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2499
			ret = 0;
2500 2501 2502 2503 2504 2505 2506 2507
		}
		break;
	case DISABLE_KEY:
		ath_key_delete(sc, key);
		break;
	default:
		ret = -EINVAL;
	}
2508

2509
	ath9k_ps_restore(sc);
2510 2511
	mutex_unlock(&sc->mutex);

2512 2513
	return ret;
}
2514

2515 2516 2517 2518 2519
static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
				   struct ieee80211_vif *vif,
				   struct ieee80211_bss_conf *bss_conf,
				   u32 changed)
{
2520 2521
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2522 2523 2524 2525
	struct ath_hw *ah = sc->sc_ah;
	struct ath_vif *avp = (void *)vif->drv_priv;
	u32 rfilt = 0;
	int error, i;
2526

2527 2528
	mutex_lock(&sc->mutex);

2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607
	/*
	 * TODO: Need to decide which hw opmode to use for
	 *       multi-interface cases
	 * XXX: This belongs into add_interface!
	 */
	if (vif->type == NL80211_IFTYPE_AP &&
	    ah->opmode != NL80211_IFTYPE_AP) {
		ah->opmode = NL80211_IFTYPE_STATION;
		ath9k_hw_setopmode(ah);
		memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
		sc->curaid = 0;
		ath9k_hw_write_associd(sc);
		/* Request full reset to get hw opmode changed properly */
		sc->sc_flags |= SC_OP_FULL_RESET;
	}

	if ((changed & BSS_CHANGED_BSSID) &&
	    !is_zero_ether_addr(bss_conf->bssid)) {
		switch (vif->type) {
		case NL80211_IFTYPE_STATION:
		case NL80211_IFTYPE_ADHOC:
		case NL80211_IFTYPE_MESH_POINT:
			/* Set BSSID */
			memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
			memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
			sc->curaid = 0;
			ath9k_hw_write_associd(sc);

			/* Set aggregation protection mode parameters */
			sc->config.ath_aggr_prot = 0;

			DPRINTF(sc, ATH_DBG_CONFIG,
				"RX filter 0x%x bssid %pM aid 0x%x\n",
				rfilt, sc->curbssid, sc->curaid);

			/* need to reconfigure the beacon */
			sc->sc_flags &= ~SC_OP_BEACONS ;

			break;
		default:
			break;
		}
	}

	if ((vif->type == NL80211_IFTYPE_ADHOC) ||
	    (vif->type == NL80211_IFTYPE_AP) ||
	    (vif->type == NL80211_IFTYPE_MESH_POINT)) {
		if ((changed & BSS_CHANGED_BEACON) ||
		    (changed & BSS_CHANGED_BEACON_ENABLED &&
		     bss_conf->enable_beacon)) {
			/*
			 * Allocate and setup the beacon frame.
			 *
			 * Stop any previous beacon DMA.  This may be
			 * necessary, for example, when an ibss merge
			 * causes reconfiguration; we may be called
			 * with beacon transmission active.
			 */
			ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);

			error = ath_beacon_alloc(aphy, vif);
			if (!error)
				ath_beacon_config(sc, vif);
		}
	}

	/* Check for WLAN_CAPABILITY_PRIVACY ? */
	if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
		for (i = 0; i < IEEE80211_WEP_NKID; i++)
			if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
				ath9k_hw_keysetmac(sc->sc_ah,
						   (u16)i,
						   sc->curbssid);
	}

	/* Only legacy IBSS for now */
	if (vif->type == NL80211_IFTYPE_ADHOC)
		ath_update_chainmask(sc, 0);

2608
	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
S
Sujith 已提交
2609
		DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2610 2611 2612 2613 2614 2615
			bss_conf->use_short_preamble);
		if (bss_conf->use_short_preamble)
			sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
		else
			sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
	}
2616

2617
	if (changed & BSS_CHANGED_ERP_CTS_PROT) {
S
Sujith 已提交
2618
		DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2619 2620 2621 2622 2623 2624 2625
			bss_conf->use_cts_prot);
		if (bss_conf->use_cts_prot &&
		    hw->conf.channel->band != IEEE80211_BAND_5GHZ)
			sc->sc_flags |= SC_OP_PROTECT_ENABLE;
		else
			sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
	}
2626

2627
	if (changed & BSS_CHANGED_ASSOC) {
S
Sujith 已提交
2628
		DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2629
			bss_conf->assoc);
S
Sujith 已提交
2630
		ath9k_bss_assoc_info(sc, vif, bss_conf);
2631
	}
2632

2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644
	/*
	 * The HW TSF has to be reset when the beacon interval changes.
	 * We set the flag here, and ath_beacon_config_ap() would take this
	 * into account when it gets called through the subsequent
	 * config_interface() call - with IFCC_BEACON in the changed field.
	 */

	if (changed & BSS_CHANGED_BEACON_INT) {
		sc->sc_flags |= SC_OP_TSF_RESET;
		sc->beacon_interval = bss_conf->beacon_int;
	}

2645
	mutex_unlock(&sc->mutex);
2646
}
2647

2648 2649 2650
static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
{
	u64 tsf;
2651 2652
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2653

2654 2655 2656
	mutex_lock(&sc->mutex);
	tsf = ath9k_hw_gettsf64(sc->sc_ah);
	mutex_unlock(&sc->mutex);
2657

2658 2659
	return tsf;
}
2660

2661 2662
static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
{
2663 2664
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2665

2666 2667 2668
	mutex_lock(&sc->mutex);
	ath9k_hw_settsf64(sc->sc_ah, tsf);
	mutex_unlock(&sc->mutex);
2669 2670
}

2671 2672
static void ath9k_reset_tsf(struct ieee80211_hw *hw)
{
2673 2674
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2675

2676 2677 2678
	mutex_lock(&sc->mutex);
	ath9k_hw_reset_tsf(sc->sc_ah);
	mutex_unlock(&sc->mutex);
2679
}
2680

2681
static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2682 2683 2684
			      enum ieee80211_ampdu_mlme_action action,
			      struct ieee80211_sta *sta,
			      u16 tid, u16 *ssn)
2685
{
2686 2687
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2688
	int ret = 0;
2689

2690 2691
	switch (action) {
	case IEEE80211_AMPDU_RX_START:
2692 2693
		if (!(sc->sc_flags & SC_OP_RXAGGR))
			ret = -ENOTSUPP;
2694 2695 2696 2697
		break;
	case IEEE80211_AMPDU_RX_STOP:
		break;
	case IEEE80211_AMPDU_TX_START:
S
Sujith 已提交
2698 2699
		ath_tx_aggr_start(sc, sta, tid, ssn);
		ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2700 2701
		break;
	case IEEE80211_AMPDU_TX_STOP:
S
Sujith 已提交
2702
		ath_tx_aggr_stop(sc, sta, tid);
2703
		ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2704
		break;
2705
	case IEEE80211_AMPDU_TX_OPERATIONAL:
2706 2707
		ath_tx_aggr_resume(sc, sta, tid);
		break;
2708
	default:
S
Sujith 已提交
2709
		DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2710 2711 2712
	}

	return ret;
2713 2714
}

2715 2716
static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
{
2717 2718
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2719

2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732
	if (ath9k_wiphy_scanning(sc)) {
		printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
		       "same time\n");
		/*
		 * Do not allow the concurrent scanning state for now. This
		 * could be improved with scanning control moved into ath9k.
		 */
		return;
	}

	aphy->state = ATH_WIPHY_SCAN;
	ath9k_wiphy_pause_all_forced(sc, aphy);

2733
	spin_lock_bh(&sc->ani_lock);
2734
	sc->sc_flags |= SC_OP_SCANNING;
2735
	spin_unlock_bh(&sc->ani_lock);
2736 2737 2738 2739
}

static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
{
2740 2741
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
2742

2743
	spin_lock_bh(&sc->ani_lock);
2744
	aphy->state = ATH_WIPHY_ACTIVE;
2745
	sc->sc_flags &= ~SC_OP_SCANNING;
2746
	sc->sc_flags |= SC_OP_FULL_RESET;
2747
	spin_unlock_bh(&sc->ani_lock);
2748 2749
}

2750
struct ieee80211_ops ath9k_ops = {
2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762
	.tx 		    = ath9k_tx,
	.start 		    = ath9k_start,
	.stop 		    = ath9k_stop,
	.add_interface 	    = ath9k_add_interface,
	.remove_interface   = ath9k_remove_interface,
	.config 	    = ath9k_config,
	.configure_filter   = ath9k_configure_filter,
	.sta_notify         = ath9k_sta_notify,
	.conf_tx 	    = ath9k_conf_tx,
	.bss_info_changed   = ath9k_bss_info_changed,
	.set_key            = ath9k_set_key,
	.get_tsf 	    = ath9k_get_tsf,
2763
	.set_tsf 	    = ath9k_set_tsf,
2764
	.reset_tsf 	    = ath9k_reset_tsf,
2765
	.ampdu_action       = ath9k_ampdu_action,
2766 2767
	.sw_scan_start      = ath9k_sw_scan_start,
	.sw_scan_complete   = ath9k_sw_scan_complete,
2768
	.rfkill_poll        = ath9k_rfkill_poll_state,
2769 2770
};

2771 2772 2773 2774 2775 2776 2777 2778 2779
static struct {
	u32 version;
	const char * name;
} ath_mac_bb_names[] = {
	{ AR_SREV_VERSION_5416_PCI,	"5416" },
	{ AR_SREV_VERSION_5416_PCIE,	"5418" },
	{ AR_SREV_VERSION_9100,		"9100" },
	{ AR_SREV_VERSION_9160,		"9160" },
	{ AR_SREV_VERSION_9280,		"9280" },
2780 2781
	{ AR_SREV_VERSION_9285,		"9285" },
	{ AR_SREV_VERSION_9287,         "9287" }
2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797
};

static struct {
	u16 version;
	const char * name;
} ath_rf_names[] = {
	{ 0,				"5133" },
	{ AR_RAD5133_SREV_MAJOR,	"5133" },
	{ AR_RAD5122_SREV_MAJOR,	"5122" },
	{ AR_RAD2133_SREV_MAJOR,	"2133" },
	{ AR_RAD2122_SREV_MAJOR,	"2122" }
};

/*
 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
 */
2798
const char *
2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814
ath_mac_bb_name(u32 mac_bb_version)
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
		if (ath_mac_bb_names[i].version == mac_bb_version) {
			return ath_mac_bb_names[i].name;
		}
	}

	return "????";
}

/*
 * Return the RF name. "????" is returned if the RF is unknown.
 */
2815
const char *
2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828
ath_rf_name(u16 rf_version)
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
		if (ath_rf_names[i].version == rf_version) {
			return ath_rf_names[i].name;
		}
	}

	return "????";
}

2829
static int __init ath9k_init(void)
2830
{
2831 2832 2833 2834 2835 2836
	int error;

	/* Register rate control algorithm */
	error = ath_rate_control_register();
	if (error != 0) {
		printk(KERN_ERR
2837 2838
			"ath9k: Unable to register rate control "
			"algorithm: %d\n",
2839
			error);
2840
		goto err_out;
2841 2842
	}

2843 2844 2845 2846 2847 2848 2849 2850
	error = ath9k_debug_create_root();
	if (error) {
		printk(KERN_ERR
			"ath9k: Unable to create debugfs root: %d\n",
			error);
		goto err_rate_unregister;
	}

2851 2852
	error = ath_pci_init();
	if (error < 0) {
2853
		printk(KERN_ERR
2854
			"ath9k: No PCI devices found, driver not installed.\n");
2855
		error = -ENODEV;
2856
		goto err_remove_root;
2857 2858
	}

2859 2860 2861 2862 2863 2864
	error = ath_ahb_init();
	if (error < 0) {
		error = -ENODEV;
		goto err_pci_exit;
	}

2865
	return 0;
2866

2867 2868 2869
 err_pci_exit:
	ath_pci_exit();

2870 2871
 err_remove_root:
	ath9k_debug_remove_root();
2872 2873 2874 2875
 err_rate_unregister:
	ath_rate_control_unregister();
 err_out:
	return error;
2876
}
2877
module_init(ath9k_init);
2878

2879
static void __exit ath9k_exit(void)
2880
{
2881
	ath_ahb_exit();
2882
	ath_pci_exit();
2883
	ath9k_debug_remove_root();
2884
	ath_rate_control_unregister();
S
Sujith 已提交
2885
	printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2886
}
2887
module_exit(ath9k_exit);
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