dma.c 59.2 KB
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/*
 * linux/arch/arm/plat-omap/dma.c
 *
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 * Copyright (C) 2003 - 2008 Nokia Corporation
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 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
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 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
 * Graphics DMA and LCD DMA graphics tranformations
 * by Imre Deak <imre.deak@nokia.com>
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 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
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 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
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 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
 *
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 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
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 * Support functions for the OMAP internal DMA channels.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#include <mach/hardware.h>
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#include <plat/dma.h>
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#include <plat/tc.h>
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#undef DEBUG

#ifndef CONFIG_ARCH_OMAP1
enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
	DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
};

enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
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#endif
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#define OMAP_DMA_ACTIVE			0x01
#define OMAP_DMA_CCR_EN			(1 << 7)
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#define OMAP2_DMA_CSR_CLEAR_MASK	0xffe
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#define OMAP_FUNC_MUX_ARM_BASE		(0xfffe1000 + 0xec)
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static int enable_1510_mode;
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struct omap_dma_lch {
	int next_lch;
	int dev_id;
	u16 saved_csr;
	u16 enabled_irqs;
	const char *dev_name;
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	void (*callback)(int lch, u16 ch_status, void *data);
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	void *data;
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#ifndef CONFIG_ARCH_OMAP1
	/* required for Dynamic chaining */
	int prev_linked_ch;
	int next_linked_ch;
	int state;
	int chain_id;

	int status;
#endif
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	long flags;
};

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struct dma_link_info {
	int *linked_dmach_q;
	int no_of_lchs_linked;

	int q_count;
	int q_tail;
	int q_head;

	int chain_state;
	int chain_mode;

};

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static struct dma_link_info *dma_linked_lch;

#ifndef CONFIG_ARCH_OMAP1
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/* Chain handling macros */
#define OMAP_DMA_CHAIN_QINIT(chain_id)					\
	do {								\
		dma_linked_lch[chain_id].q_head =			\
		dma_linked_lch[chain_id].q_tail =			\
		dma_linked_lch[chain_id].q_count = 0;			\
	} while (0)
#define OMAP_DMA_CHAIN_QFULL(chain_id)					\
		(dma_linked_lch[chain_id].no_of_lchs_linked ==		\
		dma_linked_lch[chain_id].q_count)
#define OMAP_DMA_CHAIN_QLAST(chain_id)					\
	do {								\
		((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==	\
		dma_linked_lch[chain_id].q_count)			\
	} while (0)
#define OMAP_DMA_CHAIN_QEMPTY(chain_id)					\
		(0 == dma_linked_lch[chain_id].q_count)
#define __OMAP_DMA_CHAIN_INCQ(end)					\
	((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
#define OMAP_DMA_CHAIN_INCQHEAD(chain_id)				\
	do {								\
		__OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head);	\
		dma_linked_lch[chain_id].q_count--;			\
	} while (0)

#define OMAP_DMA_CHAIN_INCQTAIL(chain_id)				\
	do {								\
		__OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail);	\
		dma_linked_lch[chain_id].q_count++; \
	} while (0)
#endif
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static int dma_lch_count;
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static int dma_chan_count;
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static int omap_dma_reserve_channels;
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static spinlock_t dma_chan_lock;
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static struct omap_dma_lch *dma_chan;
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static void __iomem *omap_dma_base;
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static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
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	INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
	INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
	INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
	INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
	INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
};

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static inline void disable_lnk(int lch);
static void omap_disable_channel_irq(int lch);
static inline void omap_enable_channel_irq(int lch);

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#define REVISIT_24XX()		printk(KERN_ERR "FIXME: no %s on 24xx\n", \
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						__func__);
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#define dma_read(reg)							\
({									\
	u32 __val;							\
	if (cpu_class_is_omap1())					\
		__val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);	\
	else								\
		__val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);	\
	__val;								\
})

#define dma_write(val, reg)						\
({									\
	if (cpu_class_is_omap1())					\
		__raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
	else								\
		__raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);	\
})

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#ifdef CONFIG_ARCH_OMAP15XX
/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
int omap_dma_in_1510_mode(void)
{
	return enable_1510_mode;
}
#else
#define omap_dma_in_1510_mode()		0
#endif

#ifdef CONFIG_ARCH_OMAP1
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static inline int get_gdma_dev(int req)
{
	u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
	int shift = ((req - 1) % 5) * 6;

	return ((omap_readl(reg) >> shift) & 0x3f) + 1;
}

static inline void set_gdma_dev(int req, int dev)
{
	u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
	int shift = ((req - 1) % 5) * 6;
	u32 l;

	l = omap_readl(reg);
	l &= ~(0x3f << shift);
	l |= (dev - 1) << shift;
	omap_writel(l, reg);
}
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#else
#define set_gdma_dev(req, dev)	do {} while (0)
#endif
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/* Omap1 only */
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static void clear_lch_regs(int lch)
{
	int i;
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	void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
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	for (i = 0; i < 0x2c; i += 2)
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		__raw_writew(0, lch_base + i);
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}

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void omap_set_dma_priority(int lch, int dst_port, int priority)
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{
	unsigned long reg;
	u32 l;

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	if (cpu_class_is_omap1()) {
		switch (dst_port) {
		case OMAP_DMA_PORT_OCP_T1:	/* FFFECC00 */
			reg = OMAP_TC_OCPT1_PRIOR;
			break;
		case OMAP_DMA_PORT_OCP_T2:	/* FFFECCD0 */
			reg = OMAP_TC_OCPT2_PRIOR;
			break;
		case OMAP_DMA_PORT_EMIFF:	/* FFFECC08 */
			reg = OMAP_TC_EMIFF_PRIOR;
			break;
		case OMAP_DMA_PORT_EMIFS:	/* FFFECC04 */
			reg = OMAP_TC_EMIFS_PRIOR;
			break;
		default:
			BUG();
			return;
		}
		l = omap_readl(reg);
		l &= ~(0xf << 8);
		l |= (priority & 0xf) << 8;
		omap_writel(l, reg);
	}

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	if (cpu_class_is_omap2()) {
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		u32 ccr;

		ccr = dma_read(CCR(lch));
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		if (priority)
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			ccr |= (1 << 6);
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		else
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			ccr &= ~(1 << 6);
		dma_write(ccr, CCR(lch));
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	}
}
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EXPORT_SYMBOL(omap_set_dma_priority);
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void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
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				  int frame_count, int sync_mode,
				  int dma_trigger, int src_or_dst_synch)
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{
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	u32 l;

	l = dma_read(CSDP(lch));
	l &= ~0x03;
	l |= data_type;
	dma_write(l, CSDP(lch));
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	if (cpu_class_is_omap1()) {
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		u16 ccr;

		ccr = dma_read(CCR(lch));
		ccr &= ~(1 << 5);
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		if (sync_mode == OMAP_DMA_SYNC_FRAME)
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			ccr |= 1 << 5;
		dma_write(ccr, CCR(lch));
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		ccr = dma_read(CCR2(lch));
		ccr &= ~(1 << 2);
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		if (sync_mode == OMAP_DMA_SYNC_BLOCK)
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			ccr |= 1 << 2;
		dma_write(ccr, CCR2(lch));
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	}

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	if (cpu_class_is_omap2() && dma_trigger) {
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		u32 val;
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		val = dma_read(CCR(lch));
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		/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
		val &= ~((3 << 19) | 0x1f);
		val |= (dma_trigger & ~0x1f) << 14;
		val |= dma_trigger & 0x1f;
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		if (sync_mode & OMAP_DMA_SYNC_FRAME)
			val |= 1 << 5;
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		else
			val &= ~(1 << 5);
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		if (sync_mode & OMAP_DMA_SYNC_BLOCK)
			val |= 1 << 18;
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		else
			val &= ~(1 << 18);
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		if (src_or_dst_synch)
			val |= 1 << 24;		/* source synch */
		else
			val &= ~(1 << 24);	/* dest synch */

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		dma_write(val, CCR(lch));
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	}

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	dma_write(elem_count, CEN(lch));
	dma_write(frame_count, CFN(lch));
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}
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EXPORT_SYMBOL(omap_set_dma_transfer_params);
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void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
{
	BUG_ON(omap_dma_in_1510_mode());

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	if (cpu_class_is_omap1()) {
		u16 w;
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		w = dma_read(CCR2(lch));
		w &= ~0x03;

		switch (mode) {
		case OMAP_DMA_CONSTANT_FILL:
			w |= 0x01;
			break;
		case OMAP_DMA_TRANSPARENT_COPY:
			w |= 0x02;
			break;
		case OMAP_DMA_COLOR_DIS:
			break;
		default:
			BUG();
		}
		dma_write(w, CCR2(lch));

		w = dma_read(LCH_CTRL(lch));
		w &= ~0x0f;
		/* Default is channel type 2D */
		if (mode) {
			dma_write((u16)color, COLOR_L(lch));
			dma_write((u16)(color >> 16), COLOR_U(lch));
			w |= 1;		/* Channel type G */
		}
		dma_write(w, LCH_CTRL(lch));
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	}
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	if (cpu_class_is_omap2()) {
		u32 val;

		val = dma_read(CCR(lch));
		val &= ~((1 << 17) | (1 << 16));

		switch (mode) {
		case OMAP_DMA_CONSTANT_FILL:
			val |= 1 << 16;
			break;
		case OMAP_DMA_TRANSPARENT_COPY:
			val |= 1 << 17;
			break;
		case OMAP_DMA_COLOR_DIS:
			break;
		default:
			BUG();
		}
		dma_write(val, CCR(lch));

		color &= 0xffffff;
		dma_write(color, COLOR(lch));
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	}
}
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EXPORT_SYMBOL(omap_set_dma_color_mode);
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void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
{
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	if (cpu_class_is_omap2()) {
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		u32 csdp;

		csdp = dma_read(CSDP(lch));
		csdp &= ~(0x3 << 16);
		csdp |= (mode << 16);
		dma_write(csdp, CSDP(lch));
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	}
}
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EXPORT_SYMBOL(omap_set_dma_write_mode);
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void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
{
	if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
		u32 l;

		l = dma_read(LCH_CTRL(lch));
		l &= ~0x7;
		l |= mode;
		dma_write(l, LCH_CTRL(lch));
	}
}
EXPORT_SYMBOL(omap_set_dma_channel_mode);

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/* Note that src_port is only for omap1 */
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void omap_set_dma_src_params(int lch, int src_port, int src_amode,
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			     unsigned long src_start,
			     int src_ei, int src_fi)
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{
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	u32 l;

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	if (cpu_class_is_omap1()) {
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		u16 w;
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		w = dma_read(CSDP(lch));
		w &= ~(0x1f << 2);
		w |= src_port << 2;
		dma_write(w, CSDP(lch));
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	}
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	l = dma_read(CCR(lch));
	l &= ~(0x03 << 12);
	l |= src_amode << 12;
	dma_write(l, CCR(lch));
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	if (cpu_class_is_omap1()) {
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		dma_write(src_start >> 16, CSSA_U(lch));
		dma_write((u16)src_start, CSSA_L(lch));
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	}
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	if (cpu_class_is_omap2())
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		dma_write(src_start, CSSA(lch));
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	dma_write(src_ei, CSEI(lch));
	dma_write(src_fi, CSFI(lch));
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}
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EXPORT_SYMBOL(omap_set_dma_src_params);
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void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
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{
	omap_set_dma_transfer_params(lch, params->data_type,
				     params->elem_count, params->frame_count,
				     params->sync_mode, params->trigger,
				     params->src_or_dst_synch);
	omap_set_dma_src_params(lch, params->src_port,
				params->src_amode, params->src_start,
				params->src_ei, params->src_fi);

	omap_set_dma_dest_params(lch, params->dst_port,
				 params->dst_amode, params->dst_start,
				 params->dst_ei, params->dst_fi);
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	if (params->read_prio || params->write_prio)
		omap_dma_set_prio_lch(lch, params->read_prio,
				      params->write_prio);
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}
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EXPORT_SYMBOL(omap_set_dma_params);
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void omap_set_dma_src_index(int lch, int eidx, int fidx)
{
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	if (cpu_class_is_omap2())
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		return;
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	dma_write(eidx, CSEI(lch));
	dma_write(fidx, CSFI(lch));
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}
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EXPORT_SYMBOL(omap_set_dma_src_index);
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void omap_set_dma_src_data_pack(int lch, int enable)
{
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	u32 l;

	l = dma_read(CSDP(lch));
	l &= ~(1 << 6);
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	if (enable)
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		l |= (1 << 6);
	dma_write(l, CSDP(lch));
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}
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EXPORT_SYMBOL(omap_set_dma_src_data_pack);
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void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
{
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	unsigned int burst = 0;
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	u32 l;

	l = dma_read(CSDP(lch));
	l &= ~(0x03 << 7);
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	switch (burst_mode) {
	case OMAP_DMA_DATA_BURST_DIS:
		break;
	case OMAP_DMA_DATA_BURST_4:
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		if (cpu_class_is_omap2())
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			burst = 0x1;
		else
			burst = 0x2;
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		break;
	case OMAP_DMA_DATA_BURST_8:
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		if (cpu_class_is_omap2()) {
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			burst = 0x2;
			break;
		}
		/* not supported by current hardware on OMAP1
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		 * w |= (0x03 << 7);
		 * fall through
		 */
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	case OMAP_DMA_DATA_BURST_16:
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		if (cpu_class_is_omap2()) {
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			burst = 0x3;
			break;
		}
		/* OMAP1 don't support burst 16
		 * fall through
		 */
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	default:
		BUG();
	}
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	l |= (burst << 7);
	dma_write(l, CSDP(lch));
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}
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EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
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/* Note that dest_port is only for OMAP1 */
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void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
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			      unsigned long dest_start,
			      int dst_ei, int dst_fi)
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{
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	u32 l;

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	if (cpu_class_is_omap1()) {
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		l = dma_read(CSDP(lch));
		l &= ~(0x1f << 9);
		l |= dest_port << 9;
		dma_write(l, CSDP(lch));
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	}
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	l = dma_read(CCR(lch));
	l &= ~(0x03 << 14);
	l |= dest_amode << 14;
	dma_write(l, CCR(lch));
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	if (cpu_class_is_omap1()) {
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		dma_write(dest_start >> 16, CDSA_U(lch));
		dma_write(dest_start, CDSA_L(lch));
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	}
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	if (cpu_class_is_omap2())
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		dma_write(dest_start, CDSA(lch));
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	dma_write(dst_ei, CDEI(lch));
	dma_write(dst_fi, CDFI(lch));
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}
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EXPORT_SYMBOL(omap_set_dma_dest_params);
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void omap_set_dma_dest_index(int lch, int eidx, int fidx)
{
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	if (cpu_class_is_omap2())
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		return;
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	dma_write(eidx, CDEI(lch));
	dma_write(fidx, CDFI(lch));
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}
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EXPORT_SYMBOL(omap_set_dma_dest_index);
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void omap_set_dma_dest_data_pack(int lch, int enable)
{
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	u32 l;

	l = dma_read(CSDP(lch));
	l &= ~(1 << 13);
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	if (enable)
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		l |= 1 << 13;
	dma_write(l, CSDP(lch));
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}
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EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
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void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
{
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	unsigned int burst = 0;
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	u32 l;

	l = dma_read(CSDP(lch));
	l &= ~(0x03 << 14);
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	switch (burst_mode) {
	case OMAP_DMA_DATA_BURST_DIS:
		break;
	case OMAP_DMA_DATA_BURST_4:
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		if (cpu_class_is_omap2())
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			burst = 0x1;
		else
			burst = 0x2;
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		break;
	case OMAP_DMA_DATA_BURST_8:
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		if (cpu_class_is_omap2())
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			burst = 0x2;
		else
			burst = 0x3;
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		break;
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	case OMAP_DMA_DATA_BURST_16:
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		if (cpu_class_is_omap2()) {
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			burst = 0x3;
			break;
		}
		/* OMAP1 don't support burst 16
		 * fall through
		 */
604 605 606 607 608
	default:
		printk(KERN_ERR "Invalid DMA burst mode\n");
		BUG();
		return;
	}
609 610
	l |= (burst << 14);
	dma_write(l, CSDP(lch));
611
}
T
Tony Lindgren 已提交
612
EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
613

614
static inline void omap_enable_channel_irq(int lch)
615
{
616
	u32 status;
617

618 619
	/* Clear CSR */
	if (cpu_class_is_omap1())
620
		status = dma_read(CSR(lch));
621
	else if (cpu_class_is_omap2())
622
		dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
623

624
	/* Enable some nice interrupts. */
625
	dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
626 627
}

628
static void omap_disable_channel_irq(int lch)
629
{
630
	if (cpu_class_is_omap2())
631
		dma_write(0, CICR(lch));
632 633 634 635 636 637
}

void omap_enable_dma_irq(int lch, u16 bits)
{
	dma_chan[lch].enabled_irqs |= bits;
}
T
Tony Lindgren 已提交
638
EXPORT_SYMBOL(omap_enable_dma_irq);
639

640 641 642 643
void omap_disable_dma_irq(int lch, u16 bits)
{
	dma_chan[lch].enabled_irqs &= ~bits;
}
T
Tony Lindgren 已提交
644
EXPORT_SYMBOL(omap_disable_dma_irq);
645 646 647

static inline void enable_lnk(int lch)
{
648 649 650 651
	u32 l;

	l = dma_read(CLNK_CTRL(lch));

652
	if (cpu_class_is_omap1())
653
		l &= ~(1 << 14);
654

655
	/* Set the ENABLE_LNK bits */
656
	if (dma_chan[lch].next_lch != -1)
657
		l = dma_chan[lch].next_lch | (1 << 15);
658 659

#ifndef CONFIG_ARCH_OMAP1
T
Tony Lindgren 已提交
660 661 662
	if (cpu_class_is_omap2())
		if (dma_chan[lch].next_linked_ch != -1)
			l = dma_chan[lch].next_linked_ch | (1 << 15);
663
#endif
664 665

	dma_write(l, CLNK_CTRL(lch));
666 667 668 669
}

static inline void disable_lnk(int lch)
{
670 671 672 673
	u32 l;

	l = dma_read(CLNK_CTRL(lch));

674
	/* Disable interrupts */
675
	if (cpu_class_is_omap1()) {
676
		dma_write(0, CICR(lch));
677
		/* Set the STOP_LNK bit */
678
		l |= 1 << 14;
679
	}
680

681
	if (cpu_class_is_omap2()) {
682 683
		omap_disable_channel_irq(lch);
		/* Clear the ENABLE_LNK bit */
684
		l &= ~(1 << 15);
685
	}
686

687
	dma_write(l, CLNK_CTRL(lch));
688 689 690
	dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
}

691
static inline void omap2_enable_irq_lch(int lch)
692
{
693 694
	u32 val;

695
	if (!cpu_class_is_omap2())
696 697
		return;

698
	val = dma_read(IRQENABLE_L0);
699
	val |= 1 << lch;
700
	dma_write(val, IRQENABLE_L0);
701 702 703
}

int omap_request_dma(int dev_id, const char *dev_name,
T
Tony Lindgren 已提交
704
		     void (*callback)(int lch, u16 ch_status, void *data),
705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727
		     void *data, int *dma_ch_out)
{
	int ch, free_ch = -1;
	unsigned long flags;
	struct omap_dma_lch *chan;

	spin_lock_irqsave(&dma_chan_lock, flags);
	for (ch = 0; ch < dma_chan_count; ch++) {
		if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
			free_ch = ch;
			if (dev_id == 0)
				break;
		}
	}
	if (free_ch == -1) {
		spin_unlock_irqrestore(&dma_chan_lock, flags);
		return -EBUSY;
	}
	chan = dma_chan + free_ch;
	chan->dev_id = dev_id;

	if (cpu_class_is_omap1())
		clear_lch_regs(free_ch);
728

729
	if (cpu_class_is_omap2())
730 731 732 733 734 735 736
		omap_clear_dma(free_ch);

	spin_unlock_irqrestore(&dma_chan_lock, flags);

	chan->dev_name = dev_name;
	chan->callback = callback;
	chan->data = data;
737
	chan->flags = 0;
T
Tony Lindgren 已提交
738

739
#ifndef CONFIG_ARCH_OMAP1
T
Tony Lindgren 已提交
740 741 742 743
	if (cpu_class_is_omap2()) {
		chan->chain_id = -1;
		chan->next_linked_ch = -1;
	}
744
#endif
T
Tony Lindgren 已提交
745

746
	chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
747

748 749
	if (cpu_class_is_omap1())
		chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
750
	else if (cpu_class_is_omap2())
751 752
		chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
			OMAP2_DMA_TRANS_ERR_IRQ;
753 754 755 756 757 758 759

	if (cpu_is_omap16xx()) {
		/* If the sync device is set, configure it dynamically. */
		if (dev_id != 0) {
			set_gdma_dev(free_ch + 1, dev_id);
			dev_id = free_ch + 1;
		}
T
Tony Lindgren 已提交
760 761 762 763
		/*
		 * Disable the 1510 compatibility mode and set the sync device
		 * id.
		 */
764
		dma_write(dev_id | (1 << 10), CCR(free_ch));
765
	} else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
766
		dma_write(dev_id, CCR(free_ch));
767 768
	}

769
	if (cpu_class_is_omap2()) {
770 771 772
		omap2_enable_irq_lch(free_ch);
		omap_enable_channel_irq(free_ch);
		/* Clear the CSR register and IRQ status register */
773 774
		dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
		dma_write(1 << free_ch, IRQSTATUS_L0);
775 776 777 778 779 780
	}

	*dma_ch_out = free_ch;

	return 0;
}
T
Tony Lindgren 已提交
781
EXPORT_SYMBOL(omap_request_dma);
782 783 784 785 786 787

void omap_free_dma(int lch)
{
	unsigned long flags;

	if (dma_chan[lch].dev_id == -1) {
T
Tony Lindgren 已提交
788
		pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
789 790 791
		       lch);
		return;
	}
T
Tony Lindgren 已提交
792

793 794
	if (cpu_class_is_omap1()) {
		/* Disable all DMA interrupts for the channel. */
795
		dma_write(0, CICR(lch));
796
		/* Make sure the DMA transfer is stopped. */
797
		dma_write(0, CCR(lch));
798 799
	}

800
	if (cpu_class_is_omap2()) {
801 802
		u32 val;
		/* Disable interrupts */
803
		val = dma_read(IRQENABLE_L0);
804
		val &= ~(1 << lch);
805
		dma_write(val, IRQENABLE_L0);
806 807

		/* Clear the CSR register and IRQ status register */
808 809
		dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
		dma_write(1 << lch, IRQSTATUS_L0);
810 811

		/* Disable all DMA interrupts for the channel. */
812
		dma_write(0, CICR(lch));
813 814

		/* Make sure the DMA transfer is stopped. */
815
		dma_write(0, CCR(lch));
816 817
		omap_clear_dma(lch);
	}
818 819 820 821 822 823

	spin_lock_irqsave(&dma_chan_lock, flags);
	dma_chan[lch].dev_id = -1;
	dma_chan[lch].next_lch = -1;
	dma_chan[lch].callback = NULL;
	spin_unlock_irqrestore(&dma_chan_lock, flags);
824
}
T
Tony Lindgren 已提交
825
EXPORT_SYMBOL(omap_free_dma);
826

827 828 829 830 831
/**
 * @brief omap_dma_set_global_params : Set global priority settings for dma
 *
 * @param arb_rate
 * @param max_fifo_depth
832 833 834 835
 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 * 						   DMA_THREAD_RESERVE_ONET
 * 						   DMA_THREAD_RESERVE_TWOT
 * 						   DMA_THREAD_RESERVE_THREET
836 837 838 839 840 841 842
 */
void
omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
{
	u32 reg;

	if (!cpu_class_is_omap2()) {
843
		printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
844 845 846
		return;
	}

847 848
	if (max_fifo_depth == 0)
		max_fifo_depth = 1;
849 850 851
	if (arb_rate == 0)
		arb_rate = 1;

852 853 854
	reg = 0xff & max_fifo_depth;
	reg |= (0x3 & tparams) << 12;
	reg |= (arb_rate & 0xff) << 16;
855

856
	dma_write(reg, GCR);
857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872
}
EXPORT_SYMBOL(omap_dma_set_global_params);

/**
 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 *
 * @param lch
 * @param read_prio - Read priority
 * @param write_prio - Write priority
 * Both of the above can be set with one of the following values :
 * 	DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 */
int
omap_dma_set_prio_lch(int lch, unsigned char read_prio,
		      unsigned char write_prio)
{
873
	u32 l;
874

875
	if (unlikely((lch < 0 || lch >= dma_lch_count))) {
876 877 878
		printk(KERN_ERR "Invalid channel id\n");
		return -EINVAL;
	}
879 880
	l = dma_read(CCR(lch));
	l &= ~((1 << 6) | (1 << 26));
881
	if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
882
		l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
883
	else
884 885 886
		l |= ((read_prio & 0x1) << 6);

	dma_write(l, CCR(lch));
887 888 889 890 891

	return 0;
}
EXPORT_SYMBOL(omap_dma_set_prio_lch);

892 893 894 895 896 897 898 899 900 901 902
/*
 * Clears any DMA state so the DMA engine is ready to restart with new buffers
 * through omap_start_dma(). Any buffers in flight are discarded.
 */
void omap_clear_dma(int lch)
{
	unsigned long flags;

	local_irq_save(flags);

	if (cpu_class_is_omap1()) {
903 904 905 906 907
		u32 l;

		l = dma_read(CCR(lch));
		l &= ~OMAP_DMA_CCR_EN;
		dma_write(l, CCR(lch));
908 909

		/* Clear pending interrupts */
910
		l = dma_read(CSR(lch));
911 912
	}

913
	if (cpu_class_is_omap2()) {
914
		int i;
915
		void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
916
		for (i = 0; i < 0x44; i += 4)
917
			__raw_writel(0, lch_base + i);
918 919 920 921
	}

	local_irq_restore(flags);
}
T
Tony Lindgren 已提交
922
EXPORT_SYMBOL(omap_clear_dma);
923 924 925

void omap_start_dma(int lch)
{
926 927
	u32 l;

928 929
	if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
		int next_lch, cur_lch;
930
		char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
931 932 933 934 935 936 937 938 939 940

		dma_chan_link_map[lch] = 1;
		/* Set the link register of the first channel */
		enable_lnk(lch);

		memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
		cur_lch = dma_chan[lch].next_lch;
		do {
			next_lch = dma_chan[cur_lch].next_lch;

941
			/* The loop case: we've been here already */
942 943 944 945 946 947
			if (dma_chan_link_map[cur_lch])
				break;
			/* Mark the current channel */
			dma_chan_link_map[cur_lch] = 1;

			enable_lnk(cur_lch);
948
			omap_enable_channel_irq(cur_lch);
949 950 951

			cur_lch = next_lch;
		} while (next_lch != -1);
V
Vikram Pandita 已提交
952 953 954
	} else if (cpu_is_omap242x() ||
		(cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {

955
		/* Errata: Need to write lch even if not using chaining */
956
		dma_write(lch, CLNK_CTRL(lch));
957 958
	}

959 960
	omap_enable_channel_irq(lch);

961 962
	l = dma_read(CCR(lch));

T
Tony Lindgren 已提交
963 964 965 966
	/*
	 * Errata: On ES2.0 BUFFERING disable must be set.
	 * This will always fail on ES1.0
	 */
967 968
	if (cpu_is_omap24xx())
		l |= OMAP_DMA_CCR_EN;
969

970 971
	l |= OMAP_DMA_CCR_EN;
	dma_write(l, CCR(lch));
972 973 974

	dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
}
T
Tony Lindgren 已提交
975
EXPORT_SYMBOL(omap_start_dma);
976 977 978

void omap_stop_dma(int lch)
{
979 980
	u32 l;

981 982 983 984 985 986 987 988
	/* Disable all interrupts on the channel */
	if (cpu_class_is_omap1())
		dma_write(0, CICR(lch));

	l = dma_read(CCR(lch));
	l &= ~OMAP_DMA_CCR_EN;
	dma_write(l, CCR(lch));

989 990
	if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
		int next_lch, cur_lch = lch;
991
		char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006

		memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
		do {
			/* The loop case: we've been here already */
			if (dma_chan_link_map[cur_lch])
				break;
			/* Mark the current channel */
			dma_chan_link_map[cur_lch] = 1;

			disable_lnk(cur_lch);

			next_lch = dma_chan[cur_lch].next_lch;
			cur_lch = next_lch;
		} while (next_lch != -1);
	}
1007

1008 1009
	dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
}
T
Tony Lindgren 已提交
1010
EXPORT_SYMBOL(omap_stop_dma);
1011

1012 1013 1014 1015 1016
/*
 * Allows changing the DMA callback function or data. This may be needed if
 * the driver shares a single DMA channel for multiple dma triggers.
 */
int omap_set_dma_callback(int lch,
T
Tony Lindgren 已提交
1017
			  void (*callback)(int lch, u16 ch_status, void *data),
1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036
			  void *data)
{
	unsigned long flags;

	if (lch < 0)
		return -ENODEV;

	spin_lock_irqsave(&dma_chan_lock, flags);
	if (dma_chan[lch].dev_id == -1) {
		printk(KERN_ERR "DMA callback for not set for free channel\n");
		spin_unlock_irqrestore(&dma_chan_lock, flags);
		return -EINVAL;
	}
	dma_chan[lch].callback = callback;
	dma_chan[lch].data = data;
	spin_unlock_irqrestore(&dma_chan_lock, flags);

	return 0;
}
T
Tony Lindgren 已提交
1037
EXPORT_SYMBOL(omap_set_dma_callback);
1038

1039 1040 1041 1042 1043 1044 1045 1046 1047
/*
 * Returns current physical source address for the given DMA channel.
 * If the channel is running the caller must disable interrupts prior calling
 * this function and process the returned value before re-enabling interrupt to
 * prevent races with the interrupt handler. Note that in continuous mode there
 * is a chance for CSSA_L register overflow inbetween the two reads resulting
 * in incorrect return value.
 */
dma_addr_t omap_get_dma_src_pos(int lch)
1048
{
T
Tony Lindgren 已提交
1049
	dma_addr_t offset = 0;
1050

1051 1052 1053 1054
	if (cpu_is_omap15xx())
		offset = dma_read(CPC(lch));
	else
		offset = dma_read(CSAC(lch));
1055

1056 1057 1058 1059 1060 1061 1062 1063 1064
	/*
	 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
	 * read before the DMA controller finished disabling the channel.
	 */
	if (!cpu_is_omap15xx() && offset == 0)
		offset = dma_read(CSAC(lch));

	if (cpu_class_is_omap1())
		offset |= (dma_read(CSSA_U(lch)) << 16);
1065

1066
	return offset;
1067
}
T
Tony Lindgren 已提交
1068
EXPORT_SYMBOL(omap_get_dma_src_pos);
1069

1070 1071 1072 1073 1074 1075 1076 1077 1078
/*
 * Returns current physical destination address for the given DMA channel.
 * If the channel is running the caller must disable interrupts prior calling
 * this function and process the returned value before re-enabling interrupt to
 * prevent races with the interrupt handler. Note that in continuous mode there
 * is a chance for CDSA_L register overflow inbetween the two reads resulting
 * in incorrect return value.
 */
dma_addr_t omap_get_dma_dst_pos(int lch)
1079
{
T
Tony Lindgren 已提交
1080
	dma_addr_t offset = 0;
1081

1082 1083 1084 1085
	if (cpu_is_omap15xx())
		offset = dma_read(CPC(lch));
	else
		offset = dma_read(CDAC(lch));
1086

1087 1088 1089 1090 1091 1092 1093 1094 1095
	/*
	 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
	 * read before the DMA controller finished disabling the channel.
	 */
	if (!cpu_is_omap15xx() && offset == 0)
		offset = dma_read(CDAC(lch));

	if (cpu_class_is_omap1())
		offset |= (dma_read(CDSA_U(lch)) << 16);
1096

1097
	return offset;
1098
}
T
Tony Lindgren 已提交
1099
EXPORT_SYMBOL(omap_get_dma_dst_pos);
1100 1101 1102 1103

int omap_get_dma_active_status(int lch)
{
	return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1104
}
1105
EXPORT_SYMBOL(omap_get_dma_active_status);
1106

1107
int omap_dma_running(void)
1108
{
1109
	int lch;
1110

1111 1112 1113 1114
	/* Check if LCD DMA is running */
	if (cpu_is_omap16xx())
		if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
			return 1;
1115

1116
	for (lch = 0; lch < dma_chan_count; lch++)
1117
		if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1118
			return 1;
1119

1120
	return 0;
1121 1122 1123 1124 1125 1126 1127
}

/*
 * lch_queue DMA will start right after lch_head one is finished.
 * For this DMA link to start, you still need to start (see omap_start_dma)
 * the first one. That will fire up the entire queue.
 */
T
Tony Lindgren 已提交
1128
void omap_dma_link_lch(int lch_head, int lch_queue)
1129 1130
{
	if (omap_dma_in_1510_mode()) {
1131 1132 1133 1134 1135
		if (lch_head == lch_queue) {
			dma_write(dma_read(CCR(lch_head)) | (3 << 8),
								CCR(lch_head));
			return;
		}
1136 1137 1138 1139 1140 1141 1142
		printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
		BUG();
		return;
	}

	if ((dma_chan[lch_head].dev_id == -1) ||
	    (dma_chan[lch_queue].dev_id == -1)) {
1143 1144
		printk(KERN_ERR "omap_dma: trying to link "
		       "non requested channels\n");
1145 1146 1147 1148 1149
		dump_stack();
	}

	dma_chan[lch_head].next_lch = lch_queue;
}
T
Tony Lindgren 已提交
1150
EXPORT_SYMBOL(omap_dma_link_lch);
1151 1152 1153 1154

/*
 * Once the DMA queue is stopped, we can destroy it.
 */
T
Tony Lindgren 已提交
1155
void omap_dma_unlink_lch(int lch_head, int lch_queue)
1156 1157
{
	if (omap_dma_in_1510_mode()) {
1158 1159 1160 1161 1162
		if (lch_head == lch_queue) {
			dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
								CCR(lch_head));
			return;
		}
1163 1164 1165 1166 1167 1168 1169
		printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
		BUG();
		return;
	}

	if (dma_chan[lch_head].next_lch != lch_queue ||
	    dma_chan[lch_head].next_lch == -1) {
1170 1171
		printk(KERN_ERR "omap_dma: trying to unlink "
		       "non linked channels\n");
1172 1173 1174 1175 1176
		dump_stack();
	}

	if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
	    (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1177 1178
		printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
		       "before unlinking\n");
1179 1180 1181 1182 1183
		dump_stack();
	}

	dma_chan[lch_head].next_lch = -1;
}
T
Tony Lindgren 已提交
1184 1185 1186
EXPORT_SYMBOL(omap_dma_unlink_lch);

/*----------------------------------------------------------------------------*/
1187

1188 1189 1190 1191
#ifndef CONFIG_ARCH_OMAP1
/* Create chain of DMA channesls */
static void create_dma_lch_chain(int lch_head, int lch_queue)
{
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	u32 l;
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	/* Check if this is the first link in chain */
	if (dma_chan[lch_head].next_linked_ch == -1) {
		dma_chan[lch_head].next_linked_ch = lch_queue;
		dma_chan[lch_head].prev_linked_ch = lch_queue;
		dma_chan[lch_queue].next_linked_ch = lch_head;
		dma_chan[lch_queue].prev_linked_ch = lch_head;
	}

	/* a link exists, link the new channel in circular chain */
	else {
		dma_chan[lch_queue].next_linked_ch =
					dma_chan[lch_head].next_linked_ch;
		dma_chan[lch_queue].prev_linked_ch = lch_head;
		dma_chan[lch_head].next_linked_ch = lch_queue;
		dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
					lch_queue;
	}

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	l = dma_read(CLNK_CTRL(lch_head));
	l &= ~(0x1f);
	l |= lch_queue;
	dma_write(l, CLNK_CTRL(lch_head));
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	l = dma_read(CLNK_CTRL(lch_queue));
	l &= ~(0x1f);
	l |= (dma_chan[lch_queue].next_linked_ch);
	dma_write(l, CLNK_CTRL(lch_queue));
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}

/**
 * @brief omap_request_dma_chain : Request a chain of DMA channels
 *
 * @param dev_id - Device id using the dma channel
 * @param dev_name - Device name
 * @param callback - Call back function
 * @chain_id -
 * @no_of_chans - Number of channels requested
 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
 * 					      OMAP_DMA_DYNAMIC_CHAIN
 * @params - Channel parameters
 *
 * @return - Succes : 0
 * 	     Failure: -EINVAL/-ENOMEM
 */
int omap_request_dma_chain(int dev_id, const char *dev_name,
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			   void (*callback) (int lch, u16 ch_status,
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					     void *data),
			   int *chain_id, int no_of_chans, int chain_mode,
			   struct omap_dma_channel_params params)
{
	int *channels;
	int i, err;

	/* Is the chain mode valid ? */
	if (chain_mode != OMAP_DMA_STATIC_CHAIN
			&& chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
		printk(KERN_ERR "Invalid chain mode requested\n");
		return -EINVAL;
	}

	if (unlikely((no_of_chans < 1
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			|| no_of_chans > dma_lch_count))) {
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		printk(KERN_ERR "Invalid Number of channels requested\n");
		return -EINVAL;
	}

	/* Allocate a queue to maintain the status of the channels
	 * in the chain */
	channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
	if (channels == NULL) {
		printk(KERN_ERR "omap_dma: No memory for channel queue\n");
		return -ENOMEM;
	}

	/* request and reserve DMA channels for the chain */
	for (i = 0; i < no_of_chans; i++) {
		err = omap_request_dma(dev_id, dev_name,
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					callback, NULL, &channels[i]);
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		if (err < 0) {
			int j;
			for (j = 0; j < i; j++)
				omap_free_dma(channels[j]);
			kfree(channels);
			printk(KERN_ERR "omap_dma: Request failed %d\n", err);
			return err;
		}
		dma_chan[channels[i]].prev_linked_ch = -1;
		dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;

		/*
		 * Allowing client drivers to set common parameters now,
		 * so that later only relevant (src_start, dest_start
		 * and element count) can be set
		 */
		omap_set_dma_params(channels[i], &params);
	}

	*chain_id = channels[0];
	dma_linked_lch[*chain_id].linked_dmach_q = channels;
	dma_linked_lch[*chain_id].chain_mode = chain_mode;
	dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
	dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;

	for (i = 0; i < no_of_chans; i++)
		dma_chan[channels[i]].chain_id = *chain_id;

	/* Reset the Queue pointers */
	OMAP_DMA_CHAIN_QINIT(*chain_id);

	/* Set up the chain */
	if (no_of_chans == 1)
		create_dma_lch_chain(channels[0], channels[0]);
	else {
		for (i = 0; i < (no_of_chans - 1); i++)
			create_dma_lch_chain(channels[i], channels[i + 1]);
	}
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	return 0;
}
EXPORT_SYMBOL(omap_request_dma_chain);

/**
 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
 * params after setting it. Dont do this while dma is running!!
 *
 * @param chain_id - Chained logical channel id.
 * @param params
 *
 * @return - Success : 0
 * 	     Failure : -EINVAL
 */
int omap_modify_dma_chain_params(int chain_id,
				struct omap_dma_channel_params params)
{
	int *channels;
	u32 i;

	/* Check for input params */
	if (unlikely((chain_id < 0
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			|| chain_id >= dma_lch_count))) {
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		printk(KERN_ERR "Invalid chain id\n");
		return -EINVAL;
	}

	/* Check if the chain exists */
	if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
		printk(KERN_ERR "Chain doesn't exists\n");
		return -EINVAL;
	}
	channels = dma_linked_lch[chain_id].linked_dmach_q;

	for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
		/*
		 * Allowing client drivers to set common parameters now,
		 * so that later only relevant (src_start, dest_start
		 * and element count) can be set
		 */
		omap_set_dma_params(channels[i], &params);
	}
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	return 0;
}
EXPORT_SYMBOL(omap_modify_dma_chain_params);

/**
 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
 *
 * @param chain_id
 *
 * @return - Success : 0
 * 	     Failure : -EINVAL
 */
int omap_free_dma_chain(int chain_id)
{
	int *channels;
	u32 i;

	/* Check for input params */
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	if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
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		printk(KERN_ERR "Invalid chain id\n");
		return -EINVAL;
	}

	/* Check if the chain exists */
	if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
		printk(KERN_ERR "Chain doesn't exists\n");
		return -EINVAL;
	}

	channels = dma_linked_lch[chain_id].linked_dmach_q;
	for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
		dma_chan[channels[i]].next_linked_ch = -1;
		dma_chan[channels[i]].prev_linked_ch = -1;
		dma_chan[channels[i]].chain_id = -1;
		dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
		omap_free_dma(channels[i]);
	}

	kfree(channels);

	dma_linked_lch[chain_id].linked_dmach_q = NULL;
	dma_linked_lch[chain_id].chain_mode = -1;
	dma_linked_lch[chain_id].chain_state = -1;
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	return (0);
}
EXPORT_SYMBOL(omap_free_dma_chain);

/**
 * @brief omap_dma_chain_status - Check if the chain is in
 * active / inactive state.
 * @param chain_id
 *
 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
 * 	     Failure : -EINVAL
 */
int omap_dma_chain_status(int chain_id)
{
	/* Check for input params */
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	if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
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		printk(KERN_ERR "Invalid chain id\n");
		return -EINVAL;
	}

	/* Check if the chain exists */
	if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
		printk(KERN_ERR "Chain doesn't exists\n");
		return -EINVAL;
	}
	pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
			dma_linked_lch[chain_id].q_count);

	if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
		return OMAP_DMA_CHAIN_INACTIVE;
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	return OMAP_DMA_CHAIN_ACTIVE;
}
EXPORT_SYMBOL(omap_dma_chain_status);

/**
 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
 * set the params and start the transfer.
 *
 * @param chain_id
 * @param src_start - buffer start address
 * @param dest_start - Dest address
 * @param elem_count
 * @param frame_count
 * @param callbk_data - channel callback parameter data.
 *
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 * @return  - Success : 0
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 * 	      Failure: -EINVAL/-EBUSY
 */
int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
			int elem_count, int frame_count, void *callbk_data)
{
	int *channels;
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	u32 l, lch;
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	int start_dma = 0;

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	/*
	 * if buffer size is less than 1 then there is
	 * no use of starting the chain
	 */
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	if (elem_count < 1) {
		printk(KERN_ERR "Invalid buffer size\n");
		return -EINVAL;
	}

	/* Check for input params */
	if (unlikely((chain_id < 0
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			|| chain_id >= dma_lch_count))) {
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		printk(KERN_ERR "Invalid chain id\n");
		return -EINVAL;
	}

	/* Check if the chain exists */
	if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
		printk(KERN_ERR "Chain doesn't exist\n");
		return -EINVAL;
	}

	/* Check if all the channels in chain are in use */
	if (OMAP_DMA_CHAIN_QFULL(chain_id))
		return -EBUSY;

	/* Frame count may be negative in case of indexed transfers */
	channels = dma_linked_lch[chain_id].linked_dmach_q;

	/* Get a free channel */
	lch = channels[dma_linked_lch[chain_id].q_tail];

	/* Store the callback data */
	dma_chan[lch].data = callbk_data;

	/* Increment the q_tail */
	OMAP_DMA_CHAIN_INCQTAIL(chain_id);

	/* Set the params to the free channel */
	if (src_start != 0)
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		dma_write(src_start, CSSA(lch));
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	if (dest_start != 0)
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		dma_write(dest_start, CDSA(lch));
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	/* Write the buffer size */
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	dma_write(elem_count, CEN(lch));
	dma_write(frame_count, CFN(lch));
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	/*
	 * If the chain is dynamically linked,
	 * then we may have to start the chain if its not active
	 */
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	if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {

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		/*
		 * In Dynamic chain, if the chain is not started,
		 * queue the channel
		 */
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		if (dma_linked_lch[chain_id].chain_state ==
						DMA_CHAIN_NOTSTARTED) {
			/* Enable the link in previous channel */
			if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
								DMA_CH_QUEUED)
				enable_lnk(dma_chan[lch].prev_linked_ch);
			dma_chan[lch].state = DMA_CH_QUEUED;
		}

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		/*
		 * Chain is already started, make sure its active,
		 * if not then start the chain
		 */
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		else {
			start_dma = 1;

			if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
							DMA_CH_STARTED) {
				enable_lnk(dma_chan[lch].prev_linked_ch);
				dma_chan[lch].state = DMA_CH_QUEUED;
				start_dma = 0;
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				if (0 == ((1 << 7) & dma_read(
					CCR(dma_chan[lch].prev_linked_ch)))) {
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					disable_lnk(dma_chan[lch].
						    prev_linked_ch);
					pr_debug("\n prev ch is stopped\n");
					start_dma = 1;
				}
			}

			else if (dma_chan[dma_chan[lch].prev_linked_ch].state
							== DMA_CH_QUEUED) {
				enable_lnk(dma_chan[lch].prev_linked_ch);
				dma_chan[lch].state = DMA_CH_QUEUED;
				start_dma = 0;
			}
			omap_enable_channel_irq(lch);

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			l = dma_read(CCR(lch));
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			if ((0 == (l & (1 << 24))))
				l &= ~(1 << 25);
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			else
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				l |= (1 << 25);
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			if (start_dma == 1) {
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				if (0 == (l & (1 << 7))) {
					l |= (1 << 7);
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					dma_chan[lch].state = DMA_CH_STARTED;
					pr_debug("starting %d\n", lch);
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					dma_write(l, CCR(lch));
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				} else
					start_dma = 0;
			} else {
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				if (0 == (l & (1 << 7)))
					dma_write(l, CCR(lch));
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			}
			dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
		}
	}
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	return 0;
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}
EXPORT_SYMBOL(omap_dma_chain_a_transfer);

/**
 * @brief omap_start_dma_chain_transfers - Start the chain
 *
 * @param chain_id
 *
 * @return - Success : 0
 * 	     Failure : -EINVAL/-EBUSY
 */
int omap_start_dma_chain_transfers(int chain_id)
{
	int *channels;
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	u32 l, i;
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	if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
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		printk(KERN_ERR "Invalid chain id\n");
		return -EINVAL;
	}

	channels = dma_linked_lch[chain_id].linked_dmach_q;

	if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
		printk(KERN_ERR "Chain is already started\n");
		return -EBUSY;
	}

	if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
		for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
									i++) {
			enable_lnk(channels[i]);
			omap_enable_channel_irq(channels[i]);
		}
	} else {
		omap_enable_channel_irq(channels[0]);
	}

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	l = dma_read(CCR(channels[0]));
	l |= (1 << 7);
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	dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
	dma_chan[channels[0]].state = DMA_CH_STARTED;

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	if ((0 == (l & (1 << 24))))
		l &= ~(1 << 25);
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	else
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		l |= (1 << 25);
	dma_write(l, CCR(channels[0]));
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	dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
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	return 0;
}
EXPORT_SYMBOL(omap_start_dma_chain_transfers);

/**
 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
 *
 * @param chain_id
 *
 * @return - Success : 0
 * 	     Failure : EINVAL
 */
int omap_stop_dma_chain_transfers(int chain_id)
{
	int *channels;
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	u32 l, i;
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	u32 sys_cf;

	/* Check for input params */
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	if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
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		printk(KERN_ERR "Invalid chain id\n");
		return -EINVAL;
	}

	/* Check if the chain exists */
	if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
		printk(KERN_ERR "Chain doesn't exists\n");
		return -EINVAL;
	}
	channels = dma_linked_lch[chain_id].linked_dmach_q;

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	/*
	 * DMA Errata:
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	 * Special programming model needed to disable DMA before end of block
	 */
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	sys_cf = dma_read(OCP_SYSCONFIG);
	l = sys_cf;
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	/* Middle mode reg set no Standby */
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	l &= ~((1 << 12)|(1 << 13));
	dma_write(l, OCP_SYSCONFIG);
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	for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {

		/* Stop the Channel transmission */
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		l = dma_read(CCR(channels[i]));
		l &= ~(1 << 7);
		dma_write(l, CCR(channels[i]));
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		/* Disable the link in all the channels */
		disable_lnk(channels[i]);
		dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;

	}
	dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;

	/* Reset the Queue pointers */
	OMAP_DMA_CHAIN_QINIT(chain_id);

	/* Errata - put in the old value */
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	dma_write(sys_cf, OCP_SYSCONFIG);
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	return 0;
}
EXPORT_SYMBOL(omap_stop_dma_chain_transfers);

/* Get the index of the ongoing DMA in chain */
/**
 * @brief omap_get_dma_chain_index - Get the element and frame index
 * of the ongoing DMA in chain
 *
 * @param chain_id
 * @param ei - Element index
 * @param fi - Frame index
 *
 * @return - Success : 0
 * 	     Failure : -EINVAL
 */
int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
{
	int lch;
	int *channels;

	/* Check for input params */
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	if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
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		printk(KERN_ERR "Invalid chain id\n");
		return -EINVAL;
	}

	/* Check if the chain exists */
	if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
		printk(KERN_ERR "Chain doesn't exists\n");
		return -EINVAL;
	}
	if ((!ei) || (!fi))
		return -EINVAL;

	channels = dma_linked_lch[chain_id].linked_dmach_q;

	/* Get the current channel */
	lch = channels[dma_linked_lch[chain_id].q_head];

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	*ei = dma_read(CCEN(lch));
	*fi = dma_read(CCFN(lch));
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	return 0;
}
EXPORT_SYMBOL(omap_get_dma_chain_index);

/**
 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
 * ongoing DMA in chain
 *
 * @param chain_id
 *
 * @return - Success : Destination position
 * 	     Failure : -EINVAL
 */
int omap_get_dma_chain_dst_pos(int chain_id)
{
	int lch;
	int *channels;

	/* Check for input params */
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	if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
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		printk(KERN_ERR "Invalid chain id\n");
		return -EINVAL;
	}

	/* Check if the chain exists */
	if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
		printk(KERN_ERR "Chain doesn't exists\n");
		return -EINVAL;
	}

	channels = dma_linked_lch[chain_id].linked_dmach_q;

	/* Get the current channel */
	lch = channels[dma_linked_lch[chain_id].q_head];

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	return dma_read(CDAC(lch));
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}
EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);

/**
 * @brief omap_get_dma_chain_src_pos - Get the source position
 * of the ongoing DMA in chain
 * @param chain_id
 *
 * @return - Success : Destination position
 * 	     Failure : -EINVAL
 */
int omap_get_dma_chain_src_pos(int chain_id)
{
	int lch;
	int *channels;

	/* Check for input params */
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	if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
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		printk(KERN_ERR "Invalid chain id\n");
		return -EINVAL;
	}

	/* Check if the chain exists */
	if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
		printk(KERN_ERR "Chain doesn't exists\n");
		return -EINVAL;
	}

	channels = dma_linked_lch[chain_id].linked_dmach_q;

	/* Get the current channel */
	lch = channels[dma_linked_lch[chain_id].q_head];

1797
	return dma_read(CSAC(lch));
1798 1799
}
EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
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Tony Lindgren 已提交
1800
#endif	/* ifndef CONFIG_ARCH_OMAP1 */
1801

1802 1803 1804 1805 1806 1807
/*----------------------------------------------------------------------------*/

#ifdef CONFIG_ARCH_OMAP1

static int omap1_dma_handle_ch(int ch)
{
1808
	u32 csr;
1809 1810 1811 1812 1813

	if (enable_1510_mode && ch >= 6) {
		csr = dma_chan[ch].saved_csr;
		dma_chan[ch].saved_csr = 0;
	} else
1814
		csr = dma_read(CSR(ch));
1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825
	if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
		dma_chan[ch + 6].saved_csr = csr >> 7;
		csr &= 0x7f;
	}
	if ((csr & 0x3f) == 0)
		return 0;
	if (unlikely(dma_chan[ch].dev_id == -1)) {
		printk(KERN_WARNING "Spurious interrupt from DMA channel "
		       "%d (CSR %04x)\n", ch, csr);
		return 0;
	}
1826
	if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1827 1828 1829 1830 1831 1832 1833 1834 1835
		printk(KERN_WARNING "DMA timeout with device %d\n",
		       dma_chan[ch].dev_id);
	if (unlikely(csr & OMAP_DMA_DROP_IRQ))
		printk(KERN_WARNING "DMA synchronization event drop occurred "
		       "with device %d\n", dma_chan[ch].dev_id);
	if (likely(csr & OMAP_DMA_BLOCK_IRQ))
		dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
	if (likely(dma_chan[ch].callback != NULL))
		dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
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Tony Lindgren 已提交
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1837 1838 1839
	return 1;
}

1840
static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862
{
	int ch = ((int) dev_id) - 1;
	int handled = 0;

	for (;;) {
		int handled_now = 0;

		handled_now += omap1_dma_handle_ch(ch);
		if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
			handled_now += omap1_dma_handle_ch(ch + 6);
		if (!handled_now)
			break;
		handled += handled_now;
	}

	return handled ? IRQ_HANDLED : IRQ_NONE;
}

#else
#define omap1_dma_irq_handler	NULL
#endif

1863 1864
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
			defined(CONFIG_ARCH_OMAP4)
1865 1866 1867

static int omap2_dma_handle_ch(int ch)
{
1868
	u32 status = dma_read(CSR(ch));
1869

1870 1871
	if (!status) {
		if (printk_ratelimit())
T
Tony Lindgren 已提交
1872 1873
			printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
				ch);
1874
		dma_write(1 << ch, IRQSTATUS_L0);
1875
		return 0;
1876 1877 1878 1879 1880
	}
	if (unlikely(dma_chan[ch].dev_id == -1)) {
		if (printk_ratelimit())
			printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
					"channel %d\n", status, ch);
1881
		return 0;
1882
	}
1883 1884 1885 1886
	if (unlikely(status & OMAP_DMA_DROP_IRQ))
		printk(KERN_INFO
		       "DMA synchronization event drop occurred with device "
		       "%d\n", dma_chan[ch].dev_id);
1887
	if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1888 1889
		printk(KERN_INFO "DMA transaction error with device %d\n",
		       dma_chan[ch].dev_id);
1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902
		if (cpu_class_is_omap2()) {
			/* Errata: sDMA Channel is not disabled
			 * after a transaction error. So we explicitely
			 * disable the channel
			 */
			u32 ccr;

			ccr = dma_read(CCR(ch));
			ccr &= ~OMAP_DMA_CCR_EN;
			dma_write(ccr, CCR(ch));
			dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
		}
	}
1903 1904 1905 1906 1907 1908
	if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
		printk(KERN_INFO "DMA secure error with device %d\n",
		       dma_chan[ch].dev_id);
	if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
		printk(KERN_INFO "DMA misaligned error with device %d\n",
		       dma_chan[ch].dev_id);
1909

1910 1911
	dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
	dma_write(1 << ch, IRQSTATUS_L0);
1912

1913 1914 1915 1916
	/* If the ch is not chained then chain_id will be -1 */
	if (dma_chan[ch].chain_id != -1) {
		int chain_id = dma_chan[ch].chain_id;
		dma_chan[ch].state = DMA_CH_NOTSTARTED;
1917
		if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1918 1919 1920 1921 1922 1923 1924 1925 1926
			dma_chan[dma_chan[ch].next_linked_ch].state =
							DMA_CH_STARTED;
		if (dma_linked_lch[chain_id].chain_mode ==
						OMAP_DMA_DYNAMIC_CHAIN)
			disable_lnk(ch);

		if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
			OMAP_DMA_CHAIN_INCQHEAD(chain_id);

1927
		status = dma_read(CSR(ch));
1928 1929
	}

1930 1931
	dma_write(status, CSR(ch));

1932 1933
	if (likely(dma_chan[ch].callback != NULL))
		dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1934

1935 1936 1937 1938
	return 0;
}

/* STATUS register count is from 1-32 while our is 0-31 */
1939
static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1940
{
1941
	u32 val, enable_reg;
1942 1943
	int i;

1944
	val = dma_read(IRQSTATUS_L0);
1945 1946 1947 1948 1949
	if (val == 0) {
		if (printk_ratelimit())
			printk(KERN_WARNING "Spurious DMA IRQ\n");
		return IRQ_HANDLED;
	}
1950 1951
	enable_reg = dma_read(IRQENABLE_L0);
	val &= enable_reg; /* Dispatch only relevant interrupts */
1952
	for (i = 0; i < dma_lch_count && val != 0; i++) {
1953 1954 1955
		if (val & 1)
			omap2_dma_handle_ch(i);
		val >>= 1;
1956 1957 1958 1959 1960 1961 1962 1963
	}

	return IRQ_HANDLED;
}

static struct irqaction omap24xx_dma_irq = {
	.name = "DMA",
	.handler = omap2_dma_irq_handler,
1964
	.flags = IRQF_DISABLED
1965 1966 1967 1968 1969 1970 1971
};

#else
static struct irqaction omap24xx_dma_irq;
#endif

/*----------------------------------------------------------------------------*/
1972 1973 1974 1975

static struct lcd_dma_info {
	spinlock_t lock;
	int reserved;
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1976
	void (*callback)(u16 status, void *data);
1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997
	void *cb_data;

	int active;
	unsigned long addr, size;
	int rotate, data_type, xres, yres;
	int vxres;
	int mirror;
	int xscale, yscale;
	int ext_ctrl;
	int src_port;
	int single_transfer;
} lcd_dma;

void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
			 int data_type)
{
	lcd_dma.addr = addr;
	lcd_dma.data_type = data_type;
	lcd_dma.xres = fb_xres;
	lcd_dma.yres = fb_yres;
}
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EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1999 2000 2001 2002 2003 2004 2005 2006 2007 2008

void omap_set_lcd_dma_src_port(int port)
{
	lcd_dma.src_port = port;
}

void omap_set_lcd_dma_ext_controller(int external)
{
	lcd_dma.ext_ctrl = external;
}
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Tony Lindgren 已提交
2009
EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2010 2011 2012 2013 2014

void omap_set_lcd_dma_single_transfer(int single)
{
	lcd_dma.single_transfer = single;
}
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Tony Lindgren 已提交
2015
EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

void omap_set_lcd_dma_b1_rotation(int rotate)
{
	if (omap_dma_in_1510_mode()) {
		printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
		BUG();
		return;
	}
	lcd_dma.rotate = rotate;
}
T
Tony Lindgren 已提交
2026
EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2027 2028 2029 2030 2031 2032 2033 2034 2035

void omap_set_lcd_dma_b1_mirror(int mirror)
{
	if (omap_dma_in_1510_mode()) {
		printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
		BUG();
	}
	lcd_dma.mirror = mirror;
}
T
Tony Lindgren 已提交
2036
EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2037 2038 2039 2040 2041 2042 2043 2044 2045 2046

void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
{
	if (omap_dma_in_1510_mode()) {
		printk(KERN_ERR "DMA virtual resulotion is not supported "
				"in 1510 mode\n");
		BUG();
	}
	lcd_dma.vxres = vxres;
}
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Tony Lindgren 已提交
2047
EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2048 2049 2050 2051 2052 2053 2054 2055 2056 2057

void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
{
	if (omap_dma_in_1510_mode()) {
		printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
		BUG();
	}
	lcd_dma.xscale = xscale;
	lcd_dma.yscale = yscale;
}
T
Tony Lindgren 已提交
2058
EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088

static void set_b1_regs(void)
{
	unsigned long top, bottom;
	int es;
	u16 w;
	unsigned long en, fn;
	long ei, fi;
	unsigned long vxres;
	unsigned int xscale, yscale;

	switch (lcd_dma.data_type) {
	case OMAP_DMA_DATA_TYPE_S8:
		es = 1;
		break;
	case OMAP_DMA_DATA_TYPE_S16:
		es = 2;
		break;
	case OMAP_DMA_DATA_TYPE_S32:
		es = 4;
		break;
	default:
		BUG();
		return;
	}

	vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
	xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
	yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
	BUG_ON(vxres < lcd_dma.xres);
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Tony Lindgren 已提交
2089 2090 2091

#define PIXADDR(x, y) (lcd_dma.addr +					\
		((y) * vxres * yscale + (x) * xscale) * es)
2092
#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
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Tony Lindgren 已提交
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2094 2095 2096 2097 2098 2099 2100 2101
	switch (lcd_dma.rotate) {
	case 0:
		if (!lcd_dma.mirror) {
			top = PIXADDR(0, 0);
			bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
			/* 1510 DMA requires the bottom address to be 2 more
			 * than the actual last memory access location. */
			if (omap_dma_in_1510_mode() &&
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Tony Lindgren 已提交
2102 2103
				lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
					bottom += 2;
2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161
			ei = PIXSTEP(0, 0, 1, 0);
			fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
		} else {
			top = PIXADDR(lcd_dma.xres - 1, 0);
			bottom = PIXADDR(0, lcd_dma.yres - 1);
			ei = PIXSTEP(1, 0, 0, 0);
			fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
		}
		en = lcd_dma.xres;
		fn = lcd_dma.yres;
		break;
	case 90:
		if (!lcd_dma.mirror) {
			top = PIXADDR(0, lcd_dma.yres - 1);
			bottom = PIXADDR(lcd_dma.xres - 1, 0);
			ei = PIXSTEP(0, 1, 0, 0);
			fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
		} else {
			top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
			bottom = PIXADDR(0, 0);
			ei = PIXSTEP(0, 1, 0, 0);
			fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
		}
		en = lcd_dma.yres;
		fn = lcd_dma.xres;
		break;
	case 180:
		if (!lcd_dma.mirror) {
			top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
			bottom = PIXADDR(0, 0);
			ei = PIXSTEP(1, 0, 0, 0);
			fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
		} else {
			top = PIXADDR(0, lcd_dma.yres - 1);
			bottom = PIXADDR(lcd_dma.xres - 1, 0);
			ei = PIXSTEP(0, 0, 1, 0);
			fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
		}
		en = lcd_dma.xres;
		fn = lcd_dma.yres;
		break;
	case 270:
		if (!lcd_dma.mirror) {
			top = PIXADDR(lcd_dma.xres - 1, 0);
			bottom = PIXADDR(0, lcd_dma.yres - 1);
			ei = PIXSTEP(0, 0, 0, 1);
			fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
		} else {
			top = PIXADDR(0, 0);
			bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
			ei = PIXSTEP(0, 0, 0, 1);
			fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
		}
		en = lcd_dma.yres;
		fn = lcd_dma.xres;
		break;
	default:
		BUG();
S
Simon Arlott 已提交
2162
		return;	/* Suppress warning about uninitialized vars */
2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191
	}

	if (omap_dma_in_1510_mode()) {
		omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
		omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
		omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
		omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);

		return;
	}

	/* 1610 regs */
	omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
	omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
	omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
	omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);

	omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
	omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);

	w = omap_readw(OMAP1610_DMA_LCD_CSDP);
	w &= ~0x03;
	w |= lcd_dma.data_type;
	omap_writew(w, OMAP1610_DMA_LCD_CSDP);

	w = omap_readw(OMAP1610_DMA_LCD_CTRL);
	/* Always set the source port as SDRAM for now*/
	w &= ~(0x03 << 6);
	if (lcd_dma.callback != NULL)
2192
		w |= 1 << 1;		/* Block interrupt enable */
2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210
	else
		w &= ~(1 << 1);
	omap_writew(w, OMAP1610_DMA_LCD_CTRL);

	if (!(lcd_dma.rotate || lcd_dma.mirror ||
	      lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
		return;

	w = omap_readw(OMAP1610_DMA_LCD_CCR);
	/* Set the double-indexed addressing mode */
	w |= (0x03 << 12);
	omap_writew(w, OMAP1610_DMA_LCD_CCR);

	omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
	omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
	omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
}

2211
static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229
{
	u16 w;

	w = omap_readw(OMAP1610_DMA_LCD_CTRL);
	if (unlikely(!(w & (1 << 3)))) {
		printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
		return IRQ_NONE;
	}
	/* Ack the IRQ */
	w |= (1 << 3);
	omap_writew(w, OMAP1610_DMA_LCD_CTRL);
	lcd_dma.active = 0;
	if (lcd_dma.callback != NULL)
		lcd_dma.callback(w, lcd_dma.cb_data);

	return IRQ_HANDLED;
}

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Tony Lindgren 已提交
2230
int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255
			 void *data)
{
	spin_lock_irq(&lcd_dma.lock);
	if (lcd_dma.reserved) {
		spin_unlock_irq(&lcd_dma.lock);
		printk(KERN_ERR "LCD DMA channel already reserved\n");
		BUG();
		return -EBUSY;
	}
	lcd_dma.reserved = 1;
	spin_unlock_irq(&lcd_dma.lock);
	lcd_dma.callback = callback;
	lcd_dma.cb_data = data;
	lcd_dma.active = 0;
	lcd_dma.single_transfer = 0;
	lcd_dma.rotate = 0;
	lcd_dma.vxres = 0;
	lcd_dma.mirror = 0;
	lcd_dma.xscale = 0;
	lcd_dma.yscale = 0;
	lcd_dma.ext_ctrl = 0;
	lcd_dma.src_port = 0;

	return 0;
}
T
Tony Lindgren 已提交
2256
EXPORT_SYMBOL(omap_request_lcd_dma);
2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267

void omap_free_lcd_dma(void)
{
	spin_lock(&lcd_dma.lock);
	if (!lcd_dma.reserved) {
		spin_unlock(&lcd_dma.lock);
		printk(KERN_ERR "LCD DMA is not reserved\n");
		BUG();
		return;
	}
	if (!enable_1510_mode)
2268 2269
		omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
			    OMAP1610_DMA_LCD_CCR);
2270 2271 2272
	lcd_dma.reserved = 0;
	spin_unlock(&lcd_dma.lock);
}
T
Tony Lindgren 已提交
2273
EXPORT_SYMBOL(omap_free_lcd_dma);
2274 2275 2276 2277 2278

void omap_enable_lcd_dma(void)
{
	u16 w;

T
Tony Lindgren 已提交
2279 2280
	/*
	 * Set the Enable bit only if an external controller is
2281 2282 2283 2284 2285
	 * connected. Otherwise the OMAP internal controller will
	 * start the transfer when it gets enabled.
	 */
	if (enable_1510_mode || !lcd_dma.ext_ctrl)
		return;
2286 2287 2288 2289 2290

	w = omap_readw(OMAP1610_DMA_LCD_CTRL);
	w |= 1 << 8;
	omap_writew(w, OMAP1610_DMA_LCD_CTRL);

2291 2292
	lcd_dma.active = 1;

2293 2294 2295 2296
	w = omap_readw(OMAP1610_DMA_LCD_CCR);
	w |= 1 << 7;
	omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
T
Tony Lindgren 已提交
2297
EXPORT_SYMBOL(omap_enable_lcd_dma);
2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312

void omap_setup_lcd_dma(void)
{
	BUG_ON(lcd_dma.active);
	if (!enable_1510_mode) {
		/* Set some reasonable defaults */
		omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
		omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
		omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
	}
	set_b1_regs();
	if (!enable_1510_mode) {
		u16 w;

		w = omap_readw(OMAP1610_DMA_LCD_CCR);
T
Tony Lindgren 已提交
2313 2314
		/*
		 * If DMA was already active set the end_prog bit to have
2315 2316 2317 2318 2319
		 * the programmed register set loaded into the active
		 * register set.
		 */
		w |= 1 << 11;		/* End_prog */
		if (!lcd_dma.single_transfer)
T
Tony Lindgren 已提交
2320
			w |= (3 << 8);	/* Auto_init, repeat */
2321 2322 2323
		omap_writew(w, OMAP1610_DMA_LCD_CCR);
	}
}
T
Tony Lindgren 已提交
2324
EXPORT_SYMBOL(omap_setup_lcd_dma);
2325 2326 2327

void omap_stop_lcd_dma(void)
{
2328 2329
	u16 w;

2330
	lcd_dma.active = 0;
2331 2332 2333 2334 2335 2336 2337 2338 2339 2340
	if (enable_1510_mode || !lcd_dma.ext_ctrl)
		return;

	w = omap_readw(OMAP1610_DMA_LCD_CCR);
	w &= ~(1 << 7);
	omap_writew(w, OMAP1610_DMA_LCD_CCR);

	w = omap_readw(OMAP1610_DMA_LCD_CTRL);
	w &= ~(1 << 8);
	omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2341
}
T
Tony Lindgren 已提交
2342
EXPORT_SYMBOL(omap_stop_lcd_dma);
2343

2344
/*----------------------------------------------------------------------------*/
2345

2346 2347
static int __init omap_init_dma(void)
{
T
Tony Lindgren 已提交
2348
	unsigned long base;
2349 2350
	int ch, r;

2351
	if (cpu_class_is_omap1()) {
T
Tony Lindgren 已提交
2352
		base = OMAP1_DMA_BASE;
2353
		dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2354
	} else if (cpu_is_omap24xx()) {
T
Tony Lindgren 已提交
2355
		base = OMAP24XX_DMA4_BASE;
2356
		dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2357
	} else if (cpu_is_omap34xx()) {
T
Tony Lindgren 已提交
2358
		base = OMAP34XX_DMA4_BASE;
2359
		dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2360
	} else if (cpu_is_omap44xx()) {
T
Tony Lindgren 已提交
2361
		base = OMAP44XX_DMA4_BASE;
2362
		dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2363 2364 2365 2366
	} else {
		pr_err("DMA init failed for unsupported omap\n");
		return -ENODEV;
	}
2367

T
Tony Lindgren 已提交
2368 2369 2370
	omap_dma_base = ioremap(base, SZ_4K);
	BUG_ON(!omap_dma_base);

2371 2372 2373 2374
	if (cpu_class_is_omap2() && omap_dma_reserve_channels
			&& (omap_dma_reserve_channels <= dma_lch_count))
		dma_lch_count = omap_dma_reserve_channels;

2375 2376
	dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
				GFP_KERNEL);
T
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2377 2378 2379 2380
	if (!dma_chan) {
		r = -ENOMEM;
		goto out_unmap;
	}
2381 2382 2383 2384 2385

	if (cpu_class_is_omap2()) {
		dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
						dma_lch_count, GFP_KERNEL);
		if (!dma_linked_lch) {
T
Tony Lindgren 已提交
2386 2387
			r = -ENOMEM;
			goto out_free;
2388 2389 2390
		}
	}

2391 2392
	if (cpu_is_omap15xx()) {
		printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2393 2394
		dma_chan_count = 9;
		enable_1510_mode = 1;
2395
	} else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2396
		printk(KERN_INFO "OMAP DMA hardware version %d\n",
2397
		       dma_read(HW_ID));
2398
		printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2399 2400 2401 2402 2403 2404
		       (dma_read(CAPS_0_U) << 16) |
		       dma_read(CAPS_0_L),
		       (dma_read(CAPS_1_U) << 16) |
		       dma_read(CAPS_1_L),
		       dma_read(CAPS_2), dma_read(CAPS_3),
		       dma_read(CAPS_4));
2405 2406 2407 2408
		if (!enable_1510_mode) {
			u16 w;

			/* Disable OMAP 3.0/3.1 compatibility mode. */
2409
			w = dma_read(GSCR);
2410
			w |= 1 << 3;
2411
			dma_write(w, GSCR);
2412 2413 2414
			dma_chan_count = 16;
		} else
			dma_chan_count = 9;
2415 2416 2417 2418 2419 2420 2421 2422
		if (cpu_is_omap16xx()) {
			u16 w;

			/* this would prevent OMAP sleep */
			w = omap_readw(OMAP1610_DMA_LCD_CTRL);
			w &= ~(1 << 8);
			omap_writew(w, OMAP1610_DMA_LCD_CTRL);
		}
2423
	} else if (cpu_class_is_omap2()) {
2424
		u8 revision = dma_read(REVISION) & 0xff;
2425 2426
		printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
		       revision >> 4, revision & 0xf);
2427
		dma_chan_count = dma_lch_count;
2428 2429 2430 2431 2432 2433 2434 2435 2436
	} else {
		dma_chan_count = 0;
		return 0;
	}

	spin_lock_init(&lcd_dma.lock);
	spin_lock_init(&dma_chan_lock);

	for (ch = 0; ch < dma_chan_count; ch++) {
2437
		omap_clear_dma(ch);
2438 2439 2440 2441 2442 2443
		dma_chan[ch].dev_id = -1;
		dma_chan[ch].next_lch = -1;

		if (ch >= 6 && enable_1510_mode)
			continue;

2444
		if (cpu_class_is_omap1()) {
T
Tony Lindgren 已提交
2445 2446 2447 2448
			/*
			 * request_irq() doesn't like dev_id (ie. ch) being
			 * zero, so we have to kludge around this.
			 */
2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460
			r = request_irq(omap1_dma_irq[ch],
					omap1_dma_irq_handler, 0, "DMA",
					(void *) (ch + 1));
			if (r != 0) {
				int i;

				printk(KERN_ERR "unable to request IRQ %d "
				       "for DMA (error %d)\n",
				       omap1_dma_irq[ch], r);
				for (i = 0; i < ch; i++)
					free_irq(omap1_dma_irq[i],
						 (void *) (i + 1));
T
Tony Lindgren 已提交
2461
				goto out_free;
2462 2463 2464 2465
			}
		}
	}

2466
	if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2467 2468 2469
		omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
				DMA_DEFAULT_FIFO_DEPTH, 0);

2470 2471 2472 2473 2474 2475 2476 2477
	if (cpu_class_is_omap2()) {
		int irq;
		if (cpu_is_omap44xx())
			irq = INT_44XX_SDMA_IRQ0;
		else
			irq = INT_24XX_SDMA_IRQ0;
		setup_irq(irq, &omap24xx_dma_irq);
	}
2478

2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491
	/* Enable smartidle idlemodes and autoidle */
	if (cpu_is_omap34xx()) {
		u32 v = dma_read(OCP_SYSCONFIG);
		v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
				DMA_SYSCONFIG_SIDLEMODE_MASK |
				DMA_SYSCONFIG_AUTOIDLE);
		v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
			DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
			DMA_SYSCONFIG_AUTOIDLE);
		dma_write(v , OCP_SYSCONFIG);
	}


2492 2493 2494 2495
	/* FIXME: Update LCD DMA to work on 24xx */
	if (cpu_class_is_omap1()) {
		r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
				"LCD DMA", NULL);
2496 2497 2498
		if (r != 0) {
			int i;

2499 2500 2501 2502
			printk(KERN_ERR "unable to request IRQ for LCD DMA "
			       "(error %d)\n", r);
			for (i = 0; i < dma_chan_count; i++)
				free_irq(omap1_dma_irq[i], (void *) (i + 1));
T
Tony Lindgren 已提交
2503
			goto out_free;
2504 2505 2506 2507
		}
	}

	return 0;
T
Tony Lindgren 已提交
2508 2509 2510 2511 2512 2513 2514 2515

out_free:
	kfree(dma_chan);

out_unmap:
	iounmap(omap_dma_base);

	return r;
2516 2517 2518 2519
}

arch_initcall(omap_init_dma);

2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532
/*
 * Reserve the omap SDMA channels using cmdline bootarg
 * "omap_dma_reserve_ch=". The valid range is 1 to 32
 */
static int __init omap_dma_cmdline_reserve_ch(char *str)
{
	if (get_option(&str, &omap_dma_reserve_channels) != 1)
		omap_dma_reserve_channels = 0;
	return 1;
}

__setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);

2533